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Hi Brendan, Austin and Everyone, Thanks for addressing my question. I would just like to add that I have been told in private communication that Austin was away on vacation and thus was unable to answer my initial question, so I would like to retract the (rash) statement I made in my last posting about him not responding. Thanks for the info, Ljubisa Brendan Cullen wrote: > Paul has a point when he says that changing Vccint should cause a change in > Iccint. This is in our plans for the Web Power Tool (WPT). When we have > sufficient silicon-based data we will add the appropriate modelling to the WPT. > > Changing Vccint (in V4) does also affect the sub-threshold leakage current - > though our measurements and analysis todate suggest it is not the simple square > relationship that Paul suggests. Again - we are continuing with our analysis - > which will be reflected in time in the WPT if (and only if) the effect is > significant. (It's of no benefit to the WPT user for us to model current > variations due to certain small effects if the normal variation from part to > part will swamp such tiny improvements.) > > Brendan > > "Paul Leventis (at home)" wrote: > > > Hi Brendan, > > > > > In terms of "PVT" - Process, Voltage & Temperature : In the WPT currently > > > you can, for V4 FX devices, vary Vccint and the ambient temperature. > > > > When I enter 1.25V vs. 1.20V in WPT 4.1, I'm given 687 mW vs. 660 mW of > > VccInt static power for a LX80, in addition to the 234 mW of VccAux power. > > > > Similarly, for some random amount of logic utlization, I get 2727 mW vs. > > 2618 mW of dynamic power. > > > > It seems to me that all the tool is doing is increasing the V in P = VI. > > However, increasing V should (a) increase dynamic current draw roughly > > linearly and (b) increase sub-threshold leakage by the square of 1.25/1.2. > > Neither of these effects appear to be modeled. > > > > Regards, > > > > Paul Leventis > > Altera Corp.Article: 83626
ahosyney wrote: > I just want to ask how will you enter your 1000 frequancy pins, how bin, not pin. -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 83627
"Frank de Groot" <franciad@online.no> wrote in message news:0F3de.8681$SL4.194828@news4.e.nsc.no... >I am looking for the cheapest PowerPC G4 PCI coprocessor board for the PC. > > All boards I have found are for military/medical applications and they > sell > for very inflated prices compared to a Mac Mini. > > When a Mac Mini can sell for 500 USD, shouldn't it be possible to have a > PCI > card with a 1 GHz G4 available for 300 USD? Of course it's possible - look at all the stuff in the Mac Mini besides the G4 subsystem for $500 retail. > > Volume and R&D cost is the issue here of course.. It's way more the volume than the R&D. I would bet that for companies making G4 PCI boards, which is a not a consumer market by any means, their cost of the bare parts alone is more than $300 in the kind of volumes they'd buy in. It's amazing when you cross from the consumer market to non-consumer markets the price differentials, and it's not companies inflating their costs, it's just the economies of scale. > > Anyonecould point me to the cheapest G4 PowerPC board(s) available? (1000 > USD would be my limit). If you are buying volume, talk to the board makers you have found and I'll bet you find their price comes down significantly with volume. If you're not, your best bet would be to look for some kind of development board as they are often subsidized by the chip makers. If you live with the latencies and inefficiences of Ethernet, you could buy the Mac Mini and ethernet it in, but my guess would be you'd spend more time running the data over Ethernet and the protocol stacks than you would number crunching. Oh, and if you want some real number crunching, we sell TigerSHARC DSP PCI boards (www.bittware.com), but good luck on the $1000 price :-) ------ Ron Huizen BittWareArticle: 83628
I need 1000 frequency "bins", where each bin is a descrete frequency. As Thomas Womack pointed out above, it is beter defined as a N-point DFT with 1000 frequency bins, where N = 1024. For each sample, every microsecond, there is 24-bits of data lets call that x(n). During that microsecond there must be 1000 MACS in parallel to calculate the N=1024 DFT. This would happen for 1024 samples to calculate the N-point DFT. I hope that is a better description. Thanks for the input.Article: 83629
Ljubisa, No offense taken. I am pleased that your questions have been adequately addressed. My niece had her wedding in Kauai over the weekend, so we flew out Friday morning, and flew back Monday. Wasn't nearly long enough to be in paradise! But I am slightly more mellow than usual just due to the sun, beaches, good friends, family and a few glasses on champagne. AustinArticle: 83630
Your design sounds like it *should* be a simple interface where you need both devices to have compatible clock-to-out and in-to-clock setup times. Is there something that makes this system less simple? Are you running the ADI chip from something that *isn't* the 65 MHz FPGA clock? Or does the ADI chip provide an interface that ISN'T relative to the ADI clock? Your subject is "gated clock problem" but you only loosely talk about clock and control propagation through a LUT. Are you generating a gated clock for the ADI device? If so, does the control signal always change from a "valid clock" to an "invalid clock" state leaving the clock level the same? If the rising edge of the clock registers the enable, the "gating" should be done at the high level; turning off the clock by forcing it low *when it is high* will give you a "runt pulse" that could mess up your system. I'm guessing here because your detail is limited - it's not clear what signals are a problem, what clocking is used, or what the I/O requirements are. "Wenju Fu" <fwj@nmrs.ac.cn> wrote in message news:ee8dffe.-1@webx.sUN8CHnE... > I posted following message, but nobody respond(I don't know the reason, maybe it is too naive). I I post it here again, wish someone could help me. > > I am using VirtexE to communication with an ADI's chip. The interface include, write, read, Data, and Address. I wish FPGA communication with the chip on FPGA main clock, which is up to 65MHz. I used a synchronized signal gated with the Clock to generate the write, read signal. Data and Address signal are synchronized. The problem is: 1) write/read signal often generate one more period than what I needed. although I could overcome it by adjust control signal's edge sensitivity, but it maybe reappear when I resynthesize the design. The reason is time delay of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Can I limit delay difference of the 2 inputs to an acceptable level? if it is, How could I do? 2) the timing of address, data and write/read is inconsistent with the timing required by ADI. I could delay some signal by add buffers or invertors. But I am afraid if it is work well if I add this modular to the top design. Is there any better way? > > if I generate the w/r signal synchronized with the clock, the problem may do not exist. But I should drive the clock twice high, I don't know if VirtexE can work well on 125MHz. > > Thank you for your advice.Article: 83631
What is this? http://www.altera.com/corporate/cust_successes/customer_showcase/csh-seventech_lp.html With VGA - LAN - I/O and more and also a C++ software dev kit RobertArticle: 83632
Do you have to supply the actual 360 MHz as a clock with your LVDS data? If you supply a lower frequency clock or no clock at all, consider the DDR capability available in the families with DCMs to improve the output rate by a factor of 2. 720 Mbits/sec? "Benjamin Menküc" <benjamin@menkuec.de> wrote in message news:d589f7$d17$03$1@news.t-online.com... > Hi, > > I am running my design now with two dcms cascaded. The max. clk2x output > of my device is 360 MHz, which I am using now. That gives me for my LCD > panel a frame rate of about 54 Hz, still not too much. Maybe I have to > switch to a faster speed grade or experiment with external clocks. > > regards, > BenjaminArticle: 83633
TheMightyShaman wrote: > > Hi Duane, how are you? > > Ok, I had the SP2, patched the files and tied the external ports to 0 > touse only the PLB connection. I even imported the core in EDK, but it > seems not to work correctly. I'm wondering if it depends on how I > clocked the DDR and the system, with the TWO classical DCM tied to 100 > MHz both for the bus and for the DDR DCM... > > How did you connected the DCMs? > I modified a little the ddr_clocks reference design. I added that diff to the same location as the other files. Notice that it is against an EDK6.2 version of that file. Also, I found and fixed one bug in read_data_path.vhd, though this only affects the external interface. The bd_top.vhd file shows one example of how to connect everything. You probably should run this simulation to make sure everything works, then modify it to zero out the external interface and try it again. I also added an example system.mhs file to show how they are connected in a real system. And finally, an example system_top.vhd file, to show the top level structure of how they connect to the pins.Article: 83634
Hello I noticed the University of Queensland distribution of uClinux for the Xilinx Microblaze soft processor core. Does anyone know of an open source embedded linux distribution for the PPC 405 cores in V2Pro and V4? Thank you, PeteArticle: 83635
Thomas, John, OK, I'll have one last go at dispelling the 'pyramid of capacitors' myth. So, you've already downloaded the Murata impedance calculator right? The one from http://www.murata.com/designlib/mcsil.html Draw the impedance curve for a 0402 X5R 1u 6.3v capacitor. Now draw the impedance for an 0603 X5R 2u2 6.3v cap. Notice how the 0402 cap has a lower impedance above about 8MHz. Now think about what you're trying to bypass. The logic in a V2PRO has risetimes of the order of 1ns (probably less), the I/Os can switch in about 3 or 4 ns. Lower impedance at <8MHz isn't gonna help power these <5ns switching times. Now experiment with 0603 caps and 0402 caps with different capacitance, and see which perform better at the frequencies of interest, (say) 100MHz and above. You'll find it makes bugger all difference. Next remember that when you use these parts, you'll likely more than double the inductance just by the PCB track, vias, BGA routing. So, the crossover point drops to about 4MHz from 8MHz. So, I recommend, pick one value in the smallest size you can use. Because they're small you can use more of them, this is good because in parallel the impedance goes down at high frequencies as well as low. When you've done that, use a few 0805s to sort out any low frequency problems, you can get 22uF ones. Two different ceramic caps are enough to sort the whole thing. Your power supply should also have bulk output capacitance. As for capacitor packs, be aware that adjacent caps in the pack have mutual capacitance. I wouldn't share the caps in one pack between different power supplies as noise will couple between the supplies especially at the switching rates mentioned above. And especially Vccaux. And always try to get some capacitance on the back side of the board from the FPGA. Get a new board assembler if they don't like it. I hope this helps. Cheers, Syms.Article: 83636
Pete wrote: > Does anyone know of an open source embedded linux distribution for the PPC > 405 cores in V2Pro and V4? MontaVista -- Dan HenryArticle: 83637
Austin, I guess I am concerned that all of these "imperceptible" changes in power over temperature that are calculated as ZERO in the power calculator could actually add up to be something. Are you saying that the combination of VCCAUX, multiple DCMs and multiple processors will still result in zero power difference between 25 degrees C and 85 degrees C for those functions? Thanks, JDArticle: 83638
"Wenju Fu" <fwj@nmrs.ac.cn> wrote in message news:ee8dffe.-1@webx.sUN8CHnE... > I posted following message, but nobody respond(I don't know the reason, maybe it is too naive). I I post it here again, wish someone could help me. > No-one responded because gated clocks are anathema to this newsgroup! Don't gate the clock. No, really, don't. You could consider gating the outputs of FFs clocked on opposite edges to get what you want, but after considering it, don't do that either. The answer is to double your clock with a DLL, and your problems will melt away! Cheers, Syms. p.s. Don't gate clocks.Article: 83639
JD, It is of course not identically 0, but it is small enough that variations from part to part will mask the effect. So the process margin is much larger than the variation, so the variation is of no importance. Austin JD_Design wrote: > Austin, > > I guess I am concerned that all of these "imperceptible" changes in > power over temperature that are calculated as ZERO in the power > calculator could actually add up to be something. Are you saying that > the combination of VCCAUX, multiple DCMs and multiple processors will > still result in zero power difference between 25 degrees C and 85 > degrees C for those functions? > > Thanks, > > JD >Article: 83640
Pete wrote: > Hello > > I noticed the University of Queensland distribution of uClinux for the > Xilinx Microblaze soft processor core. > > Does anyone know of an open source embedded linux distribution for the PPC > 405 cores in V2Pro and V4? > > Thank you, > > Pete Take a look at http://www.denx.de It was the version of Linux that came with the Avnet development board that I have. It is not uClinux, it is Linux. Regards, John McCaskillArticle: 83641
Bart, consider time / frequency as a third dimension. You have a certain job to do in a given time. Then look at the perforamnce of your multiplier, registers, etc, and you find that they will work at multiple 100 MHz. Then get creative and do certain things sequentially, and other things in parallel. You have an enormous amount of creative freedom, and pipelining is essentially free in an FPGA. Remember, any circuit that does not work close to its speed limit represents waste. Peter AlfkeArticle: 83642
Hi Preben, This post is not only a reply to your question, but also my first try using Outlook as a newsreader. If the formatting is odd, please forgive the mess! I'm eager to see what this looks like when it's posted... Your question leads me to belive you are not familiar with the actual analog behavior of a flip flop. I have some information, complete with famous quotes, located at: http://www.engr.sjsu.edu/~crabill/module03.pdf Hopefully this will give you a bit of background. If you are using a flip flop, you need to make sure you satisfiy the input setup and input hold requirements of the flip flop -- otherwise, the flip flop won't work like you expect! If you have a flip flop, with some parameters Tsu, Th, and Tq, you might visualize that: 1. Adding delay on the output path increases Tq, but leaves Tsu and Th unchanged. 2. Adding delay on the input path increases Tsu, reduces Th, and leaves Tq unchanged. 3. Adding delay on the clock path decreases Tsu, increases Th, and increases Tq. Xilinx provides input delay mechanisms so that you can implement option #2, above. It is also the case that by way of a digital clock manager, you can arrive at implementations of #3, above -- or the complement of #3, above, where you effectively remove delay on the clock path and achieve the opposite effect. Your original question, I believe, is "Why?". People use these features to modify the I/O timing -- Tq, Tsu, and Th of the input and output flip flops. "Why?" To achiveve a specific I/O timing, required by design, or required by specification. Or, to simply make life easier... Let me give you a specific example of how you might apply these techniques to make life easier. Let's say you are doing a fully synchronous design, like a PCI bus. In general, to ensure proper operation of the bus, you need to not only analyze the internal behavior of each chip, but how they interface to each other -- synchronously, with a distributed reference clock. You need to satisfy the setup and hold requirements of the input flip flops of each chip. There are two sets of calculations that are required. One, to check the input setup. Two, to check the input hold. If you look at the equations in the presentation I referenced above, you will see that you can construct something that is guaranteed to satisfy the hold time requirements -- by increasing the input delay, to get a zero (or slightly negative) hold time -- thereby eliminating the need to even check it. A sum of real physical delays is always going to be greater than zero (or slightly negative). That leaves you only needing to check the input setup. In fact, this idea is applied inside Xilinx FPGAs as well. All of the flip flops in the FPGA are designed to have zero (or slightly negative) hold time, when clocked with a single global clock signal. This ensures a fully synchronous design with one clock will not have hold violations on any flip flops. Hope that helps, EricArticle: 83643
Hi Markus, >> Hi Markus, >> I use 1k pullup ,pulldown. >> I had some problems with 10k pulldown on TCK. >> The following is from "ALTERA Support Find Answers": > > Hi Thomas, > > thank you for the hint. > > Today I have tried 1k pulldown on TCK. The result was even worse. > The TCK signal breaks down to 2V. > I get the jtag comm errors earlier. > > Maybe my USB Blaster has a defect. > > With the Byteblaster MV it works also with 1k on TCK. I had a colleague do some measurements today on a NIOS Cyclone board with both an USB Blaster and a Masterblaster. Pictures are attached. As you can see, on the NIOS board, the USB Blaster reaches 2.16V, and the Masterblaster 2.54V. This is on a working board with no known Signaltap problems. Does this look familiar or is it way off? Also, if you have an Altera NIOS board lying around, could you try to compare the waveforms between your USB Blaster and the diagram attached? If they are way off, you may indeed have a problem with the USB Blaster. Best regards, BenArticle: 83644
During the latest Xilinx netseminar on Power the Xilinx ML481 board was mentioned as a good way for users to evalute their Virtex4 designs against stratix2. Does anyone know if this development kit is something that is purchased by customers, or is it only available at the rocket labs?Article: 83645
Hi, Firstly, I'm a newbie at VHDL. I'm using 2 constants to derive a valid range of system clock periods: constant ENC_FREQ_MIN : integer := 200; -- 200 Hz constant ENC_FREQ_MAX : integer := 3500; -- 3500 Hz constant ENC_PERIOD_RANGE : integer := 50e6 /(ENC_FREQ_MAX - ENC_FREQ_MIN); -- 50MHz system clock I chose integers as I want the freedom to enter real frequencies rather than specifying bit array strings and working out their size plus I need to difference successive encoder periods to give +ve & -ve values My problem is that I want a monitor signal which outputs the encoder period difference but only the lower order bits up to 8 bits, any greater than that I just want the 8 bit output to saturate. How I can easily convert this difference (that has "unknown" size) to a saturated 8 bit number (+/-7 bits) ? Thanks in advance DaveArticle: 83646
Is this OK? if difference > 255 then saturated <= 255; else saturated <= difference mod 256; end if; Cheers, Syms. p.s. You may like to investigate the newsgroup comp.lang.vhdl . <dave_baker_100@yahoo.co.uk> wrote in message news:1115232021.444658.259310@g14g2000cwa.googlegroups.com... > Hi, > > Firstly, I'm a newbie at VHDL. > I'm using 2 constants to derive a valid range of system clock periods: > > constant ENC_FREQ_MIN : integer := 200; -- 200 Hz > constant ENC_FREQ_MAX : integer := 3500; -- 3500 Hz > constant ENC_PERIOD_RANGE : integer := 50e6 /(ENC_FREQ_MAX - > ENC_FREQ_MIN); -- 50MHz system clock > > I chose integers as I want the freedom to enter real frequencies rather > than specifying bit array strings and working out their size plus I > need to difference successive encoder periods to give +ve & -ve values > > My problem is that I want a monitor signal which outputs the encoder > period difference but only the lower order bits up to 8 bits, any > greater than that I just want the 8 bit output to saturate. > > How I can easily convert this difference (that has "unknown" size) to a > saturated 8 bit number (+/-7 bits) ? > > Thanks in advance > Dave >Article: 83647
Thanks! My application will do checks for < -128 & > 127 but the 'mod' is exactly what I need. Thanks also for the VHDL newsgroup suggestion.Article: 83648
No worries Dave. I also recommend library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; and stay clear of the other libraries. This is a great starting point:- http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf Yer man Jim knows his stuff! Cheers, Syms. <dave_baker_100@yahoo.co.uk> wrote in message news:1115232842.747575.212240@z14g2000cwz.googlegroups.com... > Thanks! > My application will do checks for < -128 & > 127 but the 'mod' is > exactly what I need. > > Thanks also for the VHDL newsgroup suggestion. >Article: 83649
Symon - thanks for that little gem! I have a couple of off-subject questions you may be able to answer: 1) Are there any really good books that relate VHDL to FPGA synthesis ? 2) Are there any rule-of-thumb measurements for the max. no. of lines of code in a clocked process statement ? Many thanks Dave
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