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What fitter is used ? I had a similar problem (which is not solved yet) with Synplify. I used the following attributes as workaround: SIGNAL ls_ddr_state, next_ls_ddr_state : ddr_state_type; attribute syn_keep : boolean; attribute syn_keep of ls_ddr_state : signal is true; attribute nomerge : boolean; attribute nomerge of ls_ddr_state : signal is true; Rgds Andr=E9 Mike Treseler schrieb: > Tim Verstraete wrote: > > > I made a FSM with about 23 states (not the first time i've done vhdl > > work, but never had this problem before with FSM =3D> in fact it is not > > really a problem) and i used following scheme: > ... > > and i was just wondering why XST does not find my FSM???? > > Perhaps XST is expecting a one or two process format. > > But as you said, this is not really a problem if > sims and runs as you expect. A few dubious statistics > are not worth much extra work. >=20 > -- Mike TreselerArticle: 89251
... sorry if i'm repeating myself :-) Design F/X Pin Assignment tracks IO standards as they change, allows for interface driven design and much more with real-time Xilinx FPGA DRC's. And it generates UCF files on demand to help address these kinds of issues. It's free for < 600 pins and can be downloaded from our website, http://www.prodacc.com - help file in the install directory. Have fun ! M.Article: 89252
Al Clark wrote: >>Apparently the difference has to do with the WP pin! Hmmm, this info came from my colleague when I mentioned this thread in passing. He recalled that there was a difference with the WP pin... ...however we've just checked the 25P10 and EPCS1 datasheets and they do indeed look pin-compatible w.r.t. the WP pin, so we're at a loss to explain. Sorry 'bout the red herring... Regards, MarkArticle: 89253
Paul Hartke wrote: >Have you considered XCL as the interface? > >"Xilinx CacheLink (XCL) is a high performance solution for external >memory >accesses." http://www.xilinx.com/ise/embedded/mb_ref_guide.pdf > > > No; but IŽll give it a try. I Just thought that multiplexing two chache links shoudl be far more difficult than multiplexing two LMB interfaces, but that was only un undocumented thought. I will document myself now. Thank you very much, ZaraArticle: 89254
Hi, I performed a post route simulation using FPGA Advantage tools and
Modelsim 6.0c.
The place and route process ended without errors.
I compiled the simprim library as indicated in the help provided and I
used the following command in modelsim:
vsim -L RSA_lib -L simprim_v -L simprim_v -l transcript.txt -i
-multisource_delay latest -sdftyp
/test_FIOS_with_FSM/uut/=/home/pipino/Progetti/Elsag/RSA/precisionProject/FIOS_with_FSM_impl_1/FIOS_with_FSM_out.sdf
-t ps +typdelays -foreign {hdsInit
/mentor/software/fpgadv70/Hds/resources/downstream/modelsim/ModelSim_32Bit.dll}
-pli
/mentor/software/fpgadv70/Hds/resources/downstream/modelsim/ModelSim_32Bit.dll
glbl.glbl RSA_lib.test_FIOS_with_FSM
where test_FIOS_with_FSM is the module name and uut is the name of the
istantiated module that currently simulated.
This command give me the following error:
** Error: (vsim-SDF-3250)
/home/pipino/Progetti/Elsag/RSA/precisionProject/FIOS_with_FSM_impl_1/FIOS_with_FSM_out.sdf(60):
Failed to find INSTANCE '/test_FIOS_with_FSM/uut/READY/GTS_OR'.
# ** Error: (vsim-SDF-3250)
/home/pipino/Progetti/Elsag/RSA/precisionProject/FIOS_with_FSM_impl_1/FIOS_with_FSM_out.sdf(2008):
Failed to find INSTANCE
'/test_FIOS_with_FSM/uut/w_index_i(0)/COUTUSED'.
# ** Error: (vsim-SDF-3250)
/home/pipino/Progetti/Elsag/RSA/precisionProject/FIOS_with_FSM_impl_1/FIOS_with_FSM_out.sdf(2094):
Failed to find INSTANCE
'/test_FIOS_with_FSM/uut/w_index_i(2)/COUTUSED'.
# ** Error: (vsim-SDF-3250)
/home/pipino/Progetti/Elsag/RSA/precisionProject/FIOS_with_FSM_impl_1/FIOS_with_FSM_out.sdf(2209):
Failed to find INSTANCE
'/test_FIOS_with_FSM/uut/w_index_i(4)/COUTUSED'.
# ** Error: (vsim-SDF-3250)
/home/pipino/Progetti/Elsag/RSA/precisionProject/FIOS_with_FSM_impl_1/FIOS_with_FSM_out.sdf(2361):
Failed to find INSTANCE
'/test_FIOS_with_FSM/uut/w_index_j(0)/COUTUSED'.
# ** Warning: (vsim-SDF-3432)
/home/pipino/Progetti/Elsag/RSA/precisionProject/FIOS_with_FSM_impl_1/FIOS_with_FSM_out.sdf:
This file is probably applied to the wrong instance.
# Ignoring subsequent missing instances from this file.
# ** Warning: (vsim-SDF-3441)
/home/pipino/Progetti/Elsag/RSA/precisionProject/FIOS_with_FSM_impl_1/FIOS_with_FSM_out.sdf:
Failed to find 641 out of the 39247 instances from this file.
I don't understance where the GTS_OR and COUTUSED elements can be
found.
Any help will be appreciated
Article: 89255Hi! Has anyone successfully used opencores PCI in FPGA desings? I have seen this question posted a few years ago and I would like to see if there are new answers to it.Article: 89256
Hello Guys,
I am having an IP which has 2 interface master and slave interface but
there single external bus.
To adapt to this architecture i using an trisatate implementation of
bus. But the problem is
that once i have the tristating of bus , signal interfacing to slave
interface of IP gets grounded.
I have observed it in chipscope (probing the EDF) but if i donot have
tristating the IP is working fine.
I tried all ways but still i could not solve the problem.
I will explain one of the signal interface: HTRANS
Global external bus signal is HTRANS. This signal connect directly to
slave HTRANS
since its a input and there is iHTRANSOut signal in master part which
is output and i have
this to connect to same external HTRANS.
Code goes this way:
always @(posedge iHCLKBUF)
begin
if (nSYSRST == 1'b0)
AHBMasterEnable <= 1'b0;
else
if (HREADY == 1'b1)
AHBMasterEnable <= HGRANT[2];
end
assign HTRANS = (AHBMasterEnable == 1'b1) ? iHTRANSOut : 2'bzz;
Is there any problem in the tristate implementation?
Waiting for your reply,
Thanks in advance
Williams
Article: 89257depends.. try entering 01101 into VHDL and see what you get :-) you are either exact or error. true or false 1 or 0 this is binary logic.. 1101 maybe -3 .. but 01101 isn't Simon "Peter Harrison" <peteh@cannock.ac.uk> wrote in message news:dforh8$qot$1@south.jnrs.ja.net... > > "Simon Peacock" <simon$actrix.co.nz> wrote in message > news:431ebdbc@news2.actrix.gen.nz... > > almost right > > 01101 /= -3 > > 11101 = -3 > > > > you need to sign extend ;-) > > > > Simon > > > Surely not for the example given. The fifth bit there was the carry bit from > a 4 bit operation. Thus the answer only takes 4 bits and is correct. The > carry bit is used for error detection. If the carry into the MSB and the > carry out of it are different, the 2's complement operation has overflowed. > The overflow bit in a processor is just the result of an exclusive or on the > two carries. > > Pete Harrison > > Sylvain's original sums: > > >> Signed and unsigned addition are the same. Their results is to be > >> interpreted differently though ... > >> > >> Let's says the number are 4 bits unsigned : > >> > >> 1001 = 9 > >> 0100 = 4 > >> -------- > >> 01101 = 13 > >> > >> now if they are 4 signed : > >> 1001 = -7 > >> 0100 = 4 > >> --------- > >> 01101 = -3 > >> > >> > >Article: 89258
Austin wrote: > > It really is 5pF across 100 ohms > As presently documented in your datasheets and IBIS files, it's really two 10 pFs in shunt to ground across a 100 ohm +/-20% R. It may appeal to your inner marketeer to call it 5 pF, but that won't make your parts work any better. If you're going to continue to 'correct' folks who quote your own documentation, at least have the technical honesty to point out that modeling two shunt C's as an across-the-pair 1/2 C is ONLY valid if the input signal is perfectly differential. Here's to hoping that when you eventually publish S3E IBIS and SSO info, those slimmed-down DCI-less I/O buffers have a lower C. ( And I'd still love to see some of the smaller S3E parts appear in a ground-paddle VQFP or QFN package ) > > As well, "they" use an external 100 ohms for all their simulations, > where we recommend use of the internal 100 ohms for all high speed > interfaces (really makes things look worse due to the stub). > Perhaps you should review your own documentation before throwing stones at others. The last time we went round on this, you pointed to the ML450 V4 evaluation board as a shining example of SI design. If you look at the ML450 schematic, BOM, and board layout, you'll notice that the HyperTransport input lines are terminated using external 100 ohm resistors, with stub lengths of about half an inch. Maybe this was done because you can't meet the HyperTransport +/- 10% terminator R spec with the _DT terminators, but I'd wager that the internal R's would work better than those big stubs, especially with the non-compliant Cin values of your HyperTransport inputs. I didn't spot any supporting IBIS sims for the ML450 layout anywhere; perhaps you could publish some 500 MT/s and 1 GT/s simulations in the user guide, using a fast HyperTransport compliant driver, with waveforms plotted both at the internal FPGA Rx and at a HyperTransport bus probe connector on the driving board :) From HyperTransport 2.0: internal terminator Rt : 100 ohm +/- 10% single ended Cin (400-800 MT/s) : 5 pF single ended Cin (1-2 GT/s) : 2 pF single ended Cout (400-800 MT/s) : 5 pF single ended Cout (1-2 GT/s) : 3 pF Any mention of HyperTransport in your datsheets, app notes, and user guides should be appropriately footnoted as non-compliant. BrianArticle: 89259
Do you think the A version works? I can't get an SST part from Digikey, my only source, which means I'm out of luck :( I just can't seem to grasp that one of these parts costs $17....Article: 89260
"jai.dhar@gmail.com" <jai.dhar@gmail.com> wrote in news:1126271541.652158.82620@g47g2000cwa.googlegroups.com: > Do you think the A version works? I can't get an SST part from Digikey, > my only source, which means I'm out of luck :( > > I just can't seem to grasp that one of these parts costs $17.... > > I have no idea which of these parts might work. The SST parts are pin compatible but have different IDs. They probably cannot program from quartus but they might read OK. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 89261
Williams, From what you explain about the implementation of a tri-state, and from what I see in your code, there is no problem with both. If you cannot spot this problem in simulation, try checking hardware for any other devices driving this bus, especially if you are in the first steps of ... Any details? Vladislav <stud_lang_jap@yahoo.com> wrote in message news:1126260446.092886.325910@g49g2000cwa.googlegroups.com... > Hello Guys, > > I am having an IP which has 2 interface master and slave interface but > there single external bus. > To adapt to this architecture i using an trisatate implementation of > bus. But the problem is > that once i have the tristating of bus , signal interfacing to slave > interface of IP gets grounded. > I have observed it in chipscope (probing the EDF) but if i donot have > tristating the IP is working fine. > I tried all ways but still i could not solve the problem. > > I will explain one of the signal interface: HTRANS > > Global external bus signal is HTRANS. This signal connect directly to > slave HTRANS > since its a input and there is iHTRANSOut signal in master part which > is output and i have > this to connect to same external HTRANS. > > Code goes this way: > > always @(posedge iHCLKBUF) > begin > if (nSYSRST == 1'b0) > AHBMasterEnable <= 1'b0; > else > if (HREADY == 1'b1) > AHBMasterEnable <= HGRANT[2]; > end > > assign HTRANS = (AHBMasterEnable == 1'b1) ? iHTRANSOut : 2'bzz; > > Is there any problem in the tristate implementation? > > > Waiting for your reply, > Thanks in advance > Williams >Article: 89262
Giox wrote:
> Hi, I performed a post route simulation using FPGA Advantage tools and
> Modelsim 6.0c.
If your functional sim works as expected
and your design is synchronous and you
pass post-route static timing,
no sdf sim of the routed netlist is really needed.
If you want to try one anyway,
start with a simpler example.
-- Mike Treseler
Article: 89263MIke - If you're trying to track down a synthesis bug, post synthesis simulation may be useful. I've seen case in the past where XST produced inccorect logic. A slight change to the Verilog structure and the bug disappeared. In cases like that, gate level sims are useful. In general, I don't do gate level sims, I pay attention to the the constraints and the static timing results. John ProvidenzaArticle: 89264
"Giox" wrote: >This file is probably applied to the wrong instance. Was the SDF file applied to the back annotated VHDL or verilog file, or the the source file? The SDF file has timing information for the back annotated file, not for the source file. >I don't understance where the GTS_OR and COUTUSED elements can be >found. GTS is part of the startup logic, which isn't part of your source. While I can't be sure without looking at all of the files, I'd suspect that this is related to GTS_OR. I'm going to -- Caution: Contents may contain sarcasm. Phil HaysArticle: 89265
In Verilog, I do it by defining all variables as signed. Then it's automatic. reg [7:0] p1; reg [7:0] p2 wire signed [8:0] p1s; wire signed [8:0] p2s; wire signed [8:0] diff; assign p1s = p1; assign p2s = p2; assign diff = p1s - p2s; Notice that I made all variables 9-bits to ensure that values up to 255 will be treated as positive numbers and so that the result can represent the full range of -255 to +255. Marko On Wed, 7 Sep 2005 06:21:37 +0200, "news.green.ch" <rb@freesurf.ch> wrote: >Hi >I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how >to define a signed number? >I've the following situation: > >reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 >reg [7..0] p2 // is the unsigned value that we should have 0..255 > >now I want to substract p1-p2, to have the differenz, to correct the error >reg[7..0] diff //should be a signed value > >how do I define this in Verilog HDL > > >best regards remo > > > >----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==---- >http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups >----= East and West-Coast Server Farms - Total Privacy via Encryption =----Article: 89266
I am trying to compile edk libraries( EDK 7.1 on Fedora Core 2) .I followed the "simulation in edk" instructions and used the wizard without much success. Then I manually ran the compxlib command and compiled the xilinx libraries.It worked fine. Now the problem is with the compedklib command.When I try to run the compedklib with any option like for example compedklib --help the following message pops up : xilperl: error while loading shared libraries: libdb-4.1.so: cannot open shared object file: No such file or directory Does anyone of you all have any idea what the problem could be... Thanks, NiteshArticle: 89267
> I have no idea which of these parts might work. The SST parts are pin > compatible but have different IDs. They probably cannot program from > quartus but they might read OK. Looking at the *.pof for a Cyclone configured to load from an EPCS4, the string EPCS4 is included at the start. I'm not sure of why I think this, but I've an idea that the devices check the device ID at the start of config, although this might be wrong. If this is the case you'd have to use a device with the same ID. Nial. ------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 89268
vssumesh wrote: > I wont be able to do the first two methods as it will disable all the > output pins. > I know that the third method is reasonable. But i am unable to explain > the behaviour. > 1. I deleted all the connection to the 'A' and 'B' bus from the FPGA. > But still some bits in the bus 'B' was missing. Then i connected the > FPGA to the bus 'B' and assigned input status. Then bus 'B' started > working but bus 'A' reported errors. How can it be possible. > The same thing happend when i assigned input to both buses. If i go for > bus 'B' bus 'A' gets corrupted and vice versa. > If i assign input to both the buses still bus 'A' reported errors. > And for your question i dleted all the driving of bus 'A' and 'B' from > the RTL. > Sumesh > The problem which you report remembers me of an odd behavior I encountered with a previous design. It turned out that the top-level port mapping (VHDL design flow) didn't match the UCF file (my mistake). More precisely, I had a couple IOs in the port mapping which weren't declared in the UCF file (running PACE and uncheking the "Allowing Unmatched LOC Constraints" implementation option revealed the error). The SW tools (AFAIR) connected these undeclared IOs into the first unused physical pad it found. It goes without saying that the design was then acting a bit strangely ;)Article: 89269
There are three options from easy to hard:
1.- It is very likely that all you need to do is CUT all multi-clock
transfers. This is easily done by making a clock to clock CUT
set_instance_assignment -from clk1 -to clk2 -name CUT ON
set_instance_assignment -from clk2 -to clk1 -name CUT ON
and so on.
This will at least ensure Quartus Timing Analyzer (TAN) does not try to
do a multi-clock analysis (e.g. use clk1 for the source register and
clk2 to the destination register):
2.- If this is not enough, the second solution is to simply pick one
clock (likely the fastest clock) as the clock use by TAN. To do this,
just add a CUT to the other two clocks
set_instance_assignment -to clk1 -name CUT ON
set_instance_assignment -to clk2 -name CUT ON
3.- The last possibility is to simply add a base clock on the output of
the MUX which I assume is used to select the clocks. This is ok for
FMax (i.e. internal reg to reg transfers), but will not work on Tco as
Tco is defined as an clock pin to output pin path, and does not account
for internal clocks. A workaround is to change the Tco to an
OUTPUT_MAX_DELAY assignment which can be set from the internal clock.
For information on OUTPUT_MAX_DELAY see
http://www.altera.com/literature/hb/qts/qts_qii53004.pdf
Hope this helps,
Subroto Datta
Altera Corp.
Article: 89270I have converted an old Xilinx schematic design into VHDL. However, I'm running into a problem with how to implement the GSR function properly. I'm used to having an external reset line feed one of the pins, that could be specified to Leonardo 4.22 as the global_sr signal. This design, however, used an internally generated pulse from the configuration section to pulse the registers. When I try to read in the design, I get told by Leonardo that the GSR net name that I'm using does not have a source --> looking at the schematic viewer, I find that all of the GSR nets get grounded. Any thoughts on how I can resolve this issue are welcomed. I'm going to review the older Leonardo documentation, as well as look at the Xilinx docs regarding the STARTUP block. (One of the things, however, is that the Leonardo docs state NOT to instantiate the BSCAN or STARTUP block -- which I'm not sure about). Regards, BobArticle: 89271
Can you just change the ID in the POF file manually?Article: 89272
Hello fpga-faq, I want to create a user module that will act as a master on an opb bus. I am using xilinx Platform Studio, version 7.1i. Now before you say it, I have read the http://www.xilinx.com/ise/embedded/est_rm.pdf guide on using the create/import wizard for xps. I have read it, and seen the skeleton, but have not been successful with a master bus. I have created a custom slave module, and succeeded... Has anyone done this? I just want some sample code that does anything as a master on an opb bus. In case it is not clear why this would be a good thing, there are many edk tools that will only work over an opb bus- but in many fpga designs, you don't really need a processor, just custom code. All I want is the edk uartlite over a opb bus, but I have to be the opb master to do it. thank you, ~arinArticle: 89273
arincm@hotmail.com wrote: > Hello fpga-faq, > > I want to create a user module that will act as a master on an opb bus. I have not had much luck with the Xilinx tools for creating peripherals. I would just read http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/9A7AFA74DAD200D087256AB30005F0C8/$file/OpbBus.pdf (search for opbbus.pdf on www.ibm.com) and write it by hand. Of course, if all you need is a uart there is plenty of source. Alan NishiokaArticle: 89274
Subroto Datta wrote: > Glen, > > Please check if you are getting the following message: > Warning (10040): Verilog HDL or VHDL arithmetic warning at <location>: > loss of carry in addition or borrow in subtraction > If so, then this is a linting message that points out a potential > design mistake. It's a related, but nevertheless distinct issue from > simple truncation. If you get the truncation warning, you may be using > a much older version of the software that didn't distinguish loss of > carry from generic value truncation according to Verilog expression > sizing rules. If you want you could mail the qar file for your project > to me and can confirm. I am not sure of the exact message, but yes, it is getting a warning message like that. The reason I comment on it is because I believe that verilog specifies that it has the correct width. I probably have (had, I am not working on that project currently) an older version of Quartus, so the message may have been different. I believe it actually specifies the width being used. Otherwise, yes, as a lint type warning it is fine. -- glen
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z