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Jeff Cunningham wrote: > Signals defined in a VHDL package can be global in scope. > -Jeff In Verilog it's even easier. You can specify any signal using the module hierarchy and "." as a separator like: top.instance1.signameArticle: 89151
hi how do we program the spartan 3 starter kit to load the configuration from PROM automatically at start up. Thank you. CMOSArticle: 89152
Make sure JP1 is jumpered. Upper Right Corner.Article: 89153
Hi, I just got a board with a Viretex-II pro FPGA. I'm a newbie and have several questions that would like to get some answers or suggestions. We were planning on porting linux to the FPGA. What are the advantages and disadvantages of porting linux to PPC and Microblaze? I have seen works done on porting uClinux to Microblaze, is that better than porting to PPC? Is it a good idea to port full linux instead of embedded linux to the FPGA? I'm a starter and looking for some directions. If anyone could give me suggestions or good references other than the ones on Xilinx and uClinx port to Microblaze websites, I'd really appreciate it. Thank you. EricArticle: 89154
I've been eagerly awaiting the September arrival of the Spartan-3E Starter Kit, but today the Xilinx Online Store indicates that the target availability is now December 2005. Sigh. I'll have to lay out my own board and try to get some XC3S500E chips through distribution. Though I'll still likely buy the start kit when it becomes available.Article: 89155
Follow XAPP765 (http://direct.xilinx.com/bvdocs/appnotes/xapp765.pdf) to get started with Linux on Virtex-II Pro. Another source for information are the ML310 web pages (http://www.xilinx.com/ml310). - Peter Eric wrote: > Hi, > > I just got a board with a Viretex-II pro FPGA. I'm a newbie and have > several questions that would like to get some answers or suggestions. > > We were planning on porting linux to the FPGA. What are the advantages > and disadvantages of porting linux to PPC and Microblaze? I have seen > works done on porting uClinux to Microblaze, is that better than > porting to PPC? Is it a good idea to port full linux instead of > embedded linux to the FPGA? I'm a starter and looking for some > directions. If anyone could give me suggestions or good references > other than the ones on Xilinx and uClinx port to Microblaze websites, > I'd really appreciate it. Thank you. > > Eric >Article: 89156
> > > > We will be answering questions at the end of the seminar, and I look > > forward to any follow-up in the newsgroup. > > > > Regards, > > > > Paul Leventis > > Altera Corp. > > > > > > Oh, great, can't wait for more Altera vs. Xilinx B.S., mine is bigger than yours ;-)Article: 89157
Sylvain Munaut wrote:
>Hi,
>
>I need to define some environment variable to
>change the behavior of the synthesis tool in order
>for my design to compile (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING).
>
>I'd like to define that inside the EDK project, without having to modify
>my system or user wide environment. I've tried adding that to the
>system_incl.make but that file is overwritten at each build ...
>
>What's the proper way to do that ? The search I've done so far didn't
>get many relevant results ...
>
>
> Sylvain
>
>
Sylvain,
Create a copy of system.make (call it mysystem.make) and in XPS
Project Options dialog box, point XPS to this makefile. In this
makefile, you can set the environment variable. Note that
system_incl.make and system.make are always overwritten, but you can
point XPS to use your own makefile (which is to replace system.make) and
thus change environment.
Thanks,
Amit
Article: 89158It's not only Linux, i.e. the PPC, but also the (DMA based) peripherals. Assume the PPC and a peripheral share some memory in the memory address space to communicate status. One such example can be the descriptor for an Ethernet transfer where one bit indicates whether the descriptor is free or busy. The PowerPC can have the descriptor cached or uncached depending on the implementation of the device driver. In the cached version the driver writes to the status bit and the flushes the memory area out of the cache. If the driver allocates uncached memory for the descriptor no flushing is needed and the area gets updated immediately upon a write. Now, a peripheral (almost) always accesses this bit uncached and will directly write to the byte containing this bit. However, if the memory does not support single byte writes a whole word will be overwritten and information is changed that should not have been. In Linux it is up to the developer of the device driver on how she implements the access to the shared memory. However, a user will not be able to tell what is implemented in the device driver without studying the code. I was using the RAM disk based Linux as a placeholder for a very simple Linux system without DMA, i.e. a UART as the only peripheral in the system. The RAM disk does not generally fix the missing byte masks ;-) - Peter Symon wrote: > "Peter Ryser" <peter.ryser@xilinx.com> wrote in message > news:431DBCD0.9020200@xilinx.com... > >>It is very likely that you will need to patch your card and bring the >>byte masks out. Linux uses the MMU to set up cacheable regions, ie. it >>will/may put descriptors (networks, etc.) into uncacheable areas. Unless >>you plan to modify the Linux kernel heavily it is very unlikely that >>your system will work. You can boot Linux though from a RAM disk to >>least get started. >> > > Hi Peter, > Could you explain why Linux puts these things in uncacheable areas? > Also, how does a RAM disk help you boot? > Thanks very much, Syms. > >Article: 89159
still no joy. gdb reports: status -1 ffffffff An error was reported by the proxy server. The command was: "JTAG_COMMAND_READ",3220120016,0x00000004 The command returned -1. since i'm working with a virtex2p, i didnt do the CLKDLL part of the instructions. the build tools report an expected clock speed of 75 Mhz. how critical is the CLKDLL step? at what clock speeds is it necessary to employ a clock divider? i've followed all of the other steps, twice in fact from scratch, with the same results both times. i'd very much like to get openrisc running on this board...Article: 89160
Hi Peter, OK thanks, so the mists are starting to clear a little. I can see it's a problem if byte wide semaphores are present in the memory range that the PPC sees as cached that an external peripheral needs to access by DMA. So, here's my next question!! If I locate all these peripheral status bits into memory on the Xilinx device, i.e. in BlockRAM, rather than in the external 'no mask bits' SDRAM/DDR RAM, does that solve the problem? It's possible to make the BlockRAMs work uncached and with byte access, even though the external SDRAM is cached. Thanks again, Syms. "Peter Ryser" <peter.ryser@xilinx.com> wrote in message news:431E3553.20000@xilinx.com... > It's not only Linux, i.e. the PPC, but also the (DMA based) peripherals. > > Assume the PPC and a peripheral share some memory in the memory address > space to communicate status. One such example can be the descriptor for > an Ethernet transfer where one bit indicates whether the descriptor is > free or busy. > > The PowerPC can have the descriptor cached or uncached depending on the > implementation of the device driver. In the cached version the driver > writes to the status bit and the flushes the memory area out of the > cache. If the driver allocates uncached memory for the descriptor no > flushing is needed and the area gets updated immediately upon a write. > > Now, a peripheral (almost) always accesses this bit uncached and will > directly write to the byte containing this bit. However, if the memory > does not support single byte writes a whole word will be overwritten and > information is changed that should not have been. > > In Linux it is up to the developer of the device driver on how she > implements the access to the shared memory. However, a user will not be > able to tell what is implemented in the device driver without studying > the code. > > I was using the RAM disk based Linux as a placeholder for a very simple > Linux system without DMA, i.e. a UART as the only peripheral in the > system. The RAM disk does not generally fix the missing byte masks ;-) > > - Peter > >Article: 89161
"Luis Cupido" <cupidoREMOVE@REMOVEua.pt> wrote in news:newscache$0vhemi$3um$1@newsfront4.netvisao.pt: > Hi, > > I've been using the 25P10 flash to configure cyclone devices, > as far as I can see they are exactly equal to the EPCS1 > (even silicon ID is the same, I suspect it is the same chip inside) > > All altera devices (in AS) I tested can read it and configure fine, > however the Quartus II fail to load data into the 25P10... > (I must use another software to load the 25p10 and that is less > convenient) > > Does anybody knows why... what is the trick used ? > > Luis C. > > > > This is very interesting since the configuration roms are expensive compared to typical SPI flash. I noticed that Lattice is pushing the fact that they can configure using cheap standard SPI flash. Do you use the 25p10 A version. Have you tried SST parts? -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 89162
Hi I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how to define a signed number? I've the following situation: reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 reg [7..0] p2 // is the unsigned value that we should have 0..255 now I want to substract p1-p2, to have the differenz, to correct the error reg[7..0] diff //should be a signed value how do I define this in Verilog HDL best regards remo ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==---- http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups ----= East and West-Coast Server Farms - Total Privacy via Encryption =----Article: 89163
> If I locate all these peripheral status bits into memory on the Xilinx > device, i.e. in BlockRAM, rather than in the external 'no mask bits' > SDRAM/DDR RAM, does that solve the problem? It's possible to make the > BlockRAMs work uncached and with byte access, even though the external SDRAM > is cached. Theoretically yes. But you would still have to go through all Linux device drivers, or at least the ones you plan to use, and modify them so that they would use the BRAM address space instead of the main memory address space for these special variables. IMHO, the soldering iron is the faster approach to get this working... - PeterArticle: 89164
Al Clark wrote: > "Luis Cupido" <cupidoREMOVE@REMOVEua.pt> wrote in > news:newscache$0vhemi$3um$1@newsfront4.netvisao.pt: >>Hi, >> >>I've been using the 25P10 flash to configure cyclone devices, >>as far as I can see they are exactly equal to the EPCS1 >>(even silicon ID is the same, I suspect it is the same chip inside) >> >>All altera devices (in AS) I tested can read it and configure fine, >>however the Quartus II fail to load data into the 25P10... Then SOMETHING must be different ? >>(I must use another software to load the 25p10 and that is less >>convenient) >> >>Does anybody knows why... what is the trick used ? >> >>Luis C. > > This is very interesting since the configuration roms are expensive > compared to typical SPI flash. I noticed that Lattice is pushing the fact > that they can configure using cheap standard SPI flash. > > Do you use the 25p10 A version. Have you tried SST parts? ... and you will see Xilinx have also hopped on this bandwaggon, with their newest Spartan 3E's - much hoopla about std SPI and also NOR flash loader options. It cost them ~3 pins, to select the vendor/state engine for a given SPI memory. Not before time, but it will mean Altera have to step into line as well, and remove any 'deliberate' hurdles that might have found their way into their tool flows ( if that's really what's occured ? ) -jgArticle: 89165
Hi All, Now I am using Virtex-II Pro50 Memec Design FPGA to do my projects. I want to use flash to store my data, so I have to add a flash on the fpga. From the internet I learned that I can add a System ACE CF by the System ACE connector or I can add a P160 module which have flash on it by P160 connector. Are the two methods all OK for the Virtex-II FPGA, if so, which is better and easier? if not, what can I do to use flash to store my data? Thank you! LinaArticle: 89166
Hello, The new release (1.5.1) of OpenTech is available now with more and more new free open source hardware designs and design software. This is the 11th release of OpenTech in 6 years. OpenTech is the first and the only package that distributes open source hardware designs (e.g. VHDL, Verilog, PCB, schematics......) and hardware design software (e.g. Synthesis tools, schematic captures, PCB and IC layout, simulators ......) For information about the contents, the available packages and ordering information visit http://www.opencores.org/projects.cgi/web/opentech/about To offer support to OpenTech users we started teh OpenSupport programs where you can forward your support requests about the listed designs and tools. http://www.opencores.org/projects.cgi/web/opentech/partners If you can provide support to other designs or tools you can join this program and offer support and earn money We are currently searching for free (or open source) documentation, books, tutorials or study materials to include them in the future releases of OpenTech OpenTech offers some special offers to students and universities (contact us for more info) Besides that we are looking for local distributors or resellers of OpenTech CDROMs For more information visit our site or send us email Best regards, Jamil Khatib OpenTech maintainer http://www.opencores.org/projects.cgi/web/opentech/aboutArticle: 89167
...I'm still waiting for the softies to come back, in the meantime I have modified my DDR2 controller, actually the PLB side of it (I didn't want to change the controller itself for this mess) such that when it detects a byte/16-bit word write it performs a read-modify-write access. It works! Instead of taking 'x' clk cycles it takes twice that :O( What I've seen in my simulation though is that byte/16bit word accesses happen once in a blue moon. I have a card with no Data Masks and a card almost in Layout which is definetely getting Data Masks wired up, this mod will get me further with the old card. Regarding... >>It's possible to make the >> BlockRAMs work uncached and with byte access, even though the external >> SDRAM >> is cached. The answer is yes, I have had our system using uncached BlockRAM and cached SDRAM, no problem. Although as Peter said you would have to modify all Linux device drivers and to me sounds painful (I insist, I'm not a software guy...yet) Regarding the soldering iron :O), in our design the Byte Data Mask signals are going to be toggling @ 200 MHz times two because its DDR nature, 400 MHz... a wee bit too fast for a normal soldering jobby ;) Regards, Ulises Hernandez "Peter Ryser" <peter.ryser@xilinx.com> wrote in message news:431E7135.2060809@xilinx.com... >> If I locate all these peripheral status bits into memory on the Xilinx >> device, i.e. in BlockRAM, rather than in the external 'no mask bits' >> SDRAM/DDR RAM, does that solve the problem? It's possible to make the >> BlockRAMs work uncached and with byte access, even though the external >> SDRAM >> is cached. > > Theoretically yes. But you would still have to go through all Linux device > drivers, or at least the ones you plan to use, and modify them so that > they would use the BRAM address space instead of the main memory address > space for these special variables. > > IMHO, the soldering iron is the faster approach to get this working... > > - Peter >Article: 89168
You FPGA guys were so nice to me when I asked questions about decapping ICs and reverse engineering PALS...I have one more for you. :) I want to reproduce Steve Wozniak's video circuit from the Apple 1. I can't reproduce it part for part since some of the parts are discontinued, but it could at least be logically accurate. The datasheets I'm looking for are: 2504 - 1024x1 DRAM 2513 - Character generator rom 2519 - 40x6 Static Shift Register The 2513 from the Apple 1 is marked like this: S7625 2513N CM2140 The 2519 from the Apple 1 is marked like this: S7640 2519B The 2504 from the Apple 1 is marked like this: S7632 2504V 1404A I downloaded www.bitsavers.org/pdf/signetics/_dataBooks/Bipolar_MOS_uProc_1977.pdf and on page 283 it says the 2513 CM2140 is a "New ASCII Character Generator, Upper Case, 7x5, Horixontal Scan". I'd really like to find this chip to find the exact dotpattern of the font. If anyone knows how to help me that would be great. I will be keeping track of the project at http://www.stockly.com, but please respond to this thread directly. (I just mention the web address for the web archives...) Thanks, GrantArticle: 89169
Hi all, Very new here, but not new to FPGA. A few questions: Does anyone know where to get cheap (used) Xilinx development boards? Looking for the ML310. Can anyone recommend a development board that can implement cache and dual channel DDR2 interface? The ML461 is just too expensive for a student. Anyone know how I can implement cache on a FPGA? Got any good links? Thanks, -TonyArticle: 89170
On 06 Sep 2005 16:40:54 -0700, Eric Smith <eric@brouhaha.com> wrote: >I've been eagerly awaiting the September arrival of the Spartan-3E >Starter Kit, but today the Xilinx Online Store indicates that the >target availability is now December 2005. > >Sigh. > >I'll have to lay out my own board and try to get some XC3S500E chips >through distribution. Though I'll still likely buy the start kit when >it becomes available. Had an email recently to say that Memec have abandoned their S3E board & would I like an S3 board instead of the 3E board I ordered at X-Fest..... Annoying thing is I only ordered it to get the software, which they won't ship seperately. What a joke. And the Xilinx webstore has no stock of any S3 parts either..... If I was about to start an FPGA design-in I think I'd be seriously looking at Altera right now....Article: 89171
news.green.ch wrote:
> Hi
> I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how
> to define a signed number?
> I've the following situation:
>
> reg [7..0] p1 //(is an unsigned value from AD converter) 0..255
> reg [7..0] p2 // is the unsigned value that we should have 0..255
>
> now I want to substract p1-p2, to have the differenz, to correct the error
> reg[7..0] diff //should be a signed value
>
> how do I define this in Verilog HDL
>
>
> best regards remo
>
>
>
> ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==----
> http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups
> ----= East and West-Coast Server Farms - Total Privacy via Encryption =----
Signed and unsigned addition are the same. Their results is to be
interpreted differently though ...
Let's says the number are 4 bits unsigned :
1001 = 9
0100 = 4
--------
01101 = 13
now if they are 4 signed :
1001 = -7
0100 = 4
---------
01101 = -3
See, the method to do the computation is the same but what it _means_ is
different ...
Now, you want to substract 2 unsigned number of seven bits so the result
to avoid overflow should be 9 bits. I don't know verilog but in vhdl
that would give
diff <= ('0' & p1) - ('0' & p2);
The synthesis tool should be smart enough to figure out to use a 8 bit
adder, input 1 to the start of the carry chain, inverting p2 and
outputing the carry to the 9th bit of diff.
Sylvain
Article: 89172
almost right
01101 /= -3
11101 = -3
you need to sign extend ;-)
Simon
"Sylvain Munaut" <com.246tNt@tnt> wrote in message
news:431ebc5a$0$27788$ba620e4c@news.skynet.be...
> news.green.ch wrote:
> > Hi
> > I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but
how
> > to define a signed number?
> > I've the following situation:
> >
> > reg [7..0] p1 //(is an unsigned value from AD converter) 0..255
> > reg [7..0] p2 // is the unsigned value that we should have 0..255
> >
> > now I want to substract p1-p2, to have the differenz, to correct the
error
> > reg[7..0] diff //should be a signed value
> >
> > how do I define this in Verilog HDL
> >
> >
> > best regards remo
> >
> >
> >
> > ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet
News==----
> > http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+
Newsgroups
> > ----= East and West-Coast Server Farms - Total Privacy via Encryption
=----
>
> Signed and unsigned addition are the same. Their results is to be
> interpreted differently though ...
>
> Let's says the number are 4 bits unsigned :
>
> 1001 = 9
> 0100 = 4
> --------
> 01101 = 13
>
> now if they are 4 signed :
> 1001 = -7
> 0100 = 4
> ---------
> 01101 = -3
>
>
> See, the method to do the computation is the same but what it _means_ is
> different ...
>
>
> Now, you want to substract 2 unsigned number of seven bits so the result
> to avoid overflow should be 9 bits. I don't know verilog but in vhdl
> that would give
>
> diff <= ('0' & p1) - ('0' & p2);
>
> The synthesis tool should be smart enough to figure out to use a 8 bit
> adder, input 1 to the start of the carry chain, inverting p2 and
> outputing the carry to the 9th bit of diff.
>
>
> Sylvain
Article: 89173Sumesh, If you want to complete isolate the FPGA from the rest of the board for troubleshooting purposes, you should be able to hold the "program" pin low. This will tristate ALL of the FPGA signals. An alternative method would be to instantiate the startup macro and use the "GTS" input to issue a global tristate to the part. This will disable ALL outputs from the FPGA. Of course, both of these methods remove all the FPGA functionality from your board, not just the bus interface. As you suggested, deleting the bus from your RTL code should disable it as well. If it isn't there, it shouldn't drive the bus. The unkown here is whether your bus inputs are used in the code and therefore cause synthesis errors. You might try declaring the bus as "input" rather than IO. Without drivers, the FPGA would simply be sniffing the bus. PipjockeyArticle: 89174
Simon Peacock wrote:
> almost right
> 01101 /= -3
> 11101 = -3
>
> you need to sign extend ;-)
Damn, my bad ... typed quicker than I thought ;)
>
> Simon
>
> "Sylvain Munaut" <com.246tNt@tnt> wrote in message
> news:431ebc5a$0$27788$ba620e4c@news.skynet.be...
>
>>news.green.ch wrote:
>>
>>>Hi
>>>I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but
>
> how
>
>>>to define a signed number?
>>>I've the following situation:
>>>
>>>reg [7..0] p1 //(is an unsigned value from AD converter) 0..255
>>>reg [7..0] p2 // is the unsigned value that we should have 0..255
>>>
>>>now I want to substract p1-p2, to have the differenz, to correct the
>
> error
>
>>>reg[7..0] diff //should be a signed value
>>>
>>>how do I define this in Verilog HDL
>>>
>>>
>>>best regards remo
>>>
>>>
>>>
>>>----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet
>
> News==----
>
>>>http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+
>
> Newsgroups
>
>>>----= East and West-Coast Server Farms - Total Privacy via Encryption
>
> =----
>
>>Signed and unsigned addition are the same. Their results is to be
>>interpreted differently though ...
>>
>>Let's says the number are 4 bits unsigned :
>>
>> 1001 = 9
>> 0100 = 4
>> --------
>>01101 = 13
>>
>>now if they are 4 signed :
>> 1001 = -7
>> 0100 = 4
>>---------
>>01101 = -3
>>
>>
>>See, the method to do the computation is the same but what it _means_ is
>>different ...
>>
>>
>>Now, you want to substract 2 unsigned number of seven bits so the result
>>to avoid overflow should be 9 bits. I don't know verilog but in vhdl
>>that would give
>>
>>diff <= ('0' & p1) - ('0' & p2);
>>
>>The synthesis tool should be smart enough to figure out to use a 8 bit
>>adder, input 1 to the start of the carry chain, inverting p2 and
>>outputing the carry to the 9th bit of diff.
>>
>>
>>Sylvain
>
>
>
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