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"Nemesis" <nemesis2001@gmx.it> wrote in message news:1126778305.353415.173300@g14g2000cwa.googlegroups.com... > Hi all, > I just received a copy of ISE7.1, I removed the old 6.3 and installed > it. > I also installed the service pack 1 I had downloaded months ago. > > Now I'm experimenting lots of problems (ISE7.1 is a very crap, it > should > be an alpha release, not a 'stable' version), so I think I'll try > installing newer fix. > > I read that service packs are cumulative, can I install the last > service pack > even if I already installed service pack 1? do you reccomend this > operation? > (I had some problems with a 6.1 release, after installing > service_pack/ip_update/mx_lib_update I couldn't simulate some projects. > Download service pack 4 from Xilinx site and install it. MarcoArticle: 89451
Paul Urbanus wrote:
> I have an FPGA design where the VHDL source code is a deliverable item
> to the customer. One of the blocks in the FPGA must be protected so that
> the customer can't see the source and modify it.
Either source code is a deliverable or it isn't.
Unreadable source code is useless so why
bother creating it.
-- Mike Treseler
Article: 89452"Mancini Stephane" <nospam@nospam.nospam> wrote in message news:pan.2005.09.15.12.26.07.96556@nospam.nospam... > Hi all, > Does anyone has implemented a SATA link on Xilinx V2Pro to connect to a > hard disk drive ? > Indeed, we have the Xilinx XUP V2Pro Dev board from Digilent and it has a > SATA connector. So I'm wondering if one can control a hard disk drive from > this SATA connector. > Furthermore, I would like to mount the disk on linux running on the PPC. > I've already compiled and installed an own driver on linux and I'm > wondering if it would be possible to mount a SATA hard disk drive. > > Do you have any information about such development ? > > Thanks a lot for your help > > Stéphane I believe all you need is to power the drive and to have a kernel compiled with sata support. I want to do this with the xupv2pro board but haven't had the time. Could also use uclinux as well. http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/ http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf AlexArticle: 89453
"Jon Schneider" <jon@jschneider.tenreversed> wrote in message
news:m3ll223ato.fsf@undecided.camcom.co.uk...
> I've got my design talking to some (Kingston) KVR133X64/1G SDRAM
> modules and running at only 66MHz, doing some simple testing (the
> data=address or maybe data={address,address}) and have found some funnies.
>
> There are a few dozen single bit errors. There are also several
> locations that come back with some F digits (as if the cells just
> don't exist). Also they are mid-burst as much as not which indicates
> it isn't a timing problem.
>
> I have done testing on different FPGAs with different SDRAM modules
> and the errors definitely go with the modules and are quite
> repeatable.
>
> I have checked the refresh timing and it's good.
>
> Is Kingston SDRAM really that bad ? The fact they are made of
> repainted Infineon chips such that you can't read the original part
> number makes me suspicious that these might not be the real
> thing. They claim 100% testing but I wonder what they do with modules
> tested as bad. Is it because the FPGA can keep memory busy in a way a
> processor can't ? Should I speed up the refresh ? We intend to try
> some Micron parts anyway.
>
> Jon
Hi,
Isn't there some minimal frequency to respect (I believe it's 75 MHz for
DDR, I don't have the specs at hand)? Failing to do this could upset the
SDRAM's PLL.
Regards,
Alvin.
Article: 89454On Thu, 15 Sep 2005 23:49:51 +1000, Alex Gibson wrote: > > "Mancini Stephane" <nospam@nospam.nospam> wrote in message > news:pan.2005.09.15.12.26.07.96556@nospam.nospam... >> Hi all, >> Does anyone has implemented a SATA link on Xilinx V2Pro to connect to a >> hard disk drive ? >> Indeed, we have the Xilinx XUP V2Pro Dev board from Digilent and it has a >> SATA connector. So I'm wondering if one can control a hard disk drive from >> this SATA connector. >> Furthermore, I would like to mount the disk on linux running on the PPC. >> I've already compiled and installed an own driver on linux and I'm >> wondering if it would be possible to mount a SATA hard disk drive. >> >> Do you have any information about such development ? >> >> Thanks a lot for your help >> >> Stéphane > > I believe all you need is to power the drive and to have a kernel compiled > with sata support. Well, I've just had a look at the SATA specification document and there are 100 pages to deal with the link layer (synchronization + CRC + base primitives). The IP should run at 75 MHz and it's not so easy... The I/O IP itself is about 1 month (even more) of development. It's true that standard SATA linux driver could be used. Stéphane > I want to do this with the xupv2pro board but haven't had the time. > Could also use uclinux as well. > http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/ > http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf > > AlexArticle: 89455
Hi Mike, PCI specification requires the implementation of Configuration registers, and once the Configuration registers are properly implemented, then your device will be Plug & Play compatible. In your case, the implementation of Command and Status Register (Configuration register 04H), and assuming that you need only one address map, Base Address Register 0 (Configuration register 10H) will make your device Plug & Play compatible. I don't recommend hardcoding decode address. I think it is asking for trouble. If that seems too much trouble, you may want to consider purchasing a personal use version of BDS XPCI PCI IP core. BDS XPCI PCI IP core is a Xilinx (TM) LogiCORE (TM) PCI compatible PCI IP core. BDS XPCI32 PCI IP core is available for as little as $100 for non-commercial, non-profit, personal use, and the same 64-bit version BDS XPCI64 PCI IP core (Includes BDS XPCI32 PCI IP core) goes for $200. This version is ideal for HDL learners, FPGA beginners, FPGA hobbyists, computer hardware enthusiasts, or student graduation projects. BDS XPCI PCI IP core comes with a PCI testbench which allows the user to simulate the design extensively on an HDL simulator like ModelSim before firing up the FPGA. With this PCI IP core, almost anyone can make their own PCI device for as little as $400. ($275 Insight Electronics Spartan-II 200 PCI Development Kit + $100 BDS XPCI32 PCI IP core.) Insight Electronics Spartan-II 200 PCI Development Kit is fully supported by this PCI IP core, and Avnet Xilinx Spartan-3 Evaluation Kit support will be added in the future. (The PCI IP core works fine with Spartan-3.) For commercial users who want to modify BDS XPCI PCI IP core or want to convert a design that uses Xilinx LogiCORE PCI to an ASIC (FPGA to ASIC conversion), BDS XPCI PCI IP core is also available in Verilog HDL RTL. For more information, visit Brace Design Solutions website at http://www.bracedesignsolutions.com. Kevin Brace Mike Zhang wrote: > Hi folks, I am starting to implement a simple PCI core using Spartan-II. I > have already implemented the basic read and write transfer before I find > this IDSEL signal which is used by PCI configuration transfers. My PCI board > just needs to read and write data from/to a fixed address. There is no need > for burst or back-to-back, nor plug-and-play. Do I need to implement the PCI > configuration? How about plug-and-play? > > Mike > > -- Brace Design Solutions Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use. http://www.bracedesignsolutions.com Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.Article: 89456
Mike Treseler wrote:
> Paul Urbanus wrote:
>
>> I have an FPGA design where the VHDL source code is a deliverable item
>> to the customer. One of the blocks in the FPGA must be protected so
>> that the customer can't see the source and modify it.
>
>
> Either source code is a deliverable or it isn't.
> Unreadable source code is useless so why
> bother creating it.
>
> -- Mike Treseler
The idea isn't to deliver source code. Instead, the idea is to deliver a
netlist file which is generated by compiling the source code. The block
in question is implemented using proprietary info
M NDA (with a chip manufacturer) states that this proprietary info must
be protected. Therefore, any code which utilizes this proprietary info
can't be redistributed in source form. So if I delivered a synthesisized
netlist I must make sure that the net names are obfuscated, at a
minimum. This can be achieved at either the source or netlist level.
You can debate the sensibility of protecting the proprietary, but I'm
contractually obligated to do so, and this policy will not be changed.
Given this, can anyone answer my original question and suggest how best
to protect a specific functional block in a larger Xilinx design.
Urb
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Article: 89457Mancini Stephane wrote: > Hi all, > Does anyone has implemented a SATA link on Xilinx V2Pro to connect to a > hard disk drive ? > Indeed, we have the Xilinx XUP V2Pro Dev board from Digilent and it has a > SATA connector. So I'm wondering if one can control a hard disk drive from > this SATA connector. > Furthermore, I would like to mount the disk on linux running on the PPC. > I've already compiled and installed an own driver on linux and I'm > wondering if it would be possible to mount a SATA hard disk drive. > > Do you have any information about such development ? > > Thanks a lot for your help > > Stéphane > Sorry, but you can't implement SATA directly with V-II Pro devices. Well at least not across the full compliance spectrum of SATA. The problems with implementing the standard are rooted in the OOB signalling requirements that require the TXP/TXN pair to be squelched to the common mode voltage (this can be implemented with an external circuit) and the spread spectrum clocking that may be present in the external drive (which can not be worked around). Both Xilinx and other vendors did place SATA connectors on our boards and these connectors can be used for general RocketIO MGT connections between boards using the Aurora protocol or anything else that you care to send across them. Virtex-4 can implemented SATA natively, but we do not yet have a full core released either from Xilinx or one of our Alliance partners at this time. EdArticle: 89458
On 15 Sep 2005 10:35:32 +0200, David Brown <david@westcontrol.removethisbit.com> wrote: >Unless you have complex timing requirements, a small micro would be the >best for making 3 PWMs. Get a small msp430 processor - they are cheap, >easy to work with, and have good free tools (the gcc port is excellent, >and there are free versions of ImageCraft and IAR tools for limited >program sizes). David, Thank you very much for your response. I am new to programmable logic and I really appreciate the suggestion. Just to make sure that I paint the entire picture, here are my full requirements... 1) 3independent PWM generators running at the same frequency. I am starting with 8-bit, but I could justify going down to 7bit and maaaaaaybe 6 or even 5 bit if it will save me much grief. 2) The FSM will probably have 8 states (cylcled through with a simple pushbutton, no reset). State 1 will tell PWM1 to run at 90% and PWM2 and 3 to be off. The rest of the states will turn the PWMs off and on in a variety of ways. The most complex of the states will tell all 3 PWMs to cylce from 10% to 90% out of phase from each other at about 0.5Hz. I do not have complex timing requirements. 3) I would like to detect the battery voltage and when it is running semi low, I would like to scale down the values of ALL PWM signals to extend battery life. For example, full battery = all PWMs @ 100%, battery 1/2 dead = all PWMs @ 50%, battery pretty much dead = sleep mode until the batteries start to receive a recharge, which could be several hours away. I got a Coolrunner II development kit just to get going with a 256macrocell chip onboard. I will plan on testing my functionality on that even if I fill the whole damn thing and then perhaps migrate to your recommended MSP430 after some research to prove why that would indeed be better than a CPLD. My application is geared towards a very high quantity consumer part, so I would like to see the chip cost under US$1 at quantity. I know that I have an uphill climb in front of me and my boots are on. If I indeed switch over to a MSP430, will my VHDL code that I am writing now be able to come with me? admitted newbie with big goals, frenchyArticle: 89459
Code up the examples on this website for good VHDL practice http://www.mcmanis.com/chuck/robotics/fpga/ EricArticle: 89460
Hello, I'm looking for small memory modules with - SRAMs (normal and fast) - FLASH - DRAMs which I want to use for tests with my FPGA-board. The module can contain only one type of the mentioned memories or more. My idea is that I only must develop an adapter for my FPGA-board because the modern packages are meanwhile a nightmare... Supply voltage 3,3 V. The FPGA-board is from Memec Design (Virtex-II Pro LC). Memec Design offers some memory add-on boards, but I need more memory. Any hints, ideas, own developments? Maybe I can use an add-on board for an embedded controller module or something like that. Thanks and greetings UdoArticle: 89461
Udo wrote: > Hello, > > I'm looking for small memory modules with > - SRAMs (normal and fast) > - FLASH > - DRAMs > which I want to use for tests with my FPGA-board. The module can > contain only one type of the mentioned memories or more. > My idea is that I only must develop an adapter for my FPGA-board > because the modern packages are meanwhile a nightmare... > Supply voltage 3,3 V. The FPGA-board is from Memec Design > (Virtex-II Pro LC). Memec Design offers some memory add-on boards, > but I need more memory. > > Any hints, ideas, own developments? Maybe I can use an add-on board > for an embedded controller module or something like that. > > Thanks and greetings > Udo The problem right away is Signal Integrity issues. Most all high performance devices want nothing to do with sockect and plugins which rules out high end DRAM, SRAM. You could look at Nallatech DIME standard, its used by a few other vendors at the V2 Pro level but its not exactly going to be pervasive like PCI. Perhaps compact PCI, but then you get IP licensing. johnjakson at usa ..Article: 89462
On Thu, 15 Sep 2005 08:06:22 +1200, Jim Granville <no.spam@designtools.co.nz> wrote: > You will struggle to do this in a Coolrunner, as you need to store >3 x 8 bit Values, plus have a 8 bit counter, plus prescaler?, and then 3 >PWM pins, so that's bumped you into 64 MC coolrunner. > > I have packed 3 x PWM into ATF1502ASL, using their logic doubling. >See >http://www.atmel.com/dyn/resources/prod_documents/DOC2310.PDF > > For small uC, do a google on Motor Control and Microcontroller. > >There are many, the most recent press release was this >http://www.st.com/stonline/press/news/year2005/p1672d.htm > >and there are numerous 80C51 variants with PCA, >and also the Atmel AT90PWMxx family.... > > Really depends what ELSE you need in the system... > >-jg > > Mr. Granville, Thanks again for your input. Please see my response to david regarding additional requirements of my system. In the meantime I will research the above uC info you provided. As I said, I have never used a uC before and I have no idea why it would be better than a CPLD. Luckily my Coolrunner development kit came with a 256macrocell chip on it! I will start there, get it working and then switch architectures based on price, etc. I had to start somewhere! thx, frenchyArticle: 89463
You could mean "Video Compression Demystified" by Peter Symes. It has a chapter on JPEG. --RYArticle: 89464
Luis, Thanks again for your response. I am new to VHDL coding, so your example helps. I see that you implemented the "counter and compare" method for the PWMs. I have read that the other implementation of PWM is slightly better with regards to required resources. See here... http://www.fpga4fun.com/PWM_DAC.html He makes this statement... "The more classical way to create the PWM output would be to use a counter and a comparator. But that requires more logic and it is tougher on the low-pass filter when "PWM_in" is wide. So the accumulator approach is better." Although I will not be using a LPF in my application, I remember his statement about logic. I think that I will employ the "count&compare" method for now, it seems more straightforward. thx again, frenchy On Thu, 15 Sep 2005 00:46:25 +0100, "Luis Cupido" <cupidoREMOVE@REMOVEua.pt> wrote: >Hi, > >If all pwm are at same frequency, you need just one >pwm_cycle counter (8 mc) and 3 comparisons with >the desired PWM values (3 registers of 8 bit) >that makes a total of 32 mc just for that. >So... 32mc... forget nearly impossible ! >64mc should be ok, (again not knowing what your state machine >will use ;). > >About the code... if using one cycle counter, just pack all >the 3 pwm together it will be more straightforward... > >if (clock='1' and clock'event) then > counter := counter +1; > if (counter>pwm_val_a) then pwm_a <= '1'; else pwm_a <='0'; end if; > if (counter>pwm_val_b) then pwm_b <= '1'; else pwm_b <='0'; end if; > if (counter>pwm_val_c) then pwm_c <= '1'; else pwm_c <='0'; end if; >end if; > >very simple VHDL code for that, the pwm_* outputs will have the duty >cycle of the registers pwm_val_* / 255 > >...my view of the thing :) > >--- >my aplic. it was low QTY, I did not care about price etc. > >lc. > > >"they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com> wrote >in message news:4kjgi15inu96ftvjg8hnl4tnh94q42d6o2@4ax.com... >> Based on your experience, do you think that three 8-bit PWMs could fit >> inside of a small CPLD (32 or 64 mcarocells)? The other funcionality >> that I plan to have in there is a state machine that drives the PWM >> inputs and perhaps some logic that detects the battery voltage level >> and chooses states accordingly. The more room that I have left over, >> the more involved I will make the state machine. >> >> The Max II that you used seems very similar to the Coolrunner II that >> I have been looking into. Was your project hi or low quantity? What >> was the cost of your MaxII at your quantity? >> >> thx again! >> frenchy >> >Article: 89465
Robin Bruce (robin.bruce@gmail.com) wrote: : I heard quite a lot about the Viva development environment last week at : the MAPLD 2005 conference in Washington DC. A lot of people had good : things to say about it. It seemed to me like Starbridge are currently : focussing on porting Viva to different hardware platforms. This leads : to ask the question: are Starbridge no longer in the hardware business? : What does this leave the Hypercomputer? : What are people's experience of using either Viva or the Hypercomputer? I did get the impression from some talks earlier in the year that Starbridge are more interested in pushing their software - lots of other people make hardware and the margins are less on hardware. Mind you my opinion of Viva isn't so great - it's bascially just a schematic capture tool and some libraries, and as nice as they seem they're more pain than they're worth - esp. as like most SC tools Viva is *proprietry*. o As complexity grows schematic tools become more like a weight around the neck o Proprietry. If they go under you can kiss your design work goodbye for future platforms / technologies. o You loose the power of things like the VHDL generate statement o Lots more Also Starbridge keep grosly misusing the word 'Polymorphic' when describing Viva - Polymorphism in an FPGA design is not a very good idea (!) and what they actually mean is that datatypes aren't fixed until compile time which is entirely different to polymorphism. I was also suprised by certian people hailing Viva as revolutionary, when it isn't. What *does* put Viva ahead of VHDL is the ability to design a core (e.g. FFT) and chance the datatype of the data flow from 8 bit fixed point to 24 bit floating point to 32 bit floating point etc. in an instant. In this sense it is easier than VHDL, but personally I reckon an HDL and a decent editor are almost as simple in this respect. Actually I think Starbridge also provide libraries to assist interfacing FPGAs running Viva generated code to host CPU systems - but they are far from alone in this respect. Cheers, ChrisArticle: 89466
Thank you Kevin! Yes, $100 dollars for the core is very cheap. But I would still like to try it myself since I have already done so much. Plus, I recently found a pretty cheap PCB manufaturer, so that can short-curcuit the evaulation boards. Cheers! MikeArticle: 89467
On Thu, 15 Sep 2005 16:29:01 +0200, "Alvin Andries"
<Alvin_Andries.dontusethispart@nowhere.agilent.remove_this_too.com> wrote:
>
>"Jon Schneider" <jon@jschneider.tenreversed> wrote in message
>news:m3ll223ato.fsf@undecided.camcom.co.uk...
>> I've got my design talking to some (Kingston) KVR133X64/1G SDRAM
>> modules and running at only 66MHz, doing some simple testing (the
>> data=address or maybe data={address,address}) and have found some funnies.
>>
>> There are a few dozen single bit errors. There are also several
>> locations that come back with some F digits (as if the cells just
>> don't exist). Also they are mid-burst as much as not which indicates
>> it isn't a timing problem.
>>
>> I have done testing on different FPGAs with different SDRAM modules
>> and the errors definitely go with the modules and are quite
>> repeatable.
>>
>> I have checked the refresh timing and it's good.
>>
>> Is Kingston SDRAM really that bad ? The fact they are made of
>> repainted Infineon chips such that you can't read the original part
>> number makes me suspicious that these might not be the real
>> thing. They claim 100% testing but I wonder what they do with modules
>> tested as bad. Is it because the FPGA can keep memory busy in a way a
>> processor can't ? Should I speed up the refresh ? We intend to try
>> some Micron parts anyway.
>>
>> Jon
>
>Hi,
>
>Isn't there some minimal frequency to respect (I believe it's 75 MHz for
>DDR, I don't have the specs at hand)? Failing to do this could upset the
>SDRAM's PLL.
Yes, but only for registered or DDR SDRAM - standard SDRAM modules don't have a PLL
Article: 89468This did the trick...in more than one way... Thanks for the advise on using ROC (Reset On Configuration). -Bob Bob Myers wrote: > Duane; > > Thanks for the info on ROC. I'm going to try it out; hopefully the > synthesis tool and Xilinx M1.5i router will handle it (I'm using the > tools "of the time"). > > I'll post later today, after I review the outputs of the two tools. > > Regards, > Bob > > Duane Clark wrote: > > > Bob Myers wrote: > > > I have converted an old Xilinx schematic design into VHDL. However, > > > I'm running into a problem with how to implement the GSR function > > > properly. > > > > > > I'm used to having an external reset line feed one of the pins, that > > > could be specified to Leonardo 4.22 as the global_sr signal. This > > > design, however, used an internally generated pulse from the > > > configuration section to pulse the registers. > > > > > > > The method I use in VHDL to implement the GSR is to instantiate within > > the design a ROC primitive (which is in the Xilinx unisim library). All > > of the Xilinx tools for many years have understood that this net is the > > GSR, and I would assume that Leonardo would too. ROC simply outputs a > > reset pulse of a few 100nS, just like the real GSR. > > > > -- synthesis translate_off > > library UNISIM; > > use UNISIM.VCOMPONENTS.ALL; > > -- synthesis translate_on > > > > ... > > component roc > > port ( > > O : out std_logic > > ); > > end component; > > > > ... > > roc_e: roc > > port map( > > O => RESET > > );Article: 89469
they call me frenchy wrote: > On 15 Sep 2005 10:35:32 +0200, David Brown > <david@westcontrol.removethisbit.com> wrote: > >>Unless you have complex timing requirements, a small micro would be the >>best for making 3 PWMs. Get a small msp430 processor - they are cheap, >>easy to work with, and have good free tools (the gcc port is excellent, >>and there are free versions of ImageCraft and IAR tools for limited >>program sizes). > > > > David, > Thank you very much for your response. I am new to programmable logic > and I really appreciate the suggestion. Just to make sure that I > paint the entire picture, here are my full requirements... > > 1) 3independent PWM generators running at the same frequency. I am > starting with 8-bit, but I could justify going down to 7bit and > maaaaaaybe 6 or even 5 bit if it will save me much grief. > > 2) The FSM will probably have 8 states (cylcled through with a simple > pushbutton, no reset). State 1 will tell PWM1 to run at 90% and PWM2 > and 3 to be off. The rest of the states will turn the PWMs off and on > in a variety of ways. The most complex of the states will tell all 3 > PWMs to cylce from 10% to 90% out of phase from each other at about > 0.5Hz. I do not have complex timing requirements. > > 3) I would like to detect the battery voltage and when it is running > semi low, I would like to scale down the values of ALL PWM signals to > extend battery life. For example, full battery = all PWMs @ 100%, > battery 1/2 dead = all PWMs @ 50%, battery pretty much dead = sleep > mode until the batteries start to receive a recharge, which could be > several hours away. > > I got a Coolrunner II development kit just to get going with a > 256macrocell chip onboard. I will plan on testing my functionality on > that even if I fill the whole damn thing and then perhaps migrate to > your recommended MSP430 after some research to prove why that would > indeed be better than a CPLD. > > My application is geared towards a very high quantity consumer part, > so I would like to see the chip cost under US$1 at quantity. I know > that I have an uphill climb in front of me and my boots are on. This does not sound like a CPLD problem. A fundamental determinant in cost is pin count, and there are no 8 or 14 pin CPLDs. CPLDs also have narrow Vcc tolerance, and in some cases, need Two supplies. You will also find the 10-20uA the CPLD vendors boast of, is MUCH higher than the Static Icc of Microcontrollers. There are no CPLDs with low power on-chip oscillators... You have not mentioned the PWM frequency, but the usage and action sounds like a lighting effects one, so you do not need the 300Mhz clock rates of a CPLD. Do a pin-count budget, and then choose a 8 pin or 14 pin Microcontroller. [I'd start with 14, and then see if it will fit in 8, when you are all done] For 8 & 14 pin Microcontrollers, look at Atmel, Freescale, Microchip, Philips, ST, TI, Zilog (etc) This application will move across uC quite easily, so choose the one that looks easiest for you to learn, and get it working on that, then start the bidding process, when it hits real volume :) > If I indeed switch over to a MSP430, will my VHDL code that I am > writing now be able to come with me? NO, but the ideas will.Article: 89470
John_H wrote: > > > PAR is multithreaded, use the -m switch. > > When I used the -m switch a while back on our unix system, I was able to > specify a node list for different hosts to run the multipass place & route > one more than one machine but I couldn't utilize multiple cores in one host. > I also can't use more than one host (or core) for one long place & route > job; the -m is specifically for multipass place & route (which, by the way, > doesn't have the option to use multiple mapper seeds!). This PAR feature is called the Turns Engine and it was never designed to support multiple jobs on a single machine. You can get around this by using a hostname alias in the node list file, or by tricking PAR by using variations of Mixed case in the node list file. For example, using a four processor machine named "speedy", and the following node list file would allow four concurrent jobs to run: speedy Speedy SPeedy SPEedy Xilinx Answer Record 10511 covers this. Regards, BretArticle: 89471
Hi, Ha!!! What they do is PDM pulse density modulation not PWM, may work the same for you... don't know, depends on how you use it. The PWM-pulse width modulation with a constant single output frequency with variable duty cycle, must be with a count and compare ;) > Although I will not be using a LPF > in my application, I remember his statement about logic. So, that is the problem... after a low pass filter both are equal, and PDM is more tolerant on filtering, but for direct use they are different ! think well if PDM does the same for you or not :) ...me, controlling step motors didn't had much luck with it ;) lc. "they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com> wrote in message news:60bji1dluro3fo2bcu6d2ig0n7q1d6qdeo@4ax.com... > Luis, > Thanks again for your response. I am new to VHDL coding, so your > example helps. I see that you implemented the "counter and compare" > method for the PWMs. I have read that the other implementation of PWM > is slightly better with regards to required resources. See here... > http://www.fpga4fun.com/PWM_DAC.html > > He makes this statement... > "The more classical way to create the PWM output would be to use a > counter and a comparator. But that requires more logic and it is > tougher on the low-pass filter when "PWM_in" is wide. So the > accumulator approach is better." Although I will not be using a LPF > in my application, I remember his statement about logic. > > I think that I will employ the "count&compare" method for now, it > seems more straightforward. > > thx again, > frenchy > > > On Thu, 15 Sep 2005 00:46:25 +0100, "Luis Cupido" > <cupidoREMOVE@REMOVEua.pt> wrote: > >>Hi, >> >>If all pwm are at same frequency, you need just one >>pwm_cycle counter (8 mc) and 3 comparisons with >>the desired PWM values (3 registers of 8 bit) >>that makes a total of 32 mc just for that. >>So... 32mc... forget nearly impossible ! >>64mc should be ok, (again not knowing what your state machine >>will use ;). >> >>About the code... if using one cycle counter, just pack all >>the 3 pwm together it will be more straightforward... >> >>if (clock='1' and clock'event) then >> counter := counter +1; >> if (counter>pwm_val_a) then pwm_a <= '1'; else pwm_a <='0'; end if; >> if (counter>pwm_val_b) then pwm_b <= '1'; else pwm_b <='0'; end if; >> if (counter>pwm_val_c) then pwm_c <= '1'; else pwm_c <='0'; end if; >>end if; >> >>very simple VHDL code for that, the pwm_* outputs will have the duty >>cycle of the registers pwm_val_* / 255 >> >>...my view of the thing :) >> >>--- >>my aplic. it was low QTY, I did not care about price etc. >> >>lc. >> >> >>"they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com> >>wrote >>in message news:4kjgi15inu96ftvjg8hnl4tnh94q42d6o2@4ax.com... >>> Based on your experience, do you think that three 8-bit PWMs could fit >>> inside of a small CPLD (32 or 64 mcarocells)? The other funcionality >>> that I plan to have in there is a state machine that drives the PWM >>> inputs and perhaps some logic that detects the battery voltage level >>> and chooses states accordingly. The more room that I have left over, >>> the more involved I will make the state machine. >>> >>> The Max II that you used seems very similar to the Coolrunner II that >>> I have been looking into. Was your project hi or low quantity? What >>> was the cost of your MaxII at your quantity? >>> >>> thx again! >>> frenchy >>> >> >Article: 89472
Atmel has an example that fits 4 8-bit PWM controllers in a 32 macrocell CPLD. It is written in CUPL. You need to download their tools at: http://www.atmel.com/dyn/products/tools_card.asp?tool_id=2759 The file is PWM8X4.PLD kevinArticle: 89473
Hi...
I am trying to use SDRAM (not chip but SDRAM as in
PCs)of micron in one of my projects (Gaming
Console).IActually i want to use it to use it as Shared Ram (As video
and also for other purposes )...
I have designed its controller and have checked by
simulation...but here is a problem to use it...
[b:8737ae6c30] Problem [/b:8737ae6c30]is that my
[b:8737ae6c30]FPGA board donot have SDRAM
Socket[/b:8737ae6c30](bank).
I m using SDRAM of 32MB and so it has 168
pins ...
So now the [b:8737ae6c30]solutions[/b:8737ae6c30] i feel
are...
[b:8737ae6c30]1- Get fpga board or some extention board which have
it[/b:8737ae6c30]
problem is that i m in university so will say my teacher to
get a board and so this process may take long time...as i not want
that so avoiding it...but till i have requested to teacher
[b:8737ae6c30]2- Second Solution is i turn on to RAM chips and use
different chips for different purposes (like one for Video and also
some for other purposes)[/b:8737ae6c30] and not use a shared RAM.
This is also time consuming as i have to request teacher
and will also make some more complications as have to handle
different small chips and i donot feel it professional...and also
VRAM may be expensive and difficult to handle... But still i have
requested teacher for that
[b:8737ae6c30]3- Make my own PCB having slot for SDRAM (SDRAM
Socket)...[/b:8737ae6c30]
Its not time consuming and i like to go for it although
its a little complex...
Problem in that is ... in my market i am unable to find
SDRAM Socket to use in my PCB... So i have to get it from some old
Motherboard which is difficult and as pins of SDRAM are close enough
so may damage pins...but will try
and also PCB for it will be of two layers at least...and
its too expensive ... so cannot go for two sided PCB...So i have to do
it in Single sided PCB... the only thing i want from my pcb is
to get the 168 pins (which are too closer) on some connector Pins...
[color=darkred:8737ae6c30]Plz Suggest...
FOR SOLUTION-1 that
Websites to Get economical FPGA or Extention boards having
SDRAM Socket in it (I m using VHDl and FPGA of Xilinx (any))
FOR SOLUTION-2 that
Websites to Get economical chips of SDRAM nad VRAM
FOR SOLUTION-3 that
Links Where to get SSDRAM Socket....
Suggestion to do it on Single sided PCB...
ANY OTHER SOLUTION [/color:8737ae6c30]
Thanks
Article: 89474Hello group, Can anyone tell me about the ML403 kit that Xilinx now advertises on there home page? Specifically, is there any source code for it? Do you pay the $895 and get all the software you need, or are there hidden cost for IP modules and the compiler software for the hard PC? Generally, I notice that the speed grades for the Virtex4 seem about twice that of the Spartan3s, although the fabric looks the same for the casual reader. Is the speed grade more a function of the Virtex4 IO SERDES functions, and not the fabric? And on the IOs, can the SERDES be used to accept a Camera Link specified 60MHz times 7 = 420MHz input rate on the specified 16 LVDS pairs? Or do I need RocketIO or MGT for this? Much oblidged, Brad Smallridge b r a d @ a i v i s i o n . c o m
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