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You could run both your 32-bit counter and the other set of registers off a fast (e. g. 100 MHz) clock. Detect the edge of the 1 kHz counter clock signal and make it a clock enable for the counter together with the 100 MHz clock. HTH, StephanArticle: 89751
If you use verilog than you may try icarus. For PC you can get it with
cygwin or windows version. For windows - http://armoid.com/icarus/
Use GTK waves to see VCD waves.
Since you mentioned that your VCD is quite large, than you may consider
to dump only part of the design and only on some of the simulation
time.
examples
//will dump all signal for all the time
initial begin
$dumpfile("1.dump");
$dumpvars(0, tb);
end
//Only three levels
initial begin
$dumpfile("1.dump");
$dumpvars(3, tb);
end
initial begin
#1000
$dumpfile("1.dump");
$dumpvars(0, tb);
end
Frank wrote:
> Thank you for the information. I will try that later.
>
> Frank
>
>
>
>
> "gallen" <arlencox@gmail.com> wrote in message
> news:1127194129.436216.289820@f14g2000cwb.googlegroups.com...
> > I can't really recommend IVI. It it's definitely not easy to use or
> > particularly stable. I'm also not a tremendous fan of Icarus. The
> > last version I used 0.8.1 (I think) had a memory leak so the
> > performance was abysmal. It was far outpaced by the slowed down
> > modelsim XE.
> >
> > If you can't spend money, I recommend gpl cver and gtk wave. They
> > aren't great, but they'll do the trick. I find cver to be slower than
> > modelsim by a fair bit, but it's faster once the limit is exceeded.
> >
> > http://www.pragmatic-c.com/gpl-cver/
> > http://home.nc.rr.com/gtkwave/
> >
> > I must give the warning that gtkwave loads the whole vcd into memory
> > and then some, so if you're opening 300MB VCD files, you really need to
> > have at least 1 GB of memory (maybe more). I know I have 768MB and it
> > thrashed until I killed it.
> >
> > There is no way you are going to get a free tool with a gui like
> > modelsim. Heck, most commercial tools don't have guis like modelsim.
> > As far as I know vcs and ncverilog don't have nice guis. With those
> > tools you do everything on the command line.
> >
> > Good luck,
> > Arlen
> >
Article: 89752I agree with Stephan. Making the whole design synchronous is the best solution. I was overly concerned with pointing out that the problem has nothing whatsoever to do with metastability, and I overlooked the simpler solution. Synchronous is the way to go, whenever possible. Peter Alfke, Xilinx (from home)Article: 89753
Andre,
I had this investigated some more. There is a difference between the
software functionality and the Handbook, but the Handbook is the official
line here. So the correct way to pack a register into an I/O from anywhere
in a design that is guaranteed to work in any future Quartus release is to
make a fast_output_register assignment on the register. Today it will work
if you make a fast_output_register assignment on a lower-level I/O, but this
is not officially supported and not guaranteed to work in a future release.
example syntax:
signal my_reg : std_logic;
attribute altera_attribute : string ;
attribute altera_attribute of my_reg : signal is "-name fast_output_register
on";
Hope this helps,
Subroto Datta
Altera Corp.
<ALuPin@web.de> wrote in message
news:1127459214.701460.285130@g47g2000cwa.googlegroups.com...
Hi Subroto,
>The useioff or altera_attribute="fast_output_register=on", can be made on
>the submodule of a design because it is really an assignment to a register
>to tell it to be packed into the I/O.
But the handbook says the following:
The useioff synthesis attribute takes a Boolean value and can only be
applied to the port declarations of a top-level Verilog HDL module or
VHDL entity (it is ignored if applied elsewhere).
So is it not possible to use "useioff" in submodules ?
Rgds
André
Article: 89754Hi, Almost all of the presentations from the 2005 MAPLD (Military and Aerospace Programmable Logic Device) International Conference, held earlier this month, are now on-line. There are a few items that need cleanup which will be taken care of soon. You may access the presentations by Session from the conference home page: http://klabs.org/mapld05 Comprehensive proceedings can be found at: http://klabs.org/mapld05/abstracts/ Papers will be posted in October. If you find any errors, please let me know. Regards, Rich Katz National Aeronautics and Space AdministrationArticle: 89755
But - I have an oddball case of a clock. One always runs at 1Khz. The other *May* run as fast as 100MHz but usually runs slower -- sometimes as slow as 100Hz. If I knew my variable clock was always fater than the 1KHz clock, the edge detection would work fine. Incidently, I already have a circuit similar to what you have in one of my other designs which does have a guaranteed fast clock. Thanks, Ed "Stephan Flock" <sflock@freenet.de> wrote in message news:dh354s$gcu$03$1@news.t-online.com... > You could run both your 32-bit counter and the other set of registers off > a > fast (e. g. 100 MHz) clock. Detect the edge of the 1 kHz counter clock > signal and make it a clock enable for the counter together with the 100 > MHz > clock. > > HTH, > Stephan > >Article: 89756
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1127539632.607707.192720@g44g2000cwa.googlegroups.com... > If I understand you right, you need to copy the 32-bit counter ontent > (which changes very slowly) into a fast-changing (fast-clocked) > register at asynchronous times. > I am sure that your problem is not metastability, but rather timing > uncertainty between the 32 register bits. Yeah, I agree - I normally just lump them together although I shouldn't. > My suggestion is to run the > 32-bit counter as a Gray counter. Since only one bit changes at any > time, a not-totally-synchronous transfer never results in a serious > error. Afterwards, you can convertthe gray code back to binary. > Binary-to-Gray conversion uses one XOR per bit, and is very fast. > Gray-to-binary involves a ripple chain, and may be more challenging at > 100 MHz, but I suppose you can do it off-line. Or you pipeline the > operation. I never thought of a gray counter. I'll look into this as it may be a better solution. I can always pipeline the conversion - I do have a dozen or so cycles to play with before I need to get the result out. Thanks, Ed > > As is often the case,,mtastabilty gets blamed here for a completely > different (and more solvable) problem. > Peter Alfke, Xilinx Applications >Article: 89757
GPE wrote: <snip> > I never thought of a gray counter. I'll look into this as it may be a > better solution. I can always pipeline the conversion - I do have a dozen > or so cycles to play with before I need to get the result out. What about dual port memory, or perhaps a special FIFO, given the extreme clock ratios ? [and the gray counter as well, for safety..] -jgArticle: 89758
I got this working in FreeBSD too.. well for some definition of "work" :) I found that if I run rpcbind and make sure my hostname is resolvable via DNS the Wind/U timeout is fast-ish.. (30 seconds or so) whereas without it, it takes several minutes(!) ktrace shows that a linux_socketcall() is attempted just prior to the error about weak client creds, and it returns EPERM. Unfortunately I don't know what the socketcall() is for/to/about since ktrace isn't very good at displaying that stuff and strace gives bogus results for linux binaries. I have found that it won't open files or projects though - the file dialog doesn't appear - instead you get an error dialog complaining that the path is too long :(Article: 89759
Dear FPGA and VHDL Experts, I am new to FPGA and VHDL. I would like to learn VHDL and start experimenting FPGA. I beleive I learn faster and better by experimenting. What would you recommend for beginners like me to getting started with VHDL and FPGA experimentation ? Which SW (for WinXP and/or Fedora Linux ) for VHDL? Which start-up experimentation board for FPGA? Which URL, books etc for easy to start experiment? Many thanks for your help. Kutaj VamorArticle: 89760
Hello,
is it possible to configure a Cyclone device connected to a shared
serial configuration bus using the nCE signal as DCLK enable? I
would like to configure it from a SecureDigital card using Passive
Serial mode and an external microcontroller responsible for generating
DCLK and SD protocol-specific communication with the card.
The configuration should be as fast as possible, so I don't want to
implement two separate data channels (SD => MCU and MCU => FPFA),
but to connect SD.MISO to FPGA.DATA0 and SD.CLK to
FPGA.DCLK and then simply generate the clock signal using the
MCU. But using this way I can read only a sector from the card,
then I must prepare the next sector and so on. This setup requires
communication with the card and, obviously, Cyclone should not
read configuration stream then. Can I set nCE to 1, do the necessary
sector setup,then set it back to 0 and send the next part of the stream?
Best regards
Piotr Wyderski
Article: 89761On Sun, 25 Sep 2005 19:33:27 +1000, "Kutaj Vamor" <kv> wrote: >Dear FPGA and VHDL Experts, > >I am new to FPGA and VHDL. I would like to learn VHDL and start >experimenting FPGA. I beleive I learn faster and better by experimenting. >What would you recommend for beginners like me to getting started with VHDL >and FPGA experimentation ? >Which SW (for WinXP and/or Fedora Linux ) for VHDL? >Which start-up experimentation board for FPGA? >Which URL, books etc for easy to start experiment? > >Many thanks for your help. > Go to http://www.fpga4fun.com/ . They have a number of tutorials and cheap development boards. Regards Anton ErasmusArticle: 89762
Hi, I have question about creating RPM and need help from xilinx expert. >From the xilinx application note, I should be able to output .ucf and .ngc (which contains the constraint information) from floorplaner after PAR. When I did that, the tool only outputs the .ucf file. One dos windows pops up and disappear immediately. And an error message window pops up saying "ngc builder did not run successfully". I do not have any other information in order to debug... I then tried another approach. After PAR, I use floorplaner to output .ucf file only. Then rename the .ucf file to .xcf file. Then I go back to XST, try to synthesize using this xcf file. The problem I have is that translation/mapping seems to create some new instance name which can not be found in rtl. The XST fails due to some instance in xcf file can not be found in the design. Does anyone know how to solve this problem or to generation more information for debug? Thank you very much. JasonArticle: 89763
Hi Kutaj,
I recommend downloading free Xilinx ISE WebPACK design software from
Xilinx since at least Xilinx gives you a very slow HDL simulator
(ModelSim XE-Starter) unlike Altera, Actel, or Lattice.
I believe ModelSim XE-Starter supports Windows only, so I recommend
sticking to Windows for the time being.
I also recommend learning Verilog instead of VHDL because Verilog is
lighter and simpler language than VHDL. (VHDL is a "heavier" language
than Verilog in my opinion.)
I know there are many different ways to learn HDL and FPGA, but
one method I recommend doing is to attach your FPGA to a desktop
computer via PCI bus, and experiment with the FPGA.
I myself tried learning HDL (Verilog and VHDL) reading books written
about them, but it didn't work out because either the examples in the
books were too short, boring (Like traffic light or vending machine
state machine example often used in HDL books.), or wasn't something
large enough like accessing an FPGA from a computer.
I always thought that attaching one's own FPGA to a desktop computer
will be an interesting project, so developed my own PCI interface to do
so, and in the process, I learned Verilog HDL. (Learned VHDL later by
porting Verilog HDL code to VHDL.)
PCI bus is a fairly complex bus (PCI Express is even worse.) which is
certainly intimidating for FPGA beginners, but the use of a PCI IP
(Intellectual Property) core can largely solve the problem, allowing the
FPGA beginner to concentrate on the user logic behind the PCI bus.
BDS XPCI PCI IP core is a Xilinx (TM) LogiCORE (TM) PCI
compatible (replacement) PCI IP core developed by Brace Design Solutions.
BDS XPCI32 PCI IP core is available for as little as $100 for
non-commercial, non-profit, personal use, and the same 64-bit version
BDS XPCI64 PCI IP core (Includes BDS XPCI32 PCI IP core) goes for $200.
Since the pricing starts at only $100, it is ideal for HDL learners,
FPGA beginners, FPGA hobbyists, computer hardware enthusiasts, or
student graduation projects.
BDS XPCI PCI IP core comes with a PCI testbench for Verilog HDL which
allows the user to simulate the design extensively on an HDL simulator
like ModelSim before firing up the FPGA.
VHDL support is currently poor, but VHDL porting of reference designs
and PCI testbench should be available in a month.
BDS XPCI PCI IP core officially supports the following PCI boards.
- Insight Electronics Spartan-II 150 PCI (Already discontinued)
- Insight Electronics Spartan-II 200 PCI Development Kit
http://www.memec.com/uploaded/SpartanII200PCI.pdf
BDS XPCI PCI IP core "unofficially" supports the following PCI boards.
- Avnet Xilinx Spartan-3 Evaluation Kit
http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D7816%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html
http://www.em.avnet.com/ctf_shared/evk/df2df2usa/Xilinx%20Spartan-3%20Evaluation%20Kit%20-%20Brief%20022504F.pdf
- Enterpoint Broaddown2 Development Board
http://www.enterpoint.co.uk/moelbryn/broaddown2.html
So with BDS XPCI PCI IP core, almost anyone can make their own PCI
device for about $400 to $500. ($300 to $400 for the board + $100 for
BDS XPCI32 PCI IP core)
For commercial users who want to modify a Xilinx LogiCORE PCI or want to
convert a design that uses Xilinx LogiCORE PCI to an ASIC (FPGA to ASIC
conversion), BDS XPCI PCI IP core is also available in Verilog HDL RTL.
For more information, visit Brace Design Solutions website at
http://www.bracedesignsolutions.com.
Kevin Brace
Kutaj Vamor wrote:
> Dear FPGA and VHDL Experts,
>
> I am new to FPGA and VHDL. I would like to learn VHDL and start
> experimenting FPGA. I beleive I learn faster and better by experimenting.
> What would you recommend for beginners like me to getting started with VHDL
> and FPGA experimentation ?
> Which SW (for WinXP and/or Fedora Linux ) for VHDL?
> Which start-up experimentation board for FPGA?
> Which URL, books etc for easy to start experiment?
>
> Many thanks for your help.
>
> Kutaj Vamor
>
>
>
>
>
--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com
Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
Article: 89764
To all,
I had compiled my SOPC design with my master peripheral + sdram
controller + my own slave peripheral (address generator) and when I
imported the VHDL file into a new Modelsim project and tried to compile
only this, there was a library file missing that the SOPC VHDL file
declares (i.e. Altera_VHDL_Support). The error produced is: library
"altera_vhdl_support" is not present. I searched for this, and it
seems that SOPC places a package VHDL file within the directory the
SOPC design was compiled in while using Quartus. However, in
Modelsim when I tried to include this VHDL file in the Modelsim project
and compile it into the default "work" library, the SOPC design
still can not locate this library and still produces an error in
compilation. Can anyone tell me where to locate this particular
library so that I can try to compile it properly? I would really
appreciate it.
Thanks,
Pino
Article: 89765> Some one already told me "Jbits is dead" but didn't explain why ! Because http://www.megacz.com/research/bitstream.secrecy.xt - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 89766
Thanks a lot guys! "Simon Heinzle" <sheinzle@student.ethz.ch> wrote in message news:4333e8e2$1@news1.ethz.ch... > To exchange flags (1 bit signals) between two unrelated clocks, a single > synchronizer flip flop to clock that signal is used normally. However, > under violations of setup/hold times of the flip flop, metastability can > occur. > > On a Virtex2 Pro, does metastability occur often? Does adding a second (or > even third) flip flop after the synchronizer flip flop help or is that > overcautious? > > Best Regards, > Simon Heinzle > > >Article: 89767
Hi, when fitting my design (120MHz clock from PLL) I get some timing violations reported. For example: Slack -2.115 ns Actual fmax 79.61MHz >From reg_starge: REG_STAGE_1 | l_ulpi_ack To ... l_ulpi_ack_h1 >From Clock pll_bank1: ...|clk0 Required Setup Relationship 4.166ns Required Longest P2P Time 4.246ns Actual Longerst P2P Time 6.361ns To correct these timing violations I open the Assignment Editor and specify a timing assignment for these registered nodes: >From l_ulpi_ack To l_ulpi_ack_h1 Assignment Name Setup Relationship Value 4 ns Enabled Yes Is that assignment sufficient to avoid the timing violation above ? Or would be an assignment "Maximum Delay" more appropiate ? What is the recommended approach ? Thank you for your help and opinion. Rgds Andr=E9Article: 89768
Hi, I'd like to learn programming a micro chip. I've heard the Altera is popular. Which one should I specifically deal with, and how do I build a burner (programming it) for it? (I need a circuit diagram) ThanksArticle: 89769
Hi I have wasted several weeks trying to get xilinx libxil to work, only to find that it doesnt work. I found that it does not acknowledge receives. Further more libxil is very limited. Therefore i am trying to find examples of socket programming for spartan 3 microblaze. I have seen the echo request server, but Im looking at a higher level. Im not sure how to set up the timer, what include files i need, and how to initialise properly? Regards --------------= Posted using GrabIt =---------------- ------= Binary Usenet downloading made easy =--------- -= Get GrabIt for free from http://www.shemes.com/ =-Article: 89770
Hello. Now I'm using Xilinx virtex2 (xc2v6000). I use blockram as dpram with read/write port a and read only port b. Since xc2v6000 has only about 1800k blockram inside, I met some limits on design because about 9000k or more dprams needed in my circuit. I tried to find some external dpram chips for several days, but I couldn't. The spec. of dpram which I need is: port a addr 10bit port a data 8bit port a we port a clk port b addr 10bit port b data 8bit port b clk That's all. Could you please recommend one?Article: 89771
Hi Adrian >> Debian Sarge with 2.4.6. and WinDriver v6.03 (orig xilinx) or v7.01 >> gives: > > Kernel 2.4.6? This is pretty old, albeit the real problem I suggest > you first update your kernel. Mh, tried different versions from 2.4.6, 2.4.26 and 2.6.13 all with the same error :-( >> // *** BATCH CMD : setCable -port ttyS1 -baud -1 > > ttyS1 is a serial (probably rs232) port. I don't own a usb cable, > but even if it emulates a serial port I guess it won't be called ttyS1 > (ttyS1 is usually the second serial port, in DOS-speak COM2). No i *think* that this is just a message because they ported it from the serial cable? I haven't seen any use of the usb serial driver from impact, windriver etc. > It should also be noted that it is always a good idea to use > up-to-date cable drivers, at least my parallel cable needs > the new windriver (>7.0.0) if I don't want to patch it for > using it with kernels newer than 2.6.11. Yes, the parallel cable works here without problems. But we want do buy more of these xup boards but if we have to buy new cables for each of these boards it gets to expensive. Thanks STArticle: 89772
"Brian Davis" <brimdavis@aol.com> wrote in message news:1127441657.143241.31760@g47g2000cwa.googlegroups.com... > acetylcholinerd@gmail.com wrote: > > > > If we break one of those pairs and run a (say) 70 MHz clock > > on the + wire and a 70 MHz data stream on the - > > > Keep it differential. > > > >I just worry about the SI problems with running a 70 MHz > > clock over 1m of cable... > > > Offhand, for 70 Mhz out and 280 Mbps back, I'd run the > drivers as LVDS_EXT, layout for a 3dB differential attenuator > at each end of the link (Note 1), use the LVDS_25_DCI on-chip > terminations at the receivers, and simulate & prototype before > relying on this advice. > > > > >I'll happily take any other suggestions > > > And now for something completely different... > > If you can live with 70 Mbps of outgoing data on a > cable with bandwidth to spare, try this for a clock > recovery scheme (untested, designed-as-I-type-this, > probably been done better before): > > Phase modulate your outgoing 70 Mhz clock's falling > edges to encode the data, using a 140 MHz master clock > and DDR output regs (Note 2): > > for a zero, send -___ > > for a one, send ---_ > > So 10110 would be ---_-___---_---_-___ > > Which has the rising edges all neatly lined up with > those of the original source clock. > > At the receiving end, divide this by two (Note 3) > with a rising edge FF to get an 35 Mhz clock, which > now has no duty cycle modulation. > > Use the daughtercard DCMs to multiply this 35 MHz > clock back to 70 Mhz to re-clock the input data > ( a fixed 180 or 270 phase shift should do, this is > a forwarded clock so cable prop delay doesn't matter). > > Also use the DCMs to generate a daughtercard 140 MHz to > use as a DDR output clock for your outgoing 280 Mbps data. > > Back on the motherboard, you'll need a dynamic or > cable-length-calibrated fixed phase shift of the master > 140 Mhz to re-clock the data, as a two meter round trip > cable delay is longer than a bit period at 280 Mbps. > > have fun, > Brian > > (Note 1) Digikey, 3db 100 ohm diff. 0404, EXB-24AB3CR8X > > (Note 2) using a good differential osc. to directly > clock the output DDR register, without using a DCM, > will avoid cascading two DCMs in the overall link. > SDR with 280 MHz clock or DDR with 140 Mhz clock. > > (Note 3) the DCMs have an input divider, which may > be rising edge triggered > Hi, Normally, you houldn't neeed the divide by 2 and cable stub: just use the fact that DCMs align to the rising edge and use their CLK180 to clock your data in. Regards, Alvin.Article: 89773
Hi Marco, you need to look what the license terms are for that specific core. Every developer on opencores.org chooses the license term themself for their project. Maybe asked direct the developer of that core. Regards, GuenterArticle: 89774
"Guenter" <dannoritzer@web.de> wrote in message news:1127732261.419821.118380@g43g2000cwa.googlegroups.com... > Hi Marco, > > you need to look what the license terms are for that specific core. > Every developer on opencores.org chooses the license term themself for > their project. > > Maybe asked direct the developer of that core. > > Regards, > > Guenter > Ok, I'll do it. Many Thanks Marco
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z