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Hello! I have an application with a Spartan-3 mainboard and 3 spartan-3-based daughterboards -- we had planned on connecting the daughterboards to the mainboard via SATA connectors, and running a 300 Mbps LVDS link in each direction (M->D and D->M). We had hoped that the daughterboards could do clock-recovery of the incoming (M->D) 300 Mbps stream, and then (since effectively the whole system would be synchronous) this would eliminate the need for explicit clock-recovery on the mainboard (which would be receiving the 3 LVDS streams from the daughterboard. However, Xilinx engineers told me yesterday that the Spartan-3s have no built-in CDR hardware (which is required to make XAPP250 "work"). So: 1. Can anyone recommend any external chips to do this sort of CDR? I've seen clock and data retiming chips available from Maxim, etc. but they all look targeted at optical applications. 2. If we run the M->D link at 75 Mbps, recover that clock, use it to drive the daughterboard FPGA, and then (using a DCM) clock-quadruple it to 300 MHz (and use that to send out the 8b/10b data on the D->M differential pair) can I assume that the phase relationship between the D and the M FPGA will be constant (assuming the master FPGA is also running a 4x clock)? I'll happily take any other suggestions -- I wish I could just feed the 8b/10b stream into the DCM, but I guess life isn't that simple :) Thanks, EricArticle: 89651
a-nerd, Have you considered the use of the dynamic phaseshift feature of the DCM? By having a synchronous system, one can use the clock, shifting its phase, until the data received is in the center of the "eye." Austin acetylcholinerd@gmail.com wrote: > Hello! I have an application with a Spartan-3 mainboard and 3 > spartan-3-based daughterboards -- we had planned on connecting the > daughterboards to the mainboard via SATA connectors, and running a 300 > Mbps LVDS link in each direction (M->D and D->M). We had hoped that the > daughterboards could do clock-recovery of the incoming (M->D) 300 Mbps > stream, and then (since effectively the whole system would be > synchronous) this would eliminate the need for explicit clock-recovery > on the mainboard (which would be receiving the 3 LVDS streams from the > daughterboard. > > However, Xilinx engineers told me yesterday that the Spartan-3s have no > built-in CDR hardware (which is required to make XAPP250 "work"). So: > > 1. Can anyone recommend any external chips to do this sort of CDR? I've > seen clock and data retiming chips available from Maxim, etc. but they > all look targeted at optical applications. > > 2. If we run the M->D link at 75 Mbps, recover that clock, use it to > drive the daughterboard FPGA, and then (using a DCM) clock-quadruple it > to 300 MHz (and use that to send out the 8b/10b data on the D->M > differential pair) can I assume that the phase relationship between the > D and the M FPGA will be constant (assuming the master FPGA is also > running a 4x clock)? > > I'll happily take any other suggestions -- I wish I could just feed the > 8b/10b stream into the DCM, but I guess life isn't that simple :) > > > Thanks, > > Eric >Article: 89652
Austin,
Thanks for the quick reply; I guess my question is then "how do I
get a synchronous system" using this configuration. XAPP250 ("Clock and
Data recovery with coded data streams") is listed under the Spartan-3
Application Notes, but as " There is no CDR in Spartan-3", I was hoping
to get suggestions for external recovery options.
Are there any reference designs or recommendations for using the
dynamic phaseshift features of the DCM to adjust for phase offset in
real-time?
On that note, are there any reference-designs or examples of the
Spartan-3 doing > 300 Mbps LVDS serial IO? I'm a bit worried about the
timing of the IOBs, even though I see the 622 Mbps rate all over
xilinx.com in conjunction with the S-3.
Thanks again for making such a great product,
Eric
Article: 89653Hi. I have a simple board with an Spartan 3 FPGA and a AD connected to it. The board is configured via JTAG using the Xilix Platform Cable USB (24 Mhz). What I would like to do is to capture the data from the A/D converter to the computer via JTAG. Does anybody know of a good way to do this with the Xilinx applications (Chipscope, System Generator, etc)? Or maybe with a 3rd party tool? I appreciate any information, JAnArticle: 89654
Yeah, but system generator does not seem to support the cable. At least in my setup ISE, and chipscope find it, but Sysgen demands Parallel Cable 4. Anyone have a different experience? Later, JAnArticle: 89655
janbeck@gmail.com wrote: > Hi. > I have a simple board with an Spartan 3 FPGA and a AD connected to it. > The board is configured via JTAG using the Xilix Platform Cable USB (24 > Mhz). What I would like to do is to capture the data from the A/D > converter to the computer via JTAG. Does anybody know of a good way to > do this with the Xilinx applications (Chipscope, System Generator, > etc)? Or maybe with a 3rd party tool? > The easiest why to do this would be with a ChipScope ILA core with the data bus connected to your ADC interface. You will be able to use the graphing option in ChipScope to visually display the data as well. If you're only want to look at the ADC output in human time, as opposed to cycle-by-cycle, you could use a ChipScope Virtual I/O (VIO) core instead of an ILA. You won't be able to graph it, but it can display it any radix and scale that you want. EdArticle: 89656
Brad Smallridge wrote: > Hello group, > > How does one combine two models? > > Specifically, I have a Spartan3 with some models > that I have made and connected to then Spartan3 > is a NBT SRAM, which I have recently downloaded > from the manufacturers web site. All in VHDL. I assume you wish to simulate this? This is Test Bench 101. You write a test bench and instantiate the DUT (your FPGA) and the SRAM model and any other models needed. I assume you don't code your FPGAs in one huge source file with one huge entity, right? > And there is (sic) relatively short traces from the > Spartan3 to the SRAM. You don't need to model trace delay if you're doing a functional simulation.Article: 89657
For the sake of completion VCS does have GUI, new one is called DVE and is quite powerful. I wouldn't comment (yet) on its stability, it has lot of good features (that you usually find/expect in such GUI). Specifically I like their assertion debug stuff. Last time I played with Simvision (NC's GUI), it looked very stable and very nice to use. I particularly liked their TCL interface - very powerful indeed. HTH Ajeetha www.noveldv.comArticle: 89658
It seems like you want to "count" the 1s in a 150-bit wide word, coming in every 100 ns = 10 MHz. Here is how I would do it: Use 6 or 7 dual-ported BlockRAMs as LUTs. Each BlockRAM is used as a ROM, organized 4k x 4,i.e. with 12 address bits and 4 output bits. The ROM stores the value of the number of ones on the address inputs. One ROM takes care of 12 inputs, but since it is dual-ported, each BlockRAM takes care of 24 inputs, generating two independent 4-bit outputs. Six BlockRAMs thus cover 144 inputs, and generate 12 independent 4-bit binary numbers in less than 4 ns. The remaining 96 ns can be used in simpler adder structures, or in a 12-step sequential accumulator running at, say, 200 MHz. Peter Alfke, Xilinx ApplicationsArticle: 89659
Why do you even think of clock recovery, which has complicated implications, like 8B10B encoding. Just buid the whole system as a straightforward synchronous system with one common clock. Then analyze the undesired clocking and data propagation delays, and compensate for them by using the dynamic phase shift option in the DCMs, effectively adjusting various clocks with a granularity of 1/256 clock period, or 50 ps, whichever is greater. That's what Austin suggested, I am just embellishing his explanation. PeterArticle: 89660
http://www.xilinx.com/bvdocs/appnotes/xapp774.pdf
http://www.xilinx.com/bvdocs/appnotes/xapp806.pdf
http://www.xilinx.com/bvdocs/appnotes/xapp764.pdf
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=19815
Should get you started.
Perhaps I do not understand the application: is there no clock at all,
just data from point A to point B?
If so, you will need some sort of PLL to recover the clock.
Xapp 224, 250, and 704 may be useful.
Austin
acetylcholinerd@gmail.com wrote:
> Austin,
> Thanks for the quick reply; I guess my question is then "how do I
> get a synchronous system" using this configuration. XAPP250 ("Clock and
> Data recovery with coded data streams") is listed under the Spartan-3
> Application Notes, but as " There is no CDR in Spartan-3", I was hoping
> to get suggestions for external recovery options.
> Are there any reference designs or recommendations for using the
> dynamic phaseshift features of the DCM to adjust for phase offset in
> real-time?
> On that note, are there any reference-designs or examples of the
> Spartan-3 doing > 300 Mbps LVDS serial IO? I'm a bit worried about the
> timing of the IOBs, even though I see the 622 Mbps rate all over
> xilinx.com in conjunction with the S-3.
>
> Thanks again for making such a great product,
>
> Eric
>
Article: 89661Hi, I am trying to implement a schematic design. My problem is that when I try to assign a constant binary number to one of the two inputs of a comparator, I can't find the way to do it. Anyone know how it can be done in Xilinx schematic? Thanks in advance for your help. Regards, JorgeArticle: 89662
I have installed the JBITS 3.0 SDK from Xilinx. How do I know that the bit pattern has actually changed before downloading on to the chip? I don't see any difference in the sizes of the input and output .bit file. Is this to be expected? I understand that JBITS 2.8 had BoardScope; but apparently Xilinx have removed BoardScope from 3.0. Can anybody help?Article: 89663
stbcasa wrote: >Hi, > >I am trying to implement a schematic design. My problem is that when I >try to assign a constant binary number to one of the two inputs of a >comparator, I can't find the way to do it. Anyone know how it can be >done in Xilinx schematic? Thanks in advance for your help. > > You use XBLOX to create a new library part, from the "CONST" type. You assign the value to it as needed. You need a different library part for each constant value, kind of cumbersome, but that's how it works. Then, you instantiate the library part on your schematic, and connect the output bus to the input as needed. JonArticle: 89664
Hi, I am trying to decide which Altera programming cable to purchase. Can anyone tell me how long it takes them to program an Altera EPCS16 and/or EPCS64 using the USB Blaster and/or ByteBlaster II? So I can do an apples-to-apples comparison: approximately how big is the configuration file and what's the processor speed of your host computer? Thanks!Article: 89665
Our application is we have one main board and 3 daughter boards, up to 1m away, and we are constrained to essentially using seven wires to connect each daughter board to the main board. For this sort of distance, we wanted to go LVDS in both directions, but to keep everything synchronous, that would require that the B->D lvds pair also contain the clock; clock recovery was going to let us still keep everything synchronous. We knew we'd need a PLL :) We've decided to go with a single-ended clock/data pair on one set of wires and a (clock-multiplied) LVDS pair for the receiver (from daughterboard -> mainboard), like Austin suggested. But Austin, I'm really curious, how does xapp250 help with a spartan-3 device? Thanks!Article: 89666
Hi Andy, Thanks for spending the time. > I assume you wish to simulate this? Yes, with ModelSim from the Xilinx webpack. > This is Test Bench 101. You write a test bench and instantiate the DUT > (your FPGA) and the SRAM model and any other models needed. Yes, I'm sure it seems rather obvious to you. However, it may not be to everyone. And there are very few text book examples of this. It seems by what you are saying that the test bench would need to drive the inputs to the SRAM, unless there is some mechanism by which models can be tied together from the test bench. What is that? I had thought that I would need a higher model, call it Board, that would instantiate both the FPGA, which I call top3, and the memory model. Board then would have something specifying the physical wires, like a signal for each of the traces, and an assignment statement (right term?) , like this: signal board_srama : std_logic_vector(20 downto 0); begin board_srama<=u3_srama; -- fpga to board mem1: mem_model port map( . . . mem_a <= board_srama, -- board to fpga . . . ) which seems to make sense to me except for the DQs which are bidirectional. > I assume you don't code your FPGAs in one huge source file with one > huge entity, right? I usually start big and then when I get into trouble I start pulling it apart and modeling the chunks. I'm not good at top down design because I'm still not sure what can be done on the bottom. Then there is the problem of running tests on hierarchial designs, where it seems to me to be quite time consuming to run a test output on a lower hierarchy to an output pin. The short answer is sometimes. >> And there is (sic) relatively short traces from the >> Spartan3 to the SRAM. > You don't need to model trace delay if you're doing a functional > simulation. Well at 166MHz, the SRAM speed, I thought I should do more than functional simulations. Do you know how to do that? BradArticle: 89667
OK, Xapp250 can also be done in S3 as there is nothing specific in there that isn't in S3. The idea that you put all the digital stuff to do CDR in the FPGA, and then have the LPF and VCO off chip is not new. One lane that recovers clock, along with using the variable phase shift, could then be used to time all the other lanes. Austin acetylcholinerd@gmail.com wrote: > Our application is we have one main board and 3 daughter boards, up to > 1m away, and we are constrained to essentially using seven wires to > connect each daughter board to the main board. For this sort of > distance, we wanted to go LVDS in both directions, but to keep > everything synchronous, that would require that the B->D lvds pair also > contain the clock; clock recovery was going to let us still keep > everything synchronous. We knew we'd need a PLL :) > > We've decided to go with a single-ended clock/data pair on one set of > wires and a (clock-multiplied) LVDS pair for the receiver (from > daughterboard -> mainboard), like Austin suggested. But Austin, I'm > really curious, how does xapp250 help with a spartan-3 device? > > Thanks! >Article: 89668
Hello all, I want to create an IP master on the OPB. I am using Xilinx Virtex2 (xc2v2000), and Xilinx platform studio (EDK) version 7.1.02i on the Xilinx Multimedia Board. I have tried looking everywhere for my answer and after a week of time-well-experienced I decided to ask the experts. I have a MicroBlaze (MB) as a master, an RS232 (UART) as a slave, LEDs (GPIO) as a slave, and memory as slave. I wanted to add my own IP master on the OPB. I created the IP using the "Create/Import Peripheral" wizard. I have tested my IP (simulation) and it works fine. Once I attach it to the bus, my IP doesn't seem to be executing anything. So I used ChipScope Pro 7.1i (Which is an amazing tool to analyze in-board signals) to tap into my request and acknowledge signals. What I noticed is that my IP doesn't seem to ever get an acknowledge. It Requested a read but never gets an acknowledge. So I realized, since there are more than one master on the bus I have to add an OPB arbiter. I added the OPB arbiter, but now I only get 16 characters on my RS232 output and no more LEDs flashing and if I tap into my IP signals I still see that my request has not been acknowledged. Can some please give me any direction? Thank you very much in advance. A side question, I noticed that the arbiter needs a device block ID (C_DEV_BLK_ID) parameter from every master on the OPB to identify them respectively. Where is this device block ID parameter for the MB and what other parameters do I have to set on the arbiter and custom IP. Peace, MohArticle: 89669
Hello Nitesh, I think you might want to consider adding an OPB arbiter. Even after adding the OPB arbiter you might get some problems assigning different masters an ID (C_DEV_BLK_ID) value to have the arbiter identify the respective masters. I just posted this messages today and if I get an answer it might be of some help to you or you might be able to help me with my issue: (thanks in advance) Hello all, I want to create an IP master on the OPB. I am using Xilinx Virtex2 (xc2v2000), and Xilinx platform studio (EDK) version 7.1.02i on the Xilinx Multimedia Board. I have tried looking everywhere for my answer and after a week of time-well-experienced I decided to ask the experts. I have a MicroBlaze (MB) as a master, an RS232 (UART) as a slave, LEDs (GPIO) as a slave, and memory as slave. I wanted to add my own IP master on the OPB. I created the IP using the "Create/Import Peripheral" wizard. I have tested my IP (simulation) and it works fine. Once I attach it to the bus, my IP doesn't seem to be executing anything. So I used ChipScope Pro 7.1i (Which is an amazing tool to analyze in-board signals) to tap into my request and acknowledge signals. What I noticed is that my IP doesn't seem to ever get an acknowledge. It Requested a read but never gets an acknowledge. So I realized, since there are more than one master on the bus I have to add an OPB arbiter. I added the OPB arbiter, but now I only get 16 characters on my RS232 output and no more LEDs flashing and if I tap into my IP signals I still see that my request has not been acknowledged. Can some please give me any direction? Thank you very much in advance. A side question, I noticed that the arbiter needs a device block ID (C_DEV_BLK_ID) parameter from every master on the OPB to identify them respectively. Where is this device block ID parameter for the MB and what other parameters do I have to set on the arbiter and custom IP. Peace, Moh Nitesh wrote: > I have designed a small module usilng vhdl.I converted this module > using IPIF and created an IP.Now I added this IP into my design as a > master/slave module to the OPB bus.I have to inititate a transaction > from my module to the OPB busi.e I want to send some data to the slave > module connected to the opb bus. > > One thing I have noticed is that there is no M_Dbus as output of IPIF > to OPB bus. > > I enable the IP2Bus_Wrreq(user logic to IPIF) high and wait for the > BUS2IP_wrack signal.But nothing happens.Also there is no change in the > M_request signal of the IPIF(on the OPB bus side)which is steady at 0 > The following is the IPIF wrapper: > port > ( > -- ADD USER PORTS BELOW THIS LINE ------------------ > --USER ports added here > -- ADD USER PORTS ABOVE THIS LINE ------------------ > > -- DO NOT EDIT BELOW THIS LINE --------------------- > -- Bus protocol ports, do not add to or delete > OPB_Clk : in std_logic; > OPB_Rst : in std_logic; > Sl_DBus : out std_logic_vector(0 to > C_OPB_DWIDTH-1); > Sl_errAck : out std_logic; > Sl_retry : out std_logic; > Sl_toutSup : out std_logic; > Sl_xferAck : out std_logic; > OPB_ABus : in std_logic_vector(0 to > C_OPB_AWIDTH-1); > OPB_BE : in std_logic_vector(0 to > C_OPB_DWIDTH/8-1); > OPB_DBus : in std_logic_vector(0 to > C_OPB_DWIDTH-1); > OPB_RNW : in std_logic; > OPB_select : in std_logic; > OPB_seqAddr : in std_logic; > M_ABus : out std_logic_vector(0 to > C_OPB_AWIDTH-1); > M_BE : out std_logic_vector(0 to > C_OPB_DWIDTH/8-1); > M_busLock : out std_logic; > M_request : out std_logic; > M_RNW : out std_logic; > M_select : out std_logic; > M_seqAddr : out std_logic; > OPB_errAck : in std_logic; > OPB_MGrant : in std_logic; > OPB_retry : in std_logic; > OPB_timeout : in std_logic; > OPB_xferAck : in std_logic > -- DO NOT EDIT ABOVE THIS LINE --------------------- > ); > > What could be the problem.Is there some other signal that thas to be > tken care of? > Is there some other way other than IPIF that I can add my module as a > master on the OPB bus. > Thanks, > NiteshArticle: 89670
Hi, Make sure that you have your XILINX and PATH environment variables pointing to the correct location. Regarding the XST error, is it possible that there is no linefeed after the one line in your .xcf file? I have seen cases where, without the linefeed after the last line, it is not interpreted correctly. StephanArticle: 89671
ModelSim is the best simulator you can buy; it's the industry standard. Unfortunately it's very expensive.Article: 89672
"Sean Durkin" <smd@despammed.com> wrote in message news:43315ac8$1@news.fhg.de... > GPE wrote: >> Wouldn't it be slick if Xilinx would offer USB as one of the available >> configuration modes for their FPGA config memories! > They do... You can buy the "USB Platform Cable" for about $150. It's the > same as the Parallel Cable 4, just hooks up to an USB2 port. Works much > more reliable than the parallel cable. ... well.... that's not exactly what I was thinking of. I was thinking of the USB built into the part. This way you could just add a USB connector to your board and not worry about users buying programming cables. I know this can be done adding an FTDI part to your design and then using a JTAG programmable memory such as the ST combo Flash/SRAM memories and using a Xilinx Spartan 3E part ... whenever those are out. But I still think it would be nice to cut the part count down further. -- Ed > > cu, > SeanArticle: 89673
Altera has NIOS (16-bit) and NIOS II (32-bit) uProc embedded. It offers performance/low-cost flavors. And allows users to built custom instructions. Thanks,Article: 89674
Assignments made in the HDL files cannot be seen in the Assignment Editor. However you can make the following assignments in a submodule: The useioff or altera_attribute="fast_output_register=on", can be made on the submodule of a design because it is really an assignment to a register to tell it to be packed into the I/O. Most other assignments (e.g. chip_pin to give a pin location) cannot be made on a submodule. Hope this helps, Subroto Datta Altera Corp. <ALuPin@web.de> wrote in message news:1127313138.878179.20220@g14g2000cwa.googlegroups.com... Hi Subroto, thank you for the link. One more question: I have put the attributes into my VHDL code. (in the ENTITY declaration). After compilation and synthesis I can see in the "Fitter Netlist Optimizations" that the signals have been routed into Fast Output Registers. But where do I see that in the Assignment Editor ? Is it visible there at all ? Are the attributes also valid if I use them in a submodule of my design ? Rgds André
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