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i write a frequency division module(name it "pre_freq_div") in order to output different frequency related to the division coefficient input,and the coefficient may be large(14-bit). this module get synthesized correctly independently. i also simulate it in modelsim se 6.0, the wave is perfect, i think. But when this module is getting into use from top level design,the systhesis tool tell me: Synthesizing Unit <pre_freq_div>. Related source file is pre_freq_div.v. Register <counter> equivalent to <freq_out> has been removed ERROR:Xst:739 - Failed to synthesize logic for signal <freq_out>. ERROR:Xst:1431 - Failed to synthesize unit <pre_freq_div>.Article: 87076
module pre_freq_div(clk,_reset,div_coef,freq_out); input clk,_reset; input [13:0] div_coef; output freq_out; reg freq_out; reg [13:0] counter; always @ (posedge clk) begin if(_reset==0) begin freq_out=0; counter=0; end else begin if(div_coef==14'b0) freq_out=0; else begin if(counter!=div_coef) begin counter=counter+1; freq_out=freq_out; end else begin counter=0; freq_out=~freq_out; end end end end endmoduleArticle: 87077
Chinix wrote: > i write a frequency division module(name it "pre_freq_div") in order to > output different frequency related to the division coefficient > input,and the coefficient may be large(14-bit). > this module get synthesized correctly independently. i also simulate it > in modelsim se 6.0, the wave is perfect, i think. > But when this module is getting into use from top level design,the > systhesis tool tell me: > Synthesizing Unit <pre_freq_div>. > Related source file is pre_freq_div.v. > Register <counter> equivalent to <freq_out> has been removed This error bothers me. how can <counter>, a 14-bit vector be equivalent to <freq_out>, a scalar value? This seems to be a clue. There's nothing obviously wrong with the code in this module, so I'd think there's a problem with the instantiation at the top level. The first place I'd look is the reset input, which is one thing that could cause <counter> to be equivalent to <freq_out>. Is it possible that XST doesn't like a leading underscore in the module input _reset? Also _reset is active low. Did you by mistake tie it to zero or leave it out of the port list at the top level? Another thing that could cause this is the lack of a clk input to the module. Also if div_coef is zero. I think we'd need to see the instantiation code to find the problem. > ERROR:Xst:739 - Failed to synthesize logic for signal <freq_out>. > ERROR:Xst:1431 - Failed to synthesize unit <pre_freq_div>.Article: 87078
Any flip-flop that has an asynchronous reset or preset term will be initialized automatically when the FPGA is loaded from the bitstream. The standard templates for flip-flops are available in the Language Templates options of ISE. Menu: Edit --> Language Templates... Navigate to: Verilog --> Synthesis Templates --> Flip Flops --> D Flip Flop with Asynchronous Reset This shows the standard template for inferring flip-flops with initialization. Note that any flip-flop that doesn't have an async reset term will default to zero after bitstream load. vssumesh wrote: > Hello all, > Is there any way i can initialise values into the Xilinx FPGA FF. I > am working on the Virtex E FPGA. Please tell me how can i achive that > through verilog. > Thank youArticle: 87079
thanks, that was, ofcourse, exactly the problem. is there a faq on why i should use std.all instead of arith.all unsigned.all? ISE inserts the use statements for me... so i was just trusting that it put in the appropriate statements.Article: 87080
_reset is a global input signal,so it won't be influenced by the upper leven unit,i think. i simulated and synthesized the module independently,it all went well,so i don't think an underscore makes any differents.Article: 87081
It may be that you have confused map by defining both TBUF outputs to be external macro pins. Since both TBUF outputs are connected to the same net (internally in the macro) you only need to define one of those outputs to be an external pin. -PeteArticle: 87082
Sounds great. Instead of a simple filter, undersampling is enough as it is, in fact, a crude LP filter. Is this correct? If were actually using filter, what specs would you use? Cutoff at 1ms, 3dB point at .5ms? Thanks BenArticle: 87083
Hello everyone, I have run into a problem when i was using the Piplined Divider ipcore(ISE7.1i). I wanna utilize it to calculate the reciprocal 1/X.As the Data Sheet describes,I input divident 01(signed) and a random divisor which is improper fraction. The divisor's bitwidth I assumed is 17,with binary point is 10,and the remainder's bitwidth is 17. However,the bitsteam inputed to divisor is treated as signed integer.So the precision of result is warped. There is another but worse problem.When the divisor becomes small,such as 0.02,the result is absolutely wrong.I think this is the problem of overflow. Are there any good methods to deal with these prob? RegardsArticle: 87084
Analyze the requirements. You must suppress the longest bounce, but you also want to react to the fastest possible legitimate operation. Establish these two times ( say 10 ms for longest bounce, and 100 ms for fastest human action) and put the cut-off somewhere in the middle. Peter AlfkeArticle: 87085
"vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1121347163.078059.224600@f14g2000cwb.googlegroups.com... > Hello all, > Is there any way i can initialise values into the Xilinx FPGA FF. I > am working on the Virtex E FPGA. Please tell me how can i achive that > through verilog. > Thank you Aside from the asynchronous clear or preset, some synthesizers will accept register initialization such as: reg [7:0] count = 8'h1c; always @( posedge clk ) count <= count + 8'h1; Other synthesizers aren't as good and can apply the xilinx INIT=S or INIT=R attribute (but it applies to all registers in a vector). In Synplify, I've been pleading for the former but am using the latter, typically with macros to make things look cleaner. `define Init_Hi /* synthesis xc_props="INIT=S" */ reg [7:0] startFromNeg1 `Init_Hi; always @( posedge clk ) startFromNeg1 <= startFromNeg1 + 8'h1;Article: 87086
Are you just simulating right now? I'd expect synthesizers to only support modulus for powers of 2. I would expect the need for a full divider, running upwards of 100 ns depending on your value widths. "Paul Solomon" <psolomon@tpg.com.au> wrote in message news:42d61af1$1@dnews.tpgi.com.au... > Hi Guys, > > I have run into a problem that I was not expecting, I need to calculate the > remainder after division (modulo) of a number preferebly in combinational > logic or a single clock cycle, and I need it to behave in the same fashion > as matlab does (as you would expect). > > So i essentially need to calculate: > x = mod(y, 6434); > > I did this in verilog as follows > > reg signed [15:0] y; > wire signed [14:0] x; > > assign x = y % 6434; > > However this does not do what I am after. I assumed that % would perform a > modulo operation however, when my input is y = -6310, x = -6310. > This seems to be doing some kind of singed mod.. I would be expecting 124 as > the answer as matlab produced. > > Can you give me any clues as to where I am going wrong?? > > Regards, > > Paul SolomonArticle: 87087
Check to see if the pin you lifted still appears shorted. There are some flux/cleaning/non-cleaning configurations that promote the growth of dendrites between PCB traces. Often a little mechanical action in the area of the microscopic short will open the short. If the lifted pin appears to work again, I'd look carefully at this. It's not a signal near a battery on the board, is it? Those pesky voltages during assembly and cleaning are such a nuisance. "Bob Myers" <rjmyers@raytheon.com> wrote in message news:42D5A818.BCE97D07@raytheon.com... > I'm trying to find out what could cause a pin in a Virtex 300 > part to short out. It's happened more than once, within a > week's time frame. I can't really find any material on Xilinx's > support web site about this situation (and what to look for). > > Work-around for the first one was to lift the pin off of the > board and re-route the signal to another pin (used one adjacent > to the bad one). May end up doing the same thing for the second > pin now. > > Any suggestions welcomed... > > -bobArticle: 87088
Does anyone know where I can find a public domain / open source tool that will read a bunch of VHDL and/or Verilog files, and generate a block diagram from them? VGUI-2 (http://www.atl.external.lmco.com/projects/rassp2/vgui/) will generate VHDL from block diagrams; the reverse process was listed as a future enhancement, but the latest update seems to be two years old. Does anyone know if the Hierarchy Surfer script (at http://www.deepchip.com/downloadpage.html) has been updated (since 2000) and posted anywhere for the general public? Has anyone adapted an older version of Hierarchy Surfer to generate block diagrams? Thanks 2^32 for your help... mjArticle: 87089
To my understanding, bus macros are tri-state buffers at relative fixed positions according to XAPP290. I'd like to implement my own bus macros to be used for a small detacheable module (run-time reconfiguration), but I cannot find a way to instantiate the tristate primitives in CLBs in my VHDL. I could only get tristates by specifying this: output <= input when t = '1' else 'Z'; is there anyway to specifically instantiate a tristate primitive, preferably with location constraint?Article: 87090
jjohnson@cs.ucf.edu wrote:
> Does anyone know where I can find a public domain / open source tool
> that will read a bunch of VHDL and/or Verilog files, and generate a
> block diagram from them?
I don't think there is one.
Quartus/Mentor/Synplicity have an hdl viewer
that can do entity boxes and wires.
Modelsim has a data flow viewer that shows
processes and signals.
What would you do with this diagram
if you had it?
If the aim were to learn a design by others,
I would write a testbench and watch
it run on a simulator.
If the aim were to document the
design, I would do it as comments
in the source and testbench code.
-- Mike Treseler
Article: 87091"John_H" <johnhandwork@mail.com> wrote in message news:C0zBe.16$4K6.241@news-west.eli.net... > Are you just simulating right now? > I'd expect synthesizers to only support modulus for powers of 2. I would > expect the need for a full divider, running upwards of 100 ns depending on > your value widths. Hmm Interesting. I have simulated the verilog code in modelsim and it seems to work as expected. however I have also synthesized and fitted my whole design and loaded into a stratix and it does not work as expected. Do you think this could be the prob? I assumed that modelsim and quartus should behave the same way. I am running an 80MHz clock so 12.5ns reg - reg and there were no timing constratints broken on the timing analysis after compile Regards. Paul Solomon > > "Paul Solomon" <psolomon@tpg.com.au> wrote in message > news:42d61af1$1@dnews.tpgi.com.au... >> Hi Guys, >> >> I have run into a problem that I was not expecting, I need to calculate > the >> remainder after division (modulo) of a number preferebly in combinational >> logic or a single clock cycle, and I need it to behave in the same >> fashion >> as matlab does (as you would expect). >> >> So i essentially need to calculate: >> x = mod(y, 6434); >> >> I did this in verilog as follows >> >> reg signed [15:0] y; >> wire signed [14:0] x; >> >> assign x = y % 6434; >> >> However this does not do what I am after. I assumed that % would perform >> a >> modulo operation however, when my input is y = -6310, x = -6310. >> This seems to be doing some kind of singed mod.. I would be expecting 124 > as >> the answer as matlab produced. >> >> Can you give me any clues as to where I am going wrong?? >> >> Regards, >> >> Paul Solomon > >Article: 87092
Bob Myers wrote: >I'm trying to find out what could cause a pin in a Virtex 300 >part to short out. It's happened more than once, within a >week's time frame. I can't really find any material on Xilinx's >support web site about this situation (and what to look for). > >Work-around for the first one was to lift the pin off of the >board and re-route the signal to another pin (used one adjacent >to the bad one). May end up doing the same thing for the second >pin now. > >Any suggestions welcomed... > > What nobody else has said, and you may or may not be familiar with, is "ESD", electrostatic discharge. The lower voltage devices are more and more sensitive to voltages generated by friction on common substances like clothing and plastic. You can generate thousands of Volts just sliding into a chair. If the pin shows shorted before the FPGA has been configured, it is most likely physical damage to the part. If it only shows the short after configuration, then it is a result of the FPGA configuration loaded into the part, and not physical in nature. If these pins became shorted just after you touched the board, or touched it with a tool or scope probe, suspect ESD. You can use commercial anti-ESD products like wrist straps, workstation pads, etc. or just use common sense plus awareness of these ESD problems to ground your body and your tools to a known grounded object like the case of a power supply, soldering iron handle or whatever you know is grounded before touching the board. Don't slide into a chair and grab the board first. JonArticle: 87093
greenplanet wrote: > Seems like there is problem initializing the mouse. > The host pulls the clk down to start initializing; however, the mouse > clock doesn't start after the host releases the clk. Just a few quick questions - * What FPGA? It is 5V compatible? * Are you driving the line to 'Z' (tri-state), or to a '1'? The fact that the line is about 4V smells bad - could you have contention? JeremyArticle: 87094
Mike Treseler <mike_treseler@comcast.net> writes: > If the aim were to document the > design, I would do it as comments > in the source and testbench code. I document testcases as comments with a special prefix. These are then filtered out and processed with LaTeX, giving a nice PDF file. One could also embed diagrams in description languages like pstricks, metapost, dot, pic etc. and handle them in the same way. If somebody has already done this, I'd love to hear about it. To the original poster: take a look at emacs' vhdl-mode and its integration into speedbar for a hierarchy parser. Cheers, Colin -- If God had not given us sticky tape, it would have been necessary to invent it. [Pete Zakel]Article: 87095
If any one has idea about interfacing external RAM with Sparton-2e ,,,,,,,,Then Plz guide ............as i need it in my project for Sound and Vga Controllers..........i m using board of Digilent.....Pegasus..........Article: 87096
With 80 MHz you are absolutely not going to get a "complex" modulus to go exceedingly quick. Quartus will not produce a "real" modulus. This is probably documented in the tool for their language support. How many bits in your input? Is the modulus fixed at 6434? Which Altera device? Given those values, some folks should be able to give you an estimate of how long it would take to produce a result. Bottom line: 12.5 ns won't happen unless the "truncated integer part" is very few bits. "Paul Solomon" <psolomon@tpg.com.au> wrote in message news:42d6e874$1@dnews.tpgi.com.au... > > "John_H" <johnhandwork@mail.com> wrote in message > news:C0zBe.16$4K6.241@news-west.eli.net... > > Are you just simulating right now? > > I'd expect synthesizers to only support modulus for powers of 2. I would > > expect the need for a full divider, running upwards of 100 ns depending on > > your value widths. > > Hmm Interesting. I have simulated the verilog code in modelsim and it seems > to work as expected. > however I have also synthesized and fitted my whole design and loaded into a > stratix and it does not > work as expected. Do you think this could be the prob? > > I assumed that modelsim and quartus should behave the same way. > > I am running an 80MHz clock so 12.5ns reg - reg and there were no timing > constratints broken on the timing analysis after compile > > Regards. > > Paul SolomonArticle: 87097
Hi John, I have done some further ingestigation this morning, found out a few other things, albeit frustrating things. 1. You are right in that the modulo operation is not occuring in 12.5ns, this section of the design is in the order of 43ns. 2. The design that simulated perfectly in Modelsim, does not actually work. I have synthesised, fitted, and written a netlist out (to a vo file) and simulated this in modelsim and it does not work. At first I thought it was the clock going to fast, but I have slowed the clock right down (to 200ns) and it is still not making any sense. I have also tried the same simulation in Quartus and I appear to be getting garbage out. Do you know what I should be looking for, what kind of things could cause a discrepancy between the simulated verilog code and the simulated vo output? both the simulators and the synthesis tool is set for verilog-2001. btw to answer your other questions the bus width is 16bit and the mod is always 12868. Regards, Paul Solomon "John_H" <johnhandwork@mail.com> wrote in message news:5sEBe.18$4K6.255@news-west.eli.net... > With 80 MHz you are absolutely not going to get a "complex" modulus to go > exceedingly quick. Quartus will not produce a "real" modulus. This is > probably documented in the tool for their language support. > > How many bits in your input? Is the modulus fixed at 6434? Which Altera > device? Given those values, some folks should be able to give you an > estimate of how long it would take to produce a result. Bottom line: 12.5 > ns won't happen unless the "truncated integer part" is very few bits. > > > "Paul Solomon" <psolomon@tpg.com.au> wrote in message > news:42d6e874$1@dnews.tpgi.com.au... >> >> "John_H" <johnhandwork@mail.com> wrote in message >> news:C0zBe.16$4K6.241@news-west.eli.net... >> > Are you just simulating right now? >> > I'd expect synthesizers to only support modulus for powers of 2. I > would >> > expect the need for a full divider, running upwards of 100 ns depending > on >> > your value widths. >> >> Hmm Interesting. I have simulated the verilog code in modelsim and it > seems >> to work as expected. >> however I have also synthesized and fitted my whole design and loaded >> into > a >> stratix and it does not >> work as expected. Do you think this could be the prob? >> >> I assumed that modelsim and quartus should behave the same way. >> >> I am running an 80MHz clock so 12.5ns reg - reg and there were no timing >> constratints broken on the timing analysis after compile >> >> Regards. >> >> Paul Solomon > >Article: 87098
Hi, We will soon be using the Nios II as embedded controller and we would like to add a High Speed (HS) USB 2.0 hosting feature that is capable or providing a sustained transfer rate of 20 MBytes/sec. to an external HS USB 2.0 device. I realize that there are a limited number of HS USB 2.0 hosts devices/IP cores currently available. The Phillips ISP1761 is the only HS USB 2.0 component I was able to locate so far and it's not clear to me if this part is readily available. Also, the FPGA-based HS USB 2.0 host IP cores look like they are just now becoming available (www.asics.ws) but they may be cost-prohibitive. Can anyone share their experiences in implementing either a HS USB 2.0 or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 MBytes/sec. achievable with the assumptions that there are no major transfer bottlenecks in the HS USB 2.0 host component or the associated HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more reasonable transfer speed goal that has a high probability of success? The choice of which OS with Nios II (or no OS at all) may also be influenced by the max. sustained HS USB 2.0 transfer speed that can be achieved. However, it's also possible that in order to meet the 20 MBytes/sec. goal, the Nios II will have to be "removed" from the data I/O path so that custom FPGA circuitry can handle the transfers directly with the external HS USB 2.0 host transceiver or the IP core. Any information and/or opinions would be helpful. Sincerely, Brad.Article: 87099
Thanks for your reply, Jeremy! I was using Xilinx Spartan 2E 200 on Digilent D2Sb with DIO4 extension board. I'm driving the line to 'Z' not to '1'. However, after probing the PS/2 port (6 pin mini-DIN)on the board without attaching a mouse, I found that the data and clk stay at '0' always (according to the schematic from Digilent, there is no pull up circuit on both PS/2 data and clk lines). When I probe the corresponding fpga pins, they work as I programmed (logic 1 = 3.3V, logic 0 ~0V). Seems like the fpga couldn't take control of the port! I will try to use another board (XESS XSA3S1000 with Xstend V3.0) and see if this happens.
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