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Paul Solomon wrote: > Hi All, > > I am using Quartus and I have acess to Modelsim, and I have been working on > a project that is RF based containing lots of filters and other demodulation > elements. As I have been going along writing each filter etc, I have been > testing it by downloading the finished code to my board and then looking at > the output of a filter etc on a spectrum analyser and deciding > (subjectively) if it looks right or not. I dont feel this is the right way > to go however and I wanted some advise on how you would do test benching on > such a project. I have little experience here so I am sure that any advise > would be helpful. > > I have seen examples using all the testbench directives such as $DISPLAY > etc, but I dont think that Quartus likes these directives being in its final > code. Also I have writted simulation models for Matlab to confirm the > concepts before I write the verilog modules, so if there was someway of > comparing a Matlab module to a Verilog module then that would be fantastic. > > If anyone could give any advise then that would be most appreciated. Start here: http://janick.bergeron.com/wtb -aArticle: 87001
Hello! I have card which generate 16-bit ISA bus timing. I like to know if ISA bus in 16 bit generates address bus sequentially 0x0000, 0x0001, 0x0002... or it generates only even/odd addresses. Thank you and best Regards, AmirArticle: 87002
Ian wrote: > Hi Everyone, > > I would be really for any help or advice you can offer me on the > following. > > I have created a simple tri-state bus as a macro using xdl. The design > consists of two TBUFs driving a single long line. > > (Diagram at http://www.comms.scitech.susx.ac.uk/~ian/files/tbuf.gif) > > <img src="http://www.comms.scitech.susx.ac.uk/~ian/files/tbuf.gif"> > > I attach external macro pins to Out, Enable and In of each TBUF. > However, when I try to include the macro in a design, the DRC in the > map phase complains that the Out pin is being driven by two sources. > MAP Error Message: > > > ERROR:MapLib:22 - Bus M0_DATA_LEFT_O_OBUF driven by bm_instance and > bm_instance has multiple active drivers. > > > This is not correct, as the O pins are external macro outputs! Is there > anyway to prevent this? There's a fitter option somewhere that tells the tools to converter internal tristates to muxes. Find that option and tell it not to do so. -aArticle: 87003
Sean Durkin wrote: > Maybe you can force Quartus to generate a latch by adding an > "ELSE"-condition, like > > ... > ELSE > OUT0 <= OUT0; > END IF; > > Don't know if this will work with Quartus, but trying won't hurt. > > I think XST would infer a latch from your description, maybe Quartus > aims to avoid latches and uses a default instead... How would a default value differ from a latch? -aArticle: 87004
Marko wrote: > One difference is that parameters can be over-ridden by the calling > module via the defparam command. Not true with `define. Some tools let you override `defines from the command line. -aArticle: 87005
Mike Treseler wrote: > tns1 wrote: > >> Many of the nodes I want to probe seem unavailable in the simulation. >> They are either optimized away, or refuse to show up in the simulation >> window even when selected in the vwf. > > > For complex designs, it is common practice > to write HDL source and simulate *that* using > a vhdl simulator, before running Quartus. > > -- Mike Treseler Sounds like a good thing to do. Which tools provide this 'source level' simulation? Any free ones? thanksArticle: 87006
On Tue, 12 Jul 2005 09:56:37 -0700, amko wrote: > Hello! > > I have card which generate 16-bit ISA bus timing. I like to know if ISA > bus in 16 bit generates address bus sequentially 0x0000, 0x0001, > 0x0002... or it generates only even/odd addresses. > > Thank you and best Regards, > Amir Addresses are byte addresses so for a single 16 bit transaction you need to use a even (A0=0) address. unaligned I/O access should be possible (16 bit transfer from odd addresses) but why do 2 8 bit transfers... Peter WallaceArticle: 87007
Hello All, Please have a look at my observations below and let me know, if you agree with them or you would like to add your expert comments. I am using Synplify 8.1 for synthesizing my design(which uses multiple DCMs) for a Xilinx Virtex-4 device. WITHOUT CONSTRAINTS: the tool infers clk0 ,clk2x and clkfx clock outputs from the DCM, if you don't specify any constraints to the tool apart from the auto constraints(default 1 MHZ).As expected,it does not propagate the DCM input clock constraints and doesn't understand the 2x and fx(M/D values ). WITH CONSTRAINTS: when you specify constraints to the input clock(clkin) of the DCM then it happily stops inferring clk0 but it does infer clk2x and clkfx DCM outputs . The tool doesn't constrain the clkfx and clk2x output clocks according to the values set in the dcm but instead it just constrains it to the default (1 Mhz). WITH XC_PROPS : I went through the Synplify reference manuals ,where it was instructed to use xc_props to specify the clkfx_multiply,clkfx_divide etc attributes (In case, the propagation of the constraints don't work properly). Next ,I tried with these attributes attached to the DCM instances in SDC as well as the code.But it could not drive synplify to do the automatic clkfx and clk2x constraint calculation. FORCED: At last , I had to find the clkfx and clk2x net names from the log file (.srr) and apply the constraints to them. Thankfully , this worked!!! :) Please, tell me if this issue is something which has been an accepted fact with Synplify synthesis or is there some other way out of this ? Thanks, AjayArticle: 87008
> > You have few options. > > 1. If you just need to update and build the old project for > the original parts (that were supported in version 3.1) the > best bet is to continue to use 3.1 - I am using 4.1 (the last > of the Aldec-based versions) on the same machine with 6.1 > and all I need to do is change my Xilinx environment variable > to switch between modes. > Thank's for your repaly The problem is that the PC with 3.1 crash and i can't find installation CD :-( I've only me project files and the version 6.1 Could you help me? Thank's Max udicomArticle: 87009
Hello All, Please have a look at my observations below and let me know,whether you agree with them.Or, if you would like to add your expert comments based on your experiences,please do. I am using Synplify 8.1 for synthesizing my design(which uses multiple DCMs) for a Xilinx Virtex-4 device. WITHOUT CONSTRAINTS: the tool infers clk0 ,clk2x and clkfx clock outputs from the DCM, if you don't specify any constraints to the tool apart from the auto constraints(default 1 MHZ).As expected,it does not propagate the DCM input clock constraints and doesn't understand the 2x and fx(M/D values ). WITH CONSTRAINTS: when you specify constraints to the input clock(clkin) of the DCM then it happily stops inferring clk0 but it does infer clk2x and clkfx DCM outputs . The tool doesn't constrain the clkfx and clk2x output clocks according to the values set in the dcm but instead it just constrains it to the default (1 Mhz). WITH XC_PROPS : I went through the Synplify reference manuals ,where it was instructed to use xc_props to specify the clkfx_multiply,clkfx_divide etc attributes (In case, the propagation of the constraints don't work properly). Next ,I tried with these attributes attached to the DCM instances in SDC as well as the code.But it could not drive synplify to do the automatic clkfx and clk2x constraint calculation. FORCED: At last , I had to find the clkfx and clk2x net names from the log file (.srr) and apply the constraints to them. Thankfully , this worked!!! :) Please, tell me if this issue is something which has been an accepted fact with Synplify synthesis or is there some other way out of this ? Thanks, AjayArticle: 87010
Max, It seems your best bet is to try the Aldec approach. They can get you started with an evaluation license (I think it's good for 1 month) and they have some app notes on migrating your old designs from Xilinx Foundation. If you don't keep the tools after the eval, you'll still have had a chance to look at and print your old schematics and possibly convert them into something usable by the 6.1 tools. If nothing else the Aldec tools should still have the VHDL export option. Good luck, Gabor Max wrote: [Snip] > > The problem is that the PC with 3.1 crash and i can't find installation CD > :-( > I've only me project files and the version 6.1 > > Could you help me? > > Thank's > > Max > > udicomArticle: 87011
The approach I've taken is to add pins to get the desired signals to appear as module ports. This works great if I'm simulating sub sets of the final design. And in the total design these pins will eventually get optomized away. If you get to the top level and need to see pins then you need to get then to output pins on the device. If you're out of pins I put them into a mux and this will keep the signals available for viewing. This all works great for functional simulatins. Good Luck. georgeArticle: 87012
Hello, I was curious if anyone can comment on writing safe state machines in AHDL. I often use One-hot encoding in my state machines and am curious how safe it is. I set the State Machine setting in Quartus for One-hot Encoding, does this force all my state machines to be safe. If I just add the line to my state machine: When Others => StateMachine = StateA; -- go back to start will the state machine be considered safe? thanks, joeArticle: 87013
Program Announced --- Registration Open
2005 MAPLD International Conference
Ronald Reagan Building and International Trade Center
Washington, D.C.
September 7-9, 2005
The 8th annual Military and Aerospace Programmable Logic Device
(MAPLD) International Conference will present papers on programmable
logic devices and technologies, digital engineering, and related
fields, for military and aerospace applications. Devices,
technologies, logic design, verification, flight applications, fault
tolerance, reliability, radiation susceptibility, and encryption
applications of programmable devices, processors, and adaptive
computing systems in military and aerospace systems are topics for
papers.
For 2005, MAPLD will be expanded to 3 full days and will feature
expanded "Birds of a Feather" Workshop Sessions. 165 oral and poster
presentations are currently on the program. Four full-day seminars
will be offered on September 6, 2005.
KEY DATES AND LINKS
Early Registration Ends: August 8, 2005
Registration: http://klabs.org/mapld05/reg
Conference Home Page: http://klabs.org/mapld05
Late Submissions: Late papers will be accepted for the
Poster and "Birds of a Feather" Workshop
sessions only, on a space-avaiable basis.
http://klabs.org/mapld05/
We are planning an exciting program with presentations by Government,
industry, academia, and consultants, including talks by distinguished
Invited Speakers. This conference is open to US and foreign
participation and is unclassified. For related information, please
see the NASA Office of Logic Design Web Site (http://klabs.org).
Special Talks Include:
* Welcome and Opening Address
Ralph Roe, NASA Engineering and Safety Center
* Invited History Talk, "The Hubble Space Telescope"
Steven Beckwith, Director, Space Telescope Science Institute
* Invited Mishap Talk (new for 2005)
"Computer Overload and The Apollo 11 Lunar Landing"
Jack Garman (formerly NASA MSC/JSC)
* Panel Session: "Why Are Space Stations So Hard?"
Roger Launius, National Air and Space Museum
Keith Cowing, Editor, NASA Watch
William Dwyer, Engineer, Space Station Freedom and ISS
and more ....
Four Seminars for 2005:
* Design Integrity
* Device Failure Modes and Reliability
* Reconfigurable High-Performance Computing
* Space Plug-and-play Avionics (SPA) Technical Committee/Workshop
Planned Technical Sessions, Oral, Poster and Birds-of-a-Feather (BOF):
* Applications: Military & Aerospace I and II
* Verification of High Reliability Designs
* Radiation Effects and Mitigation Techniques
* Logic Design and Processors
* Reconfigurable Computing, Evolvable Hardware, and Security
* Poster Session
* BOF-L: Mitigation Methods for Reprogrammable Logic in the Space
Radiation Environment
* BOF-H: Reconfigurable Computing
* BOF-J: PLD Failures, Analyses, and the Impact on Systems
* BOF-S: NESC and Software
* BOF-G: Digital Engineering and Computer Design - A Retrospective
and Lessons Learned for Today's Engineers
* BOF-W: Verification of Large Designs and Related
Design Methodologies
Reservations are being accepts for the Industrial & Gov't Exhibits:
http://klabs.org/mapld05/exhibits/reservation_request_form.htm
Industrial and Government participants include:
NASA Office of Logic Design Synthworks
Space Micro SRC Computers
BAE Systems: Information and Aldec
Electronic Warfare Systems
Actel Corporation ATK Mission Research Corporation
Aeroflex Colorado Springs Xilinx, Inc.
Sigrity Mentor Graphics Corporation
IEEE Aerospace and Electronics NASA Engineering and Safety Center
Systems Society
Nallatech Celoxica
Northrop Grumman Corporation SEAKR Engineering
Synplicity Aitech Defense Systems
LSI Logic Andraka Consulting Group
Pentek NRO: Director's Innovation Initiative
Southwest Research Institute Star Bridge Systems
Cray Alpha Data
EM Photonics NASA MSFC Traveling Exhibits Program
VMETRO MathStar
For additional information:
Conference home page: http://klabs.org/mapld05
Richard B. Katz
NASA Office of Logic Design
mapld2005@klabs.org
Article: 87014Hi all, I am trying to find the edif version used by Xilinx ISE 6.2.03i generated by XST. Also I was wondering if somebody knows where I could find the edif format online. Thanx, Hassan.Article: 87015
"Max" <mdazzan__NOSPAM___@libero.it> wrote in message news:w5VAe.13232$tX6.286211@twister1.libero.it... > > > > > Thank's for your repaly > > The problem is that the PC with 3.1 crash and i can't find installation > CD :-( > I've only me project files and the version 6.1 > > Could you help me? > > Thank's > > Max What about the old archived versions of webpack ? 3.3 and 4.1 are available under http://www.xilinx.com/webpack/classics/wpclassic/index.htmArticle: 87016
GMM50 wrote: > The approach I've taken is to add pins to get the desired signals to > appear as module ports. This works great if I'm simulating sub sets of > the final design. And in the total design these pins will eventually > get optomized away. > > If you get to the top level and need to see pins then you need to get > then to output pins on the device. If you're out of pins I put them > into a mux and this will keep the signals available for viewing. > > This all works great for functional simulatins. > > Good Luck. > george > OK, but what about when the signal looks OK in the sim, but it does not appear on the chip?Article: 87017
This paper shows a nice application where their tool was used: http://fpgajournal.com/articles_2005/20050607_impulse.htm Daniel LeuArticle: 87018
See http://www.altera.com/support/kdb/2003/05/rd05142003_7103.html It describes how to use the "keep" attribute to preserve a combinational node, and the "preserve" attribute to preserve a register. If you set the appropriate attribute on a node, it will prevent the optimization algorithms from removing it, even if that would result in a more efficient circuit. Hence you can select and view it in a simulator after compilation (either functional or timing simulation). As some other posters have pointed out, you can also bring the signal out to a pin, which is an indirect way of forcing it to be preserved -- this is often less convenient in a large design, however. See the Quartus online help for examples of the precise syntax to use to set these attributes. Regards, Vaughn Altera [v b e t z (at) altera.com] "tns1" <tns1@cox.net> wrote in message news:wWEAe.8412$Eo.7045@fed1read04... > Many of the nodes I want to probe seem unavailable in the simulation. They > are either optimized away, or refuse to show up in the simulation window > even when selected in the vwf. > > Is there a way to prevent this from happening such as a setting an > optimization level or marking registers so they will be available? > > thanks >Article: 87019
Cyclone II is faster than Cyclone I, so if this is hitting 270 MHz in Cyclone I, there's a pretty good chance it'll run at 300 MHz in Cyclone II. But of course, the speed-up from Cyclone I to Cyclone II is circuit dependent, so I can't say that for sure for this particular circuit you'll get the speed boost you need -- you'll need to try and see. Regards, Vaughn Altera [v b e t z (at) altera.com] "Ben Twijnstra" <btwijnstra@gmail.com> wrote in message news:23646$42d3afe1$d55db008$5023@news.chello.nl... > Hi praveen, > >> Hi all, >> >> I want to implement a clock extraction circuit from data at 300 Mbps. >> What i wanted to know is that is it really feasible in FPGA's( CYCLONE >> II). >> >> Is any reference design available on clock extraction circiuit. > > Altera has two reference designs for Cyclone I that do clock/data recovery > at 270MHz for DVB/ASI and SDI. It may be possible to crank this up to > 300MHz when using the fastest speed grade Cyclone but it's going to be > tricky. > > Best regards, > > > Ben >Article: 87020
It's hard to be definitive without seeing your actual timing constraints, but it sounds like your original constraints set an 80 MHz timing constraint on the clock for the two higher speed FIR filters, and left the rest of the clocks unconstrained. It also sounds like those other clocks were reduced in speed through logic on the 80 MHz clock, which would result in a slower, but highly skewed, clock relative to the 80 MHz clock. With no timing constraint on the slower clocks, Quartus will trace through the logic generating those clocks, see that it is fed by an 80 MHz clock, figure out the skew, and assume you want synchronous transfers from the 80 MHz clock to the slow clocks, if any data paths exist between these domains. The clock skew between the 80 MHz and slower clocks would be causing your hold violations. Quartus can automatically repair them by adding data delay if you ask it to, but that option is off by default to encourage designers to check their timing constraints and clock generation scheme first, just like this case. By running everything at 80 MHz, you get rid of this clock skew, and make a cleaner design with much simpler hold time conditions. Hope this helps, Vaughn Altera [v b e t z (at) altera.com] "Paul Solomon" <psolomon@tpg.com.au> wrote in message news:42d1bcfc@dnews.tpgi.com.au... > "Mike Treseler" <mike_treseler@comcast.net> wrote in message > news:B9KdndA-gtbXpUzfRVn-iw@comcast.com... >> Paul Solomon wrote: >> >>> I am using a straix part and it is clocked at 80MHz, and I have a number >>> of FIR filters in the design. There are currently 2 FIR filters that >>> need to run at 80MSPS and then a seriec of filters that these feed into >>> after decimation, so these other filters run a lower clock rates. >> >> Consider running everything at 80MHz and use >> clock enable inputs where needed for lower >> effective rates. >> >> -- Mike Treseler > > Hi Mike, > > This seems to have solved my problems, I dont claim to understand how but > it does seem to work. > > Can you explain why this fixes the problem? As I thought forcing all the > filters to be clocked at 80MHz > would add additional constraints that would lessen the chance of a correct > fit. > > Regards, > > Paul >Article: 87021
This is useful, but not what I need right now. I am now faced with the problem of having a good timing sim, but a non-functioning design. Essential signals that appear OK in the sub-project sim are being removed somehow when I compile the whole project. What would cause the sim results to be incorrect? I have a verilog top module which contains both verilog and vhdl modules. Is there some strange rule about connecting ports when mixing language modules? I am only having problems with the vhdl outputs. Vaughn Betz wrote: > See http://www.altera.com/support/kdb/2003/05/rd05142003_7103.html > > It describes how to use the "keep" attribute to preserve a combinational > node, and the "preserve" attribute to preserve a register. If you set the > appropriate attribute on a node, it will prevent the optimization algorithms > from removing it, even if that would result in a more efficient circuit. > Hence you can select and view it in a simulator after compilation (either > functional or timing simulation). As some other posters have pointed out, > you can also bring the signal out to a pin, which is an indirect way of > forcing it to be preserved -- this is often less convenient in a large > design, however. > > See the Quartus online help for examples of the precise syntax to use to set > these attributes. > > Regards, > > Vaughn > Altera > [v b e t z (at) altera.com] > > "tns1" <tns1@cox.net> wrote in message news:wWEAe.8412$Eo.7045@fed1read04... > >>Many of the nodes I want to probe seem unavailable in the simulation. They >>are either optimized away, or refuse to show up in the simulation window >>even when selected in the vwf. >> >>Is there a way to prevent this from happening such as a setting an >>optimization level or marking registers so they will be available? >> >>thanks >> > > >Article: 87022
Huomenta (o; Looks like Altera listened to me and released the NIOS2 toolchain sources on their ftp server finally (o; Details for login here, although not up2date: http://www.altera.com/support/kdb/2000/11/rd11272000_7307.html rickArticle: 87023
"Jedi" <me@aol.com> schrieb im Newsbeitrag news:VC3Be.40$k51.11@read3.inet.fi... > Huomenta (o; > > Looks like Altera listened to me and released the NIOS2 > toolchain sources on their ftp server finally (o; > > Details for login here, although not up2date: > > http://www.altera.com/support/kdb/2000/11/rd11272000_7307.html > > > rick Huomenta you are greeting in finnish? jedi aka Richard? Are you from Finnland or? Name doesnt sound like finnish (mine does). Altera HAD TODO this. Thats the way it is with open source licenses, you must agree to them or withdraw all your products that are using them, what Altera of course can not do, so they are forced to keep the nios tool sources available as that is the requirement of the licenses they are bound too. Antti soovib head päeva köigile (not in Finnish, but in Estonian)Article: 87024
"amko" <sinebrate@yahoo.com> wrote in message news:1121187397.110218.141370@z14g2000cwz.googlegroups.com... > Hello! > > I have card which generate 16-bit ISA bus timing. I like to know if ISA > bus in 16 bit generates address bus sequentially 0x0000, 0x0001, > 0x0002... or it generates only even/odd addresses. > > Thank you and best Regards, > Amir It's been long long time since my last ISA design. From what I rememebr, 16 bit transfers on ISA bus are always word aligned: i.e. A0 is always 0. This goes for both memory and I/O. If you can find IBM's "AT technical reference", you can see the original schematics of the ISA bus interface. As I remember, the logic there made it impossible to have a 16 bits I/O on the odd addresses... (I'm telling you all these things off my head. As I said before, it's been a long long time since my last ISA design).
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