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I have read the following in one post discussing latches: "None of the above applies to FPGA, you will have no control over anything and your timing will be horrible so forget it. " Comments ?Article: 87251
I'm new to FPGA synthesis and XST, so I could use some help. I'm synthesizing an entity for the first time, and I'm receiving warnings and errors related to the time type in my models. I realize that they are not synthesizable. I'm okay with the warnings because I have them in there for functional simulation only. Here is the output from XST in Foundation 7.1: <SNIP> WARNING:Xst:828 - "/../../../../work/toplevel.vhd" line 28: Constant <TPDREG> of type Time is ignored. WARNING:Xst:1537 - "/../../../../work/toplevel.vhd" line 93: Generic <tpdreg> of type Time is ignored. Analyzing generic Entity <component_g> (Architecture <structural_ar>). ERROR:Xst:834 - "/../../../../work/component_g.vhd" line 58: Generic <tpdreg> has not been given a value. --> </SNIP> It seems to me like XST is ignoring the time types and then later complaining about a generic of type time in the component instantiation, the value of which, is propogated from a higher level. Any thoughts?Article: 87252
ALuPin@web.de wrote:
> ... NO time because the external module is expecting response on the
> next clock cycle.
That's one external clock cycle, not zero.
Use a fpga clock at least twice that fast.
Send a handshake while you synchronize the data strobe.
> I have read several posts in this newsgroup
> explaining that the state machine would have to be very tricky
> to handle unregistered inputs.
Any synchronous design will have problems with asynchronous
inputs. Note that registered inputs may or may not
be synchronous to the fpga clock.
-- Mike Treseler
Article: 87253
ALuPin@web.de wrote:
> Some additional info:
>
> The clock of the FSM is provided by the external module.
>
In that case, you can just turn around the data strobe
as a handshake and latch the data on the same
clock tick.
-- Mike Treseler
Article: 87254I think we need a better statement of the problem. You have an 8-bit wide incoming data bus. Is there a clock that defines valid data? What is the timing of that clock or clock edge? If there is no clock, how do you know that there is new data? What if the new data is identical with the old data? Peter AlfkeArticle: 87255
ALuPin@web.de wrote:
> I have read the following in one post discussing latches:
> "None of the above applies to FPGA, you will have no control over
> anything and your timing will be horrible so forget it. "
In a synchronous design, even one with 30,000
flops, I need only one synthesis constraint, Fmax.
Synthesis is a formality.
In an asynchronous design I need to constrain
setup and hold times to every flop.
Synthesis is tedious at best.
-- Mike Treseler
Article: 87256Vaughn This is exactly my point. In your first paragraph you switch between the two issues here as if they are the same, which is the point of this discussion (do they teach you that at Altera). We are talking two different issues here, speed and hardware architecture. Yes, speed is complex to measure, which is why you say you are faster than Xilinx and Xilinx says they are faster than you, because of the subjectivity of the sample universe. But your entire point of this "marketing" campaign is not the speed but the hardware. An LUT is an LUT, no matter how you slice it (granted, the additional logic to enhance the LUT performance does increase the complexity, affecting speed, not LUTs). And your response of the "larger" LUT for Altera is the last point of my e-mail. Would you quit "marketing" your variable input LUT (Xilinx has had a variable input LUT feature since 1998, in fact you are a little late with this feature). If you even look at your own white paper comparing the schematics between the two; you have two individual 4-input "ALUT"s feeding into "combinational logic" that provides the flexibility for the number of inputs, so the foundation is still 2 4-input LUTs. Interestingly, Altera will not disclose how they combine the 2 4-input LUTs to provide the flexibility. Vaughn, again, you are dealing with engineers, not impressionable consumers. TimArticle: 87257
Paul You will also see this same "logic" (sorry for the pun) in my response to Vaughn. One things is certain in analyzing the Altera vs Xilinx debate, and that is that both companies claim to have the performance advantage, which is speed. Obviously the outcome is subjective. My complaint here is the hardware analysis, where you blatantly use your higher number and compare it with the Xilinx lower number, which is an abuse of logic. Let me give you the basis for this debate: http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm I would welcome your response to the hardware comparison. See my comments to Vaughn on the LUT discussion. TimArticle: 87258
Andre, There are a few alternatives. I am doing something similar in my design right now, but it depends on the speed of your clock/data rate and whether it's smooth or gapped. (*) You can generate a higher clock and do everything with it - nice, clean and quiet. In this case, use OFFSET constraint for external clock. You can apply either internal or EXTERNAL setup/hold settings for the OFFSET constraint (external means the specs of the external device, but make them a little harder than the spec). (**) You can try some very nice asynchronous switching by latches, but......................................... I am not a big fan of it. (***) NO time at all, try PAD to PAD delay, which you can contraint for the cases you have a PAD ==> combinational_logic ==> PAD. If you could give a few more details... Hope this helps. Vladislav P.S. . <ALuPin@web.de> wrote in message news:1121846253.756193.223170@g44g2000cwa.googlegroups.com... Hi, I have some doubts concerning the following problems: In my design I have an 8bit bidiretional bus "Data_ulpi". When the external module drives data into my FPGA I have to read that data and respond immediately that is I have NO time to synchronize the data with 2-stage-FFs/FIFO. ... NO time because the external module is expecting response on the next clock cycle. I have read several posts in this newsgroup explaining that the state machine would have to be very tricky to handle unregistered inputs. So how do I have to place bidirectional bus and control signals to have at least a chance of doing a good job ? What constraints do I have to take into consideration in that special case for tSU/tH ? Thank you for your advice. Rgds AndréArticle: 87259
Hi, I am currently working with the 1727 bit wide shift register....For my design requirements, I had to change it to a 3454 bit wide shift register( 2*1727)... When I did this and implemented the design, I have an error in the Mapping that: The design is too large for the device and package (I am using xc3s400 and tq144- spartan3) So instead I am working on two shift registers, each 1727 bit wide.... and giving the output of one shift reg as input to the other... This would still use the same number of resources ..so I am getting the same Mapping error....I tried contacting Xilinx support.....waiting for some help.. Is there another method to work around this..to minimize the design... Or I was wondering if I should change the fpga I am using...that would mean a whole lot of other changes on the board.... But yes that would be last resort type of thing.... Any suggestions or ideas Thanks, MethiArticle: 87260
try this link: http://www.xilinx.com/products/software/chipscope/chipscope_ila_tut.pdf it helped me a lot cheersArticle: 87261
"methi" <gmethi@gmail.com> wrote in message news:1121877741.981616.68610@g14g2000cwa.googlegroups.com... > > Hi, > > I am currently working with the 1727 bit wide shift register....For my > design requirements, I had to change it to a 3454 bit wide shift > register( 2*1727)... <snip> Is your design giving you registers for your shift elements? The SRL16 primitives can cut that utilization by a significant amount. You can also use BlockRAM to perform a shift register function. There are many solutions at your disposal but no true idea of what your overall constraits are. Is the shift register the only thing in the design? Are you using a reset for those shift elements? Is it serial-in, serial-out? Are there frequency constraints? Is the shift register fixed in length or variable?Article: 87262
If I were to do it in Verilog, I might use always @(posedge Clk27M) TotalOnes <= in[0]+in[1]+in[2]+in[3]+in[4]+in[5]+in[6]+... and continue typing until I reach +in[63]; The synthesizer MAY produce superb results. If it grinds, split it into groups - 8 groups of 8 or 4 groups of 16 nad add *those* values together as a multiple-value addition. "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:11dr26q40k9876e@corp.supernews.com... > Yeah, I understand this. But I can't wrap my head around how to code it. > > Do you do like this: > if( clk'event and clk='1') then > partial_sum1_2bit <= '0'&bit0 + '0'&bit1; > partial_sum2_2bit <= '0'&bit0 + '0'&bit1; > partial_sum1_3bit <= '0'&partial_sum1_2bit + '0'&partial_sum2_2bit; > -- and so on > end if; > > And then there is the question on how this all synthesizes, probably, for me > at 27MHz, opimized for area not speed. I could use a little insight from > someone who's done this before. > > Brad Smallridge > b r a d @ a i v i s i o n . c o mArticle: 87263
> Is the shift register the only thing in the design?
Nopes I have my design doing a whole lot of things...but its only when
I changed the length of the shift register that I came across the
Mapping error.
> Are you using a reset for those shift elements?
I am not using any reset...It takes in a clock...and shifts a bit for
every rising edge of the clock...
> Is it serial-in, serial-out?
Yes its serial_in and serial_out
> Are there frequency constraints?
No.
> Is the shift register fixed in length or variable?
Its a variable shift register....the length is determined by an input
variable called "right".
The code is as follows:
entity shifting_two is
Port ( shiftin : in std_logic;
clock_in : in std_logic;
right : in integer;
shiftout : out std_logic);
end shifting_two;
architecture Behavioral of shifting_two is
signal shift_register : std_logic_vector ( 3454 downto 0 ):= (others =>
'0');
begin
process(clock_in)
begin
if rising_edge(clock_in) then
shift_register <= shift_register( 3453 downto 0 ) & shiftin;
shiftout <= shift_register(right-1);
end if;
end process;
end Behavioral;
How can I use a BlockRam...?
My Design Summary as showin in the Map report is as follows:
Design Information
------------------
Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p
xc3s400-tq144-4 -cm
area -pr b -k 4 -c 100 -tx off -o top_1190_mem_map.ncd top_1190_mem.ngd
top_1190_mem.pcf
Target Device : x3s400
Target Package : tq144
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.16.8.2 $
Mapped Date : Wed Jul 20 11:37:18 2005
Design Summary
--------------
Number of errors: 1
Number of warnings: 38
Logic Utilization:
Number of Slice Flip Flops: 5,126 out of 7,168 71%
Number of 4 input LUTs: 4,150 out of 7,168 57%
Logic Distribution:
Number of occupied Slices: 4,175 out of
3,584 116%
(OVERMAPPED)
Number of Slices containing only related logic: 3,305 out of
4,175 79%
Number of Slices containing unrelated logic: 870 out of
4,175 20%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number 4 input LUTs: 4,274 out of 7,168 59%
Number used as logic: 4,150
Number used as a route-thru: 124
Number of bonded IOBs: 73 out of 97 75%
IOB Flip Flops: 31
Number of Block RAMs: 10 out of 16 62%
Number of GCLKs: 8 out of 8 100%
Number of DCMs: 2 out of 4 50%
Number of RPM macros: 1
Total equivalent gate count for design: 738,951
Additional JTAG gate count for IOBs: 3,504
Peak Memory Usage: 120 MB
Thankyou,
Methi
Article: 87264Brad, There are so many ways of doing this, depending on your FPGA family, required timing and the available resouces, but other than using the "natural resources", simple LUTs, pipelines, even multipliers, etc., you can also use memories. Personally, I like using memories for state machines, especially for channelized state machines or LUT for pre-computed CRC calculation. If we are talking about Virtex family, we have 16384 bits RAMs, which can be used as 4096x4 LUT, where you have a '1's counter within 12-bit vector, which is applied as an address of the entry. Each entry holds the number of '1's. It is clear how to expand this concept further to any vector, depending on the timing requirements and the available resources. One way is that you can try 5 memory blocks like this and it will give you 60 bits covered, then simply add the "data_out"s and the extra bits and pipeline them. There could be more "balanced" or optimal usage of memories and FFs. I hope i did not make any math mistake here. Vladislav "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:11dr115qoteg87b@corp.supernews.com... > Hello Group, > > What is the best way to count 64 incoming simultaneous > bit signals to determine the number of 1s (in VHDL)? > I have clock cycles to spare but the result must be pipelined > so that each clock cycle produces a new count. > > Brad Smallridge > b r a d @ a i v i s i o n . c o m > > >Article: 87265
Methi, You can use a circular buffer implemented by BRAM. What are you doing with this shift register afterwards? Vladislav "methi" <gmethi@gmail.com> wrote in message news:1121877741.981616.68610@g14g2000cwa.googlegroups.com... > > Hi, > > I am currently working with the 1727 bit wide shift register....For my > design requirements, I had to change it to a 3454 bit wide shift > register( 2*1727)... > > When I did this and implemented the design, I have an error in the > Mapping that: > The design is too large for the device and package (I am using xc3s400 > and tq144- spartan3) > > > So instead I am working on two shift registers, each 1727 bit wide.... > > and giving the output of one shift reg as input to the other... > > This would still use the same number of resources ..so I am getting the > same Mapping error....I tried contacting Xilinx support.....waiting for > some help.. > > Is there another method to work around this..to minimize the design... > > Or I was wondering if I should change the fpga I am using...that would > mean a whole lot of other changes on the board.... > > But yes that would be last resort type of thing.... > > > Any suggestions or ideas > > Thanks, > Methi >Article: 87266
Methi, when you say "wide", I believe you mean "long" or "deep". With SRL16s you can cut the size by a factor 16, but you do not have parallel access to all the bits in your shift register. Even more compact is a BlockRAM, where you can pack >16000 bits into one BlockRAM. So it all depends on how you use your shift register, and how you have o control it... Peter AlfkeArticle: 87267
I using the Xilinx tool flow. After synthesis with XST, the synthesis report looks fine, it contains all the Flip flops, adders etc. The next step of translation also goes well without errors or warnings. However, during the map phase all my design is removed as redundant logic. Any Ideas as to what I am doing wrong??Article: 87268
Hello, I want to connect a DIMM SDRam to a Cyclone FPGA, but I don't really feel confortable about the way of doing it. When it's only a module, I know I have to put some small resistances in the path. However, there are already resistances on a DIMM. So should I put resistance between the dimm and the I/O of the FPGA ? Since the input capacitance of a DIMM is significantly larger than the ones of sdram module, shall I make them smaller ? I looked on various litterature, and these solutions arised : keep a resistance of the same level, or put a smaller resistance. Which one is the best ? Regards NickArticle: 87269
Azam, This is what i can think of: (*) You are not using manual instantiation of I/O buffers, and Add I/O buffers option is turned off, in which this case, you should get many warnings during MAP, somehting like " Attribute LOC is on the wrong type of object "... But you said no warnings or errors, so.... (**) The design can have logic which does not go outside or simply unconnected. If this is a major signal, like clock, then eventually everything is being optimizes away. Can you paste the MAP report? Vladislav "azam" <azamirfan@gmail.com> wrote in message news:1121882031.010455.152800@g14g2000cwa.googlegroups.com... >I using the Xilixn tool flow. After synthesis with XST, the synthesis > report looks fine, it contains all the Flip flops, adders etc. The next > step of translation also goes well without errors or warnings. However, > durinng the mapping phase all my design is removed as redundant logic. > Any Ideas as to what I am doing wrong?? >Article: 87270
All the details are in the specification: www.jedec.org/download/search/jesd71.pdf Regards, DanielArticle: 87271
I would like to switch to Verilog, but not on this project. > If I were to do it in Verilog, I might use > always @(posedge Clk27M) > TotalOnes <= in[0]+in[1]+in[2]+in[3]+in[4]+in[5]+in[6]+... and continue > typing until I reach +in[63]; >Article: 87272
Thankyou Peter Its a 3454 bit shift register.....By saying "wide" ,I am talking about the depth... What I am trying to do is...depending on the value of the variable "right"...for eg: if right=2300, then the output would be the 2200th bit of the shift register. This would be mean that I need access to all the bits in the shift register... > With SRL16s you can cut the size by a factor 16, but you do not have > parallel access to all the bits in your shift register. Does this mean that I would get access only to the MSB and not the individual bits like how it does in my code at present? > Even more compact is a BlockRAM, where you can pack >16000 bits into > one BlockRAM. How do I use this BlockRAM....to work as shift register...Article: 87273
> Methi, > > You can use a circular buffer implemented by BRAM. > > What are you doing with this shift register afterwards? > > Vladislav > I am just using the output of my shift register...which is the MSB (this keeps changing depending on the value of the variable "right")...as input to another component....its a pulse...Article: 87274
I've come across this core in Xilinx which is a RAM-based shift register....It takes in clock:rising edge clock signal, serial input, address input(for variable length) and gives out a serial out... Would using this core instead of the code I have save any resources... Am wondering if anybody has worked with this before.. Otherwise the options I have so far is to go for: 1) BlockRAM 2) Cicular buffer with RAM 3)SLR16 Thanks, Methi
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Compare FPGA features and resources
Threads starting:
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