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Rick Thompson wrote: > On Mon, 17 Jan 2005 11:46:53 -0500, Chuck Harris > <cf-NO-SPAM-harris@erols.com> wrote: > > >>I want to go to Debian, but I am finding it hard to get excited about >>ripping my system apart and starting over...If only there was a safe >>and easy way to move from RedHat to Debian... > > > The EDA vendors only support RedHat, so I'm sticking with it, whatever > its faults. And, finally, after all these years, we now actually have > a professional Linux distribution, that's not just put together by > hackers. But I'll tell you what really pi**es me off about it - they > now charge an *annual* subscription for it. I've been buying Windoze > distributions for 20-odd years, and I've never once had to pay an > annual subscription. I bought my current Win2K 4 years ago, and I can > still download updates and security fixes for free. What exactly makes > RedHat think that they can charge year-on-year for that? If they'd > just asked me for a one-off $200 then I'd have paid it. I'm running > FC2 now, despite having to download the whole thing. > > Rick There is no reason that you have to pay RedHat. The amount you pay is purely for their support. You can get the entire distribution from a number of places. One is www.tux.com -ChuckArticle: 77851
Looks like this is a known problem and will be fixed in a later version.
Here's a workaround I received from Xilinx support:
For now if you want to do this you will need to run netgen in
command line and delete the "-s-4" option.
To do this:
1. In Project Navigator click on your top level
2. Run Generate Post-Place & Route Simulation Model ( you will still
get the same warning)
3. Under Design Entry Utilities click on View Command Line Log File
4. The last command line should read something like
1. netgen -intstyle ise -s 4 -pcf top.pcf -ngm top.ngm -w
-ofmt verilog -sim top.ncd top_timesim.v
5. Now open a command line
6. Change to your project directory
7. Paste the netgen command in the command line minus the -s 4
option. Something similar to this.
1. netgen -intstyle ise -pcf top.pcf -ngm top.ngm -w -ofmt
verilog -sim top.ncd top_timesim.v
8. You can now run Model Sim with this file
"Gabor" <gabor@alacron.com> wrote in message
news:1105136942.967063.31130@c13g2000cwb.googlegroups.com...
> gja wrote:
> > Tried that, but i get this warning message:
> >
> > Started process "Generate Post-Place & Route Simulation Model".
> >
> > WARNING:Anno:255 - command line '-s -4' overrides .pcf TEMPERATURE =
> 70.000
> > C
> >
> This message is when you build the model? It looks like NGDanno is
> being invoked with -s -4 (change speed to 4) in the command line. If
> you run NGDanno from the process window in the ISE navigator I don't
> think you can turn this off. Maybe someone knows how to run this
> from a command line. Check out the Development System Reference Guide
> chapter 24 "NGDanno" in the online documentation.
> >
> >
> >
> > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
> > news:345bivF47eeulU3@individual.net...
> > >
> > > "gja" <geeja@hotmail.com> schrieb im Newsbeitrag
> > > news:SQdDd.3214$yK7.3065@fe11.lga...
> > > > I want to do post place and route timing simulation on a Virtex2
> part
> > > using
> > > > the Xilinx Modelsim starter simulator, how can I set the
> temperature
> > point
> > > > to 70 celcius?
> > >
> > > Add
> > >
> > > temperature=70C;
> > >
> > > to your UCF
> > >
> > > Regards
> > > Falk
Article: 77852Stuart Brorson wrote: > In sci.electronics.cad Chuck Harris <cf-NO-SPAM-harris@erols.com> wrote: > : Problems/complaints: > > : 2) The schematics in the examples are all composed of main pages with > : the transistors and diodes being subpages. There is no obvious (to me > : the new user) way of making the link so the transistors appear on the > : schematic. Examples are presumably meant for new inexperienced users, > : and as such should work flawlessly. > > Please help me improve the linkage between these schematics. Is your > point that you can't open the lower-level schematics from the top > level schematic via "Hierarchy -> Down Schematic"? If so, it was a > bug in the examples; I have just fixed it. > > If you want, try the fix. Edit your gafrc (living in the RF_Amp > directory), and add the line (on a new line): > > (source-library ".") > > Then, open MSA-2643.sch, double click on Q1, and add the following > attribute to it: > > Attrbute name: source > Attribute value: Q1.sch > > Do the analogous thing for Q2. Then you should be able to use > "Hierarchy -> Down Schematic" in the top menu bar to dive into the > models for Q1 & Q2. > > Please let us know if this works for you. > > Thanks, > > Stuart Hi Stuart, Ok, I have figured out what's going on. If you cd to the directory that the RF_Amp is in, and then invoke gschem, Open page and select the MSA-2643.sch drawing, everything works the way you all probably expected it to. However, if you are in some miscellaneous directory, and invoke gschem, Open page, and wind your way through the directory structure until you find the MSA-2643.sch drawing, and open it, then you get a schematic with blank spots where the transistors should be. So, what is happening is you only read the gafrc file for the directory that you are in when gschem is invoked. What to do? It doesn't seem too unreasonable for a person to be able to start up the geda tools from any old directory they happen to be in and browse their way to the design files using open page, and expect the right thing to happen. It seems to me that a reasonable solution would be to have gEDA tools read any appropriate rc files found in the directories where you open a new, or old page. I am unsure what would be the best solution for opening a new page in a new empty directory. Perhaps if the directory is created from within the gEDA tools, the directory should be prefilled with an rc file from some template directory? -ChuckArticle: 77853
Why not use Confluence to generate your low level components, then instantiate them into your higher-level designs? (Note: Confluence 0.9.3 is the latest version with support for VHDL. 0.10.0 is Verilog-only at this point. VHDL will be back on-board with 0.10.1.) -TomArticle: 77854
On Tue, 18 Jan 2005 14:55:47 -0500, Chuck Harris <cf-NO-SPAM-harris@erols.com> wrote: >There is no reason that you have to pay RedHat. The amount you pay is >purely for their support. You can get the entire distribution from a >number of places. One is www.tux.com Are you sure? The RedHat site gives no hint that you can run the current RHs without paying. The free distribution is FCx, which is different. BTW, www.tux.com sells tuxedos... :) RickArticle: 77855
G=F6ran wrote:
>> It's never too late to learn a new language :)
>> Thanks for the tip, but I think that VHDL will have to do (for
now)..
>> Moti.
>
> You can also do recursive hardware in VHDL.
> Although it's not as small as confluence.
>
> G=F6ran
Yes, but VHDL lacks higher-order datatypes. Try passing an
entity/architecture pair into an instance of another through a generic
port.
What is this good for? Imagine a generic binary tree component that
accepts a binary operation as an input. The same recursive component
can assemble a tree of XOR gates, tree of adders, or a tree of
multiplexors. In Confluence, you can pull this off:
{tree ('+') unify vector_list summation_result}
-Tom
Article: 77856Starbridge Systems (www.starbridgesystems.com) is looking for some good FPGA engineers. Please email me (bbking at starbridgesystems dot com) a résumé if you are interested and meet all these qualifications: 1. Have several years of experience programming in Verilog/VHDL 2. Have several years of experience programming in C/C++. 2. Have a BS degree in computer science or computer engineering 3. Have familiarity with Xilinx tools and chips 4. Love programming down to the bare metal 5. Be willing to relocate to Salt Lake City, UT Preference is given to these other valuable skills that would be used: 1. Compiler writing / XML parser writing 2. PCB layout 3. Computer science theory, i.e., recursion / D & C, SWAR, neural nets, etc. 4. Driver writing 5. Serious linear algebra / sparse matrix / GPU algorithms 6. Serious DSP algorithms and implementations -- Prepend a 'b' to reply to this email. Thanks.Article: 77857
In sci.electronics.cad Chuck Harris <cf-NO-SPAM-harris@erols.com> wrote:
: Hi Stuart,
: Ok, I have figured out what's going on. If you cd to the directory
: that the RF_Amp is in, and then invoke gschem, Open page and select
: the MSA-2643.sch drawing, everything works the way you all probably
: expected it to.
: However, if you are in some miscellaneous directory, and invoke gschem,
: Open page, and wind your way through the directory structure until
: you find the MSA-2643.sch drawing, and open it, then you get a schematic
: with blank spots where the transistors should be.
: So, what is happening is you only read the gafrc file for the directory
: that you are in when gschem is invoked.
: What to do? It doesn't seem too unreasonable for a person to be able to
: start up the geda tools from any old directory they happen to be in and
: browse their way to the design files using open page, and expect the
: right thing to happen.
: It seems to me that a reasonable solution would be to have gEDA tools
: read any appropriate rc files found in the directories where you open
: a new, or old page. I am unsure what would be the best solution for
: opening a new page in a new empty directory. Perhaps if the directory
: is created from within the gEDA tools, the directory should be prefilled
: with an rc file from some template directory?
Hi Chuck --
OK, this is a user education issue. Sorry!
Loosely speaking, gEDA has three sets of RC files: One system wide,
one for you as a user, and one living in the local project directory:
* The system one lives in ${PREFIX}/share/gEDA, where ${PREFIX} =
wherever you stuck your gEDA stuff when you installed the dist. This
one holds most of the path info about where symbols live. It is
always read in upon program start-up.
* The user one should live in ${HOME}. You can use this for
customizations you would like to use across all your projects. (Like
remapping the key actions, or screen colors.) Gschem
tries to read it upon program start-up, but only warns you if it can't
find it.
* The project one lives in the project directory where the schematic
files are stored. This one is used for customizations local to that
particular project. (Like storing local symbol files, or other
project-specific stuff.) Gschem tries to read it upon program
start-up, but only warns you if it can't find it.
When gschem opens up, it tries to read all three. However, if you
run gschem on a file living in another directory from the one you are
in, then it doesn't see the project-specific RC file.
In the case of the RF_Amp example, the gafrc file lives in the RF_Amp
project directory. I am not sure that making that project-local RC
file work when reading the .sch file from outside that directory is a
good idea. The vision is that you put project-specific customizations
into there. That means that you run gschem while working out of that
directory.
There is a mechanism for specifying which RC file to load using the -r
flag, but it doesn't seem to follow file paths like "./sym" correctly
(I just checked). I can file a bug report on this.
I agree that the nice thing to do is to have all schematic open
correctly from everywhere. The way to do that is to have gschem
deduce the project directory from the path to the file being opened,
and then open the corresponding RC file. But what if a user then
opened two files in two different directories? Which RC file to open?
Both? What if they conflict?
Therefore, this question needs some further thinking. Meanwhile, it
does raise the question of bullet-proofing the examples for newbies.
I'll think about that.
Stuart
Article: 77858On Tue, 18 Jan 2005 09:30:50 +0000, Rick Thompson wrote: > On Mon, 17 Jan 2005 11:46:53 -0500, Chuck Harris > <cf-NO-SPAM-harris@erols.com> wrote: > >>I want to go to Debian, but I am finding it hard to get excited about >>ripping my system apart and starting over...If only there was a safe >>and easy way to move from RedHat to Debian... > > The EDA vendors only support RedHat, so I'm sticking with it, whatever > its faults. And, finally, after all these years, we now actually have > a professional Linux distribution, that's not just put together by > hackers. But I'll tell you what really pi**es me off about it - they > now charge an *annual* subscription for it. I've been buying Windoze > distributions for 20-odd years, and I've never once had to pay an > annual subscription. I bought my current Win2K 4 years ago, and I can > still download updates and security fixes for free. What exactly makes > RedHat think that they can charge year-on-year for that? They think they can, because they can. It's pretty much that simple. People pay them. People want Aunt-Tillie-Ready stuff, with the security of a Linux kernel, so they pay the Redmond^H^H^H^HHat people to do all of their configuration for them. > If they'd > just asked me for a one-off $200 then I'd have paid it. I'm running FC2 > now, despite having to download the whole thing. I paid $40.00 for the 4-disk Slackware set, and I'm quite happy with it, and it's downloadable for free. Actually, the only reason I actually paid for it is because I want to support Mr. Volkerding and the whole Slack mystique. ;-) You do have to know enough about your computer to be able to manage it, however. Or be willing to learn. As far as "The EDA vendors only support RedHat", that could be because Redmond^H^H^H^HHat is the only distro that _needs_ vendor support. I'll be installing gEDA from source Real Soon Now, and I'll give a full report. Good Luck! RichArticle: 77859
Rick Thompson wrote: > On Tue, 18 Jan 2005 14:55:47 -0500, Chuck Harris > <cf-NO-SPAM-harris@erols.com> wrote: > > >>There is no reason that you have to pay RedHat. The amount you pay is >>purely for their support. You can get the entire distribution from a >>number of places. One is www.tux.com > > > Are you sure? The RedHat site gives no hint that you can run the > current RHs without paying. The free distribution is FCx, which is > different. > > BTW, www.tux.com sells tuxedos... I had meant www.tuxcds.com, but I got it mixed up with www.tux.org, and ended up someplace in the muddle. But they don't seem to have RHEE anyway. I am not sure how redhat could restrict the enterprise edition, being as it is based on GPL'd code. Anyway, I am heading in the Debian direction. It is as stable as you want it to be. -ChuckArticle: 77860
Stuart Brorson wrote: > Hi Chuck -- > > OK, this is a user education issue. Sorry! I cannot honestly say that I have done a good job working my way throught the documentation. I only have a little time each day to play, and then I seem to tend to just jump in... > > Loosely speaking, gEDA has three sets of RC files: One system wide, > one for you as a user, and one living in the local project directory: > [snip] > I agree that the nice thing to do is to have all schematic open > correctly from everywhere. The way to do that is to have gschem > deduce the project directory from the path to the file being opened, > and then open the corresponding RC file. But what if a user then > opened two files in two different directories? Which RC file to open? > Both? What if they conflict? Spawn a version of gschem for each file, and use the corresponding project rc file for each incantation? > > Therefore, this question needs some further thinking. Meanwhile, it > does raise the question of bullet-proofing the examples for newbies. > I'll think about that. > > Stuart In any case, I believe the only thing the gEDA suite should take from the place it was invoked is the home directory root. The gafrc project file must be correct for the file that is currently being displayed on screen. -ChuckArticle: 77861
Rich Grise wrote: > On Tue, 18 Jan 2005 09:30:50 +0000, Rick Thompson wrote: > > > I paid $40.00 for the 4-disk Slackware set, and I'm quite happy with it, > and it's downloadable for free. Actually, the only reason I actually paid > for it is because I want to support Mr. Volkerding and the whole Slack > mystique. ;-) > > You do have to know enough about your computer to be able to manage it, > however. Or be willing to learn. > > As far as "The EDA vendors only support RedHat", that could be because > Redmond^H^H^H^HHat is the only distro that _needs_ vendor support. > > I'll be installing gEDA from source Real Soon Now, and I'll > give a full report. > > Good Luck! > Rich > All in all, the installation went ok once I ironed out two small problems. I think you will have fun. The suite looks quite competent. -ChuckArticle: 77862
Marie, I don't know which FPGA family you are using. Have a look in the datasheet. The I/O performance can be found there. Regards, Daniel LeuArticle: 77863
Check out the Xilinx Tech Exclusive at : http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=rg_cust_periph I went thru it and got a peripheral to work using PPC (not MicroBlaze). It goes through some steps about simulating the OPB interface. You might want to investigate the use of ChipScope Pro too. -Newman "jralston" <jralston@calpoly.edu> wrote in message news:827740a1c2e4d019b13a6bced8ad7327@localhost.talkaboutelectronicequipment.com... > Hello, > I'm trying to create a submodule in EDK that contains microblaze and a > custom core that basically just passes some of the OPB signals through to > the top: > > --forward signals > CLK <= Bus2IP_Clk; > CS <= Bus2IP_CS; > RdCE <= Bus2IP_RdCE; > WrCE <= Bus2IP_WrCE; > Reset <= Bus2IP_Reset; > Addr <= Bus2IP_Addr; > Data_out <= Bus2IP_DATA; > IP2Bus_DATA <= Data_in; > > When I connect the signals to a test register in ISE I am able to properly > write to the register from microblaze using XIo_Out32, but when I try to > read the value back using XIo_In32 it always reads 0x00000000, even when I > connect a constand value to the Data_in signal. I am able to read the > register through other hardware to see that it is being written correctly, > but never when using microblaze. > > Along the same lines, I am trying to trigger global interrupts to > microblaze, but they are not working. I am enabling them in my code and > have set the global interrupt handler. I make the microblaze INTERRUPT > port external and trigger it in my VHDL code. > > Do you need to do something special with input signals when having > microblaze as a submodule? Any advice would be appreciated. > > Thanks! >Article: 77864
Do any of you know if there is more information on configuring the FPGA with Micro-controller, other than the XAPP 502 document. I was looking at using the slave serial method to configure the FPGA. Can one use the same method (Slave Serial with Microprocessor) to configure PROMS? Thanks -YNArticle: 77865
Hi Andre,
Your best bet is to start reading the Timing Analysis section of the
Quartus Handbook. It is extensive, has clear definitions and explains
everything with good figures.
http://www.altera.com/literature/hb/qts/qts_qii5v3_02.pdf
Tco and Tpd are computed using the longest path:
- TPD: Tells the fitter to try to keep the longest path under the given
value
- TCO: Tells the fitter to try to keep longest Tco under the given value
Min Tco and Min Tpd are used computed using the shortest path
- Min TPD: Tells the fitter to try to make all pin to pin paths
(including shortest path) slower than this setting.
- Min TCO: Tells the fitter to try to make all Tco paths (including
shortest path) slower than this setting.
These constraints have nothing to do with multi-clock designs. They are
simply easy ways to set global values.The way to constrain a complex
multi-clock designs is to make instance specific Tsu/Th/Tco/etc constraints
on each pin.
Quartus supports constraints similar to Primetime, where all I/Os are
constrained by simply specifying external delays (basically specifying the
Tco/MinTco of the chip driving the input pin of the FPGA and specifying the
Tsu/Th of the chip the FPGA output pins drive to).
Assuming all clocks are constrained with a CLOCK_SETTING, you can use a
MAX_DELAY -from <pin> -to <register> to constrain the path
such that the fitter will pack the register into the IOCell. You can also
use fitter assignments to enforce the placement.The one that you will need
is to apply the FAST_INPUT_REGISTER=ON to the register you want placed in
the IO Cell.
You can also use a small Tsu constraint on that input pin, which should
result in the same IOC placement, i.e. let the Fitter figure it out for you.
Hope this helps.
Subroto Datta
Altera Corp.
"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0501180315.1d4fbf3c@posting.google.com...
> Hello,
>
> when having a look at the TIMING REQUIREMENTS & OPTIONS
> I see that there are
> DELAY REQUIREMENTS with Tsu, Tco, Tpd, Th
>
> and MINIMUM DELAY REQUIREMENTS with Tco, Tpd
>
> What is the difference when defining these constraints ?
> Does these constraints make sense when having a multiclock system ?
>
>
> When sampling an asynchronous signal coming into the FPGA
> how can I make the synthesis tool place the first flipflop of
> a synchronizing flip flop chain
> in a I/O register cell to improve Tsu ?
> Thanks in advance.
>
> Rgds
> André
Article: 77866Hi Mikhail, The problem could be becuase of the reset of the DCM. Ensure that the DCM is given a proper reset. Also there are some errat's on the V2P DCM when you use it in fixed phase mode and variable phase mode. Search for the following errats in www.xilinx.com/support regards Chander Symon wrote: > Mikhail, > My suspicion is that, because the design never works 100%, there's a jitter > problem somewhere. So use the real hardware! Things such as an inadequately > filtered Vccaux can cause this. > Good luck, Syms. > "MM" <mbmsv@yahoo.com> wrote in message > news:354vncF4hef03U1@individual.net... > > > > Symon, > > > > Do you mean to try it in simulation or in real hardware? > > > > /Mikhail > > > >Article: 77867
Hi Bala, It is hard to be sure without seeing your design, but it sounds like the multicycle assignments you're making are to combinational logic. I think your best bet would be to research exactly how Synplify names registers, to ensure you are putting the multicycle constaints on the correct names. Quartus accepts multicycle assignments only on registers, so it will throw any multicycle assignments away if they're on combinational logic. If you can't figure out how to set the multicycles such that they wind up on the correct registers in Synplify, you can make the assignments in Quartus, but as you say that is a bunch of extra work if you also want to expose the assignments to Synplify, so it's not a perfect solution. Using timegroups, wildcards and entity-based assignments to make the timing assignments in Quartus may reduce the work to a managable level though. Hope this helps, Vaughn Altera [v b e t z (at) altera.com] "Bala_k" <bala2k4@gmail.com> wrote in message news:1105957175.063284.187490@f14g2000cwb.googlegroups.com... > Hi, > > I have a problem with Forward-Annotating multicycle, false path > constraints from Synplify Pro 7.7.1 to Quartus 4.2 . I have given all > the multicycle and false path constraints to Synplify Pro. It is being > taken by Synplify and writing to design.tcl file also. The same > design.tcl file i am using for porting constraints to Quartus. Whatis > happening is in the netlist output given by Synplify, some of the > multicycle/false path destination registers have become combo logic(i > really don't know why?), and being ignored by Quartus. In fact, there > are some valid multicycle registers, terminated by (or through) that > combo logic. But the destination register, is not forward annotated by > Synplify. Since Quartus sees only a combo logic, and not able to find > the destination register(which is the actual multicyle path), its > ignoring my assignments. This gives me a lot of timing violations also. > There are more than 100s of such multicycle registers, so manually > searching and changing to correct registers, is not an easy task, and > bound to mistakes. Have anybody encountered these types of problems? > Please help me solve this issue. > > Thank you, >Article: 77868
tom wrote:
> Göran wrote:
>
>>>It's never too late to learn a new language :)
>>>Thanks for the tip, but I think that VHDL will have to do (for
>
> now)..
>
>>>Moti.
>>
>>You can also do recursive hardware in VHDL.
>>Although it's not as small as confluence.
>>
>>Göran
>
>
> Yes, but VHDL lacks higher-order datatypes. Try passing an
> entity/architecture pair into an instance of another through a generic
> port.
>
> What is this good for? Imagine a generic binary tree component that
> accepts a binary operation as an input. The same recursive component
> can assemble a tree of XOR gates, tree of adders, or a tree of
> multiplexors. In Confluence, you can pull this off:
> {tree ('+') unify vector_list summation_result}
>
>
> -Tom
>
Yes, That is something I miss from VHDL.
It would have been good if VHDL had taken more from ADA on the generic
functionality.
Göran
Article: 77869After further consideration, IIRC, the mentioned tech exclusive did not read back data, it is an LCD display. Newman "jralston" <jralston@calpoly.edu> wrote in message news:827740a1c2e4d019b13a6bced8ad7327@localhost.talkaboutelectronicequipment.com... > Hello, > I'm trying to create a submodule in EDK that contains microblaze and a > custom core that basically just passes some of the OPB signals through to > the top: > > --forward signals > CLK <= Bus2IP_Clk; > CS <= Bus2IP_CS; > RdCE <= Bus2IP_RdCE; > WrCE <= Bus2IP_WrCE; > Reset <= Bus2IP_Reset; > Addr <= Bus2IP_Addr; > Data_out <= Bus2IP_DATA; > IP2Bus_DATA <= Data_in; > > When I connect the signals to a test register in ISE I am able to properly > write to the register from microblaze using XIo_Out32, but when I try to > read the value back using XIo_In32 it always reads 0x00000000, even when I > connect a constand value to the Data_in signal. I am able to read the > register through other hardware to see that it is being written correctly, > but never when using microblaze. > > Along the same lines, I am trying to trigger global interrupts to > microblaze, but they are not working. I am enabling them in my code and > have set the global interrupt handler. I make the microblaze INTERRUPT > port external and trigger it in my VHDL code. > > Do you need to do something special with input signals when having > microblaze as a submodule? Any advice would be appreciated. > > Thanks! >Article: 77870
Hi Vaughn, Thank you for the suggestion. In Synplify, i am assigning multicycle constraint to registers only. But after mapping synplify adds a mux after register. This essentially blocks the regout to come out of LE. Only a combo out is going out of that LE. So synplify is porting the comboout name instead of the register's. I could find the register in Quartus Resource Property Editor view. But the problem is every rtl change can rename, the register name, and I have to repeat the same exercise every time. I am now trying to use wild cards, and attributes like syn_keep, syn_preserve etc in Synplify to keep the names. Vaughn Betz wrote: > Hi Bala, > > It is hard to be sure without seeing your design, but it sounds like the > multicycle assignments you're making are to combinational logic. I think > your best bet would be to research exactly how Synplify names registers, to > ensure you are putting the multicycle constaints on the correct names. > > Quartus accepts multicycle assignments only on registers, so it will throw > any multicycle assignments away if they're on combinational logic. If you > can't figure out how to set the multicycles such that they wind up on the > correct registers in Synplify, you can make the assignments in Quartus, but > as you say that is a bunch of extra work if you also want to expose the > assignments to Synplify, so it's not a perfect solution. Using timegroups, > wildcards and entity-based assignments to make the timing assignments in > Quartus may reduce the work to a managable level though. > > Hope this helps, > > Vaughn > Altera > [v b e t z (at) altera.com] > > > "Bala_k" <bala2k4@gmail.com> wrote in message > news:1105957175.063284.187490@f14g2000cwb.googlegroups.com... > > Hi, > > > > I have a problem with Forward-Annotating multicycle, false path > > constraints from Synplify Pro 7.7.1 to Quartus 4.2 . I have given all > > the multicycle and false path constraints to Synplify Pro. It is being > > taken by Synplify and writing to design.tcl file also. The same > > design.tcl file i am using for porting constraints to Quartus. Whatis > > happening is in the netlist output given by Synplify, some of the > > multicycle/false path destination registers have become combo logic(i > > really don't know why?), and being ignored by Quartus. In fact, there > > are some valid multicycle registers, terminated by (or through) that > > combo logic. But the destination register, is not forward annotated by > > Synplify. Since Quartus sees only a combo logic, and not able to find > > the destination register(which is the actual multicyle path), its > > ignoring my assignments. This gives me a lot of timing violations also. > > There are more than 100s of such multicycle registers, so manually > > searching and changing to correct registers, is not an easy task, and > > bound to mistakes. Have anybody encountered these types of problems? > > Please help me solve this issue. > > > > Thank you, > >Article: 77871
A master thesis comparing the LEON2, Microblaze and Openrisc-1200 processors has been carried out by two students from the Chalmers University in Sweden. The final report is now available online at: http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf . Jiri Gaisler Gaisler ResearchArticle: 77872
On Wed, 19 Jan 2005 02:29:02 -0800, jiri_gaisler wrote: > A master thesis comparing the LEON2, Microblaze and Openrisc-1200 > processors has been carried out by two students from the Chalmers > University in Sweden. The final report is now available online at: > > http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf > . > I would have thought that a comparison of synthesisable cores would have included a Nios 2 as well, and would have included other fpga targets - the conclusions might have been wildly different if an Altera fpga were used, or even if a different Xilinx fpga were used rather than just the one Virtex II. The thesis claims to cover portability, yet only considers "porting" the cores to a single Virtex II board! As open designs, the Leon2 and Openrisc cpus are a world apart on portability compared to vendor-specific cores like the Microblaze and the Nios. I think it is also important to make version information clear - I don't know details about the processors here, but the Nios family has changed dramatically in the year or so that I've been using it, and such comparisons are only valid for a particular generation of the cores.Article: 77873
On Tue, 18 Jan 2005 23:50:35 GMT, Rich Grise <richgrise@example.net> wrote: >On Tue, 18 Jan 2005 09:30:50 +0000, Rick Thompson wrote: > >> On Mon, 17 Jan 2005 11:46:53 -0500, Chuck Harris >> <cf-NO-SPAM-harris@erols.com> wrote: >> I bought my current Win2K 4 years ago, and I can >> still download updates and security fixes for free. What exactly makes >> RedHat think that they can charge year-on-year for that? > >They think they can, because they can. It's pretty much that simple. >People pay them. People want Aunt-Tillie-Ready stuff, with the security >of a Linux kernel, so they pay the Redmond^H^H^H^HHat people to do all of >their configuration for them. I've got no problem with configuration. I've got RH7.2 on one machine and FC2 on another, with various different combinations of libc, gcc, gdb, gtk, and all the rest of it, without problems. My issue is with all the half-arsed beta front-end stuff that the hackers put out with every distro and every release of that distro. Just one example: the help system on my RH7.2 never worked, despite a clean install, because of some Nautilus configuration problem that I couldn't find. How can you *possibly* ship a leading distribution with this level of incompetence? Bill Gates must be laughing all the way to the bank. The great thing about the new RedHat is that they might, finally, bring a level of professionalism that could consign all this nonsense to history. But, of course, without an annual subscription. Bill Gates didn't need it, after all. >As far as "The EDA vendors only support RedHat", that could be because >Redmond^H^H^H^HHat is the only distro that _needs_ vendor support. Synopsys, Cadence, and Mentor aren't stupid; they turn over nearly $3B between them. I don't know why they supported it historically, but RH7.2 was widely accepted. If that's good enough for them, then that's all the encouragement I need. Linux badly needs some standardisation; having so many distributions may be great for hackers, but it could kill Linux for serious work. BTW, I used Debian for a year and wasn't impressed. RickArticle: 77874
Hi, I'm looking for a video decoder board, that could be plugged on an Altera dev. board proto header. (cyclone or stratix) The decoder chip used could be any popular one (TVP5150, SAA7115...). Could anybody answer me? Thanks O.Descoubes
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