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"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message news:curmki$4pa$1@news.dialog.net.pl... > Hello, > > I have a source of extremely stable and clean clock > signal. Its frequency is about 64 MHz. I would like to > use it as the main clock for a Cyclone FPGA chip > (1C6, to be exact). The problem is that the signal > is a sine wave with the amplitude of about 1Vpp. > The exact level is not an issue, I can amplify or attenuate > it appropriately, but the shape bothers me: may I feed > the FPGA clock input with this signal directly? If yes, > then what is the optimal level of the signal? But if this, > unfortunately, is not allowed, then what solution would > you recommend me? You could amplify it with a MMIC (like the MInicircuits ERA-1) and square it up with a Schmidt trigger. LeonArticle: 79151
>> I would be happy to go the KISS path, but I don't know how one can keep >> a soft-cpu module simple to handle. You have too many options: You're >> developing on two levels: the CPU inside the FPGA with peripheral components >> and software for the CPU. During development on one of these areas different >> ways for downloading the configuration/software fits best: >> >> Simplest: Flash is configured with JOP waiting for a download of a Java program. >> How do you donwload it? Via a serial interface - Then we need a serial interface. >> Program the serial Flash with the Java program. Not very comfortable during >> development - You have to use Quartus for the Flash programming, but you are >> only interested in Java development. >> Now you start changing JOP, e.g. do some FPGA development. Do you want to >> program the Flash for every try or do you prefere to download the configuration >> direct to the FPGA. Then we need a second ByteBlaster adapter (one for the Flash >> and one for the Cyclone). Two pin heads need space and make it more complicate >> to handle the board (not the KISS path). > > It depends on the bandwidths, but I like Pablo's idea of a FT2232C - there may be enough smarts > between that device, and your FPGA, to improve PC-target bandwidths for debug (single step?) and > download -> SDRAM, prior to code FLASH for final pass. From your first suggestion I thought you mean USB master on the FPGA to use USB devices. > Perhaps a 'virtual jumper' in the FPGA code, or'd with a FT2232C pin, could select Load from > USB.FIFO, or top of SerialConfig ? I don't get the idea. For configuration from Flash I want the module to run stand-alone. That means no USB connection. The FT2232C has to be disabled in this mode and the power has to be provided through a different pin (from the SIMM bus, e.g.). > > Another device that appeals for Soft-cpu is this one : > http://www.st.com/stonline/press/news/year2005/p1563m.htm > with 75MHz burst, 32 bits wide, that's 2400MB/s, vs 25-50MB/s on a SD card. > So the SD card looses on speed, but gains on universal supply/size, > and you CAN easily remove it - hmmm... perhaps put the M58BW032 on the > other side of the PCB ? It was not the idea to exectue (Java) code direct from the SD card. We have large SDRAM on board. The code is copied from the SD card (or serial Flash) to the SDRAM prior execution. So speed is not the point. The SD card can further act as file system. I know that the automotive industry does like to execute direct from Flash. They want to avoid the additional boot time due to the memory copy. They want a boot in the ms region. However, this is not the problem for this board. > > Maybe option the SD socket, and M58BW032, on the more complex model ? > > Next, some form of Codec would be nice, what about something from this selection ? > http://para.maxim-ic.com/compare_noj.asp?Fam=CODEC&Tree=Wireless&HP=Wireless.cfm&ln= > $5-7 for 22-60Msps ADC & DAC ? > This ties in well with a SD socket, & USB link... What for would you use these Codecs? >> First ideas about the memory card format (still SIMM): >> http://www.jopdesign.com/jopstick/index.jsp >> >> One format is very small with a FPGA in TQFP100. There are just enough pins >> for the SDRAM and the SimmStick bus. The second variant is larger with >> a TQFP144 FPGA and a slot for a SD card. > > SD starts to look nice on this basis... But the SD connector is still 'large' ;-) > >>> Besides the simmmstick itself, you should consider the SODIMM modules, >>>as seen in TINI : >>> http://www.maxim-ic.com/products/tini/pdfs/TINI_GUIDE.pdf >> >> >> Yes, another option. However, is there a kind of 'standard' for this larger modules. >> Are there peripheral modules available for this form factor? > > The TINI itself ? ;) > - plus as TINI also has Java path, you could get some cross-polination ? > Yes, a point to consider. I don't know how large the TINI user base is. As the TINI is a VERY slow JVM, JOP could be a fine replacement (JOP is almost 200 times faster than the TINI). And you have an FPGA... Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 79152
> try changing compiler options Hi Antti, which compiler options should I change? I tried to do it without optimization but then the code is to big ... Which EDK Software were you using? I have the 6.2.03i version Cheers PhilippArticle: 79153
"Philipp" <carlsberg@gmx.at> schrieb im Newsbeitrag news:37e7avF5c207dU1@individual.net... > > > try changing compiler options > > Hi Antti, > > which compiler options should I change? I tried to do it without > optimization but then the code is to big ... > > Which EDK Software were you using? I have the 6.2.03i version this problem I reported was on some earlier EDK the latest EDK forced to switch global ptr off to get the previously ok code to work you can try all options-combinations and pray that some works if things go bad, but.. in your case as you are doing some FSL stuff that may stall the microblaze so that may be your problem. it just sounded similar to several compiler related issues we have had, AnttiArticle: 79154
Leon Heller wrote:
> You could amplify it with a MMIC (like the MInicircuits ERA-1)
The original signal has about 6Vpp and the output is taken from
a divider connected to an emitter follower, so it is enough to
decrease attenuatnion.
> and square it up with a Schmidt trigger.
The problem is that I have no fast enough 3.3V CMOS trigger,
so I decided to use a squaring circuit made of a comparator or
even of discrete elements, like this (at the third picture):
http://www.wenzel.com/documents/waveform.html
Best regards
Piotr Wyderski
Article: 79155
austin wrote:
> The problem with a sine wave is the slow dV/dt. That will lead to
> jitter when there is ground bounce.
Good point, especially taking into account the length
of the clock signal path, which is about 5 cm.
> A separate slicer (comparator) is a better solution in most cases.
So I will try to find a fast enough comparator or make my
own squaring circuit using two BFR92A UHF transistors.
Thank you for your replies!
Best regards
Piotr Wyderski
Article: 79156Yes, I have seen this thread, and also had a few private emails from people having problems. The real problem is that there are no clear guidelines as to how to create truly portable netlist distributions. I have searched the answer database, and the xilinx web site in general, but all information I was able to find was incomplete at best. Could somebody from Xilinx (or anybody else who has been successful doing this) post a step by step tutorial as to how to create portable netlist distributions ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 79157
"Rudolf Usselmann" <russelmann@hotmail.com> schrieb im Newsbeitrag news:cusrop$tmj$1@nobel.pacific.net.sg... > > Yes, I have seen this thread, and also had a few private emails > from people having problems. > > The real problem is that there are no clear guidelines as to > how to create truly portable netlist distributions. I have > searched the answer database, and the xilinx web site in > general, but all information I was able to find was incomplete > at best. Hi Rudi, I think a bus bridgeing component for EDK can not be implemented fully as netlist at all, not with current state of the tools, and maybe never. So at least one file of the ip core should be HDL source the remaining can be netlist. The parameters are handled in the HDL part of of the core. AnttiArticle: 79158
Hi Georgi We didn't use ribbon cables like this, because in our application the connectors were either wired via miniature coax to SMAs (to connect to the 81250) or used to connect to daughter cards. So long as the differential impedance of the LVDS pair in the ribbon cable is close to 100ohms (which it should be) this should be fine, so long as the cables are short enough that loss isn't an issue (coax is much lower loss than standard ribbon). Crosstalk will certainly not be an issue with 2 grounds between the LVDS pairs. Cheers IanArticle: 79159
> but.. in your case as you are doing some FSL stuff that may stall the > microblaze > so that may be your problem. Yeah but the thing I dont understand is that I can execute 8000 instructions without any trouble and then suddenly it just overwrites me an arbitrary register by executing a simple addition instruction. And with a dummy function it works.... weirdArticle: 79160
To solve the Ngbuild problem at bitstream generation > * First step : Install the opb2wb > -------------------------------- > > - Extract the opb2wb_v1_00_a from the tar.gz and put it into your > personnal pcore dir > - Edit the bbd file and suppress the first column (C_FAMILY) to just > leave the first line > So you should have > > <cut here> > Files > ###########...##### > opb2wb_v1_00_a.edn > <end cut> > > - Edit the mpd file and rename the 'opb_rst' into 'rst' (only the > lowercase one. > leave the OPB_rst untouched ). - Edit the netlist file (.edn) and > change the creator program to "none" > So you have (program "none") instead of (program "xilinx stuff ...") > The ngcbuild don't like to work with edif netlist created by ngc2edit > and tells > you to use the original ngc instead but we don't have it ... > Another step : Rename the .edn file to just opb2wb (without version). Also don't forget to ajust the name in the bbd file as well. Then it generate a bitstream just right. Sylvain MunautArticle: 79161
Hi, I'm working with a Virtex II Pro, and I want know where can I find the number of slices that change in partial bitstream. Thank you.Article: 79162
Hi Rudi,
I was one of the private e-mail you receive.
I would like to know what you have done to make it work in your environement
?
How did you test it ?
whith what wishbone core ?
etc..
Jonathan
"Rudolf Usselmann" <russelmann@hotmail.com> a écrit dans le message de news:
cusrop$tmj$1@nobel.pacific.net.sg...
>
> Yes, I have seen this thread, and also had a few private emails
> from people having problems.
>
> The real problem is that there are no clear guidelines as to
> how to create truly portable netlist distributions. I have
> searched the answer database, and the xilinx web site in
> general, but all information I was able to find was incomplete
> at best.
>
> Could somebody from Xilinx (or anybody else who has been
> successful doing this) post a step by step tutorial as to
> how to create portable netlist distributions ?
>
> Thanks,
> rudi
> =============================================================
> Rudolf Usselmann, ASICS World Services, http://www.asics.ws
> Your Partner for IP Cores, Design, Verification and Synthesis
Article: 79163
I've searched around Xilinx's site, but I havent' been able to find the
meaning of this error message (there was a message there about how this
had been fixed in XSE 4.something, but I've tried on both 6.2i and 6.3i
and still get the same error).
Here's the error:
Analyzing Entity <csvm> (Architecture <synth_csvm>).
ERROR:Xst:829 - C:/phil/vhdl/svm/../fix_std.vhd line 1382: Constant Value
expected for Generic 'U'.
Here's the offending line:
Copy_V(F, N, overflow, rounding);
Here's the Copy_V function:
procedure Copy_V(
target : out UFix;
source : UFix;
overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
rounding : Fix_Rounding_Mode := Fix_Default_Rounding
) is
subtype target_T is UFix(target'RANGE);
variable W: UFix(Max(target'LEFT, source'LEFT+1) downto
Min(target'RIGHT, source'RIGHT));
constant HighZero: UFix(W'LEFT downto target'LEFT+1) := (others =>
'0');
begin
assert not target'ASCENDING
report "target" & bad_direction_msg
severity direction_severity;
assert not source'ASCENDING
report "source" & bad_direction_msg
severity direction_severity;
W := (others => '0');
W(source'RANGE) := source;
if target'RIGHT > source'RIGHT then
case rounding is
when clip_LS | towards_zero =>
null;
when to_nearest =>
W(W'LEFT downto target'RIGHT-1) := UFix(
unsigned(W(W'LEFT downto target'RIGHT-1)) + 1
);
end case;
end if;
target := W(target'RANGE);
if HighZero'LENGTH > 0 then
if unsigned(W(HighZero'RANGE)) /= unsigned(HighZero) then
case overflow is
when clip_MS =>
null;
when saturate =>
target := target_T'(others => '1');
end case;
end if;
end if;
end;
I have no idea what this error message is trying to tell me. This code
compiles fine in my simulator (GHDL).
Any ideas about what this means?
Phil
Article: 79164"austin" <austin@xilinx.com> wrote in message news:curnam$baj2@cliff.xsj.xilinx.com... > Well, > > John, the issue is "what is the leakage current of the new 90nm technology > node?". > > Xilinx has claimed (and we think we have proved it) that the use of triple > oxide (basically keeping memory cells and pass gates at 130 nm in 90nm) > gives us both speed, and a 3X leakage advantage. Austin, You have posted here that the worst-case silicon, 85 C leakage for Vccint only in an LX200 is 3.3 A. Add to that the 416 mW of Vccaux leakage from the xilinx web power calculator (for typical silicon!) and you get a total *mostly* worst-case silicon, 85 C junction temperature leakage value of 4.38 W. The real worst-case may be higher, since no one from Xilinx has revealed a worst-case Vccaux leakage number. The worst-case silicon, 85 C junction temperature static power for the Stratix II 2S180 is 5.44 W. That number is plainly visible in our Early Power Estimator at http://www.altera.com/support/devices/estimator/st2-estimator/st2_power_est_2.1.xls This means that the Virtex4 leakage is 19.5% lower, with the important caveat that the number is not yet truly worst-case for Virtex4. In any case, hardly 3X. I am amazed that you continue to attack our worst-case silicon power numbers, while Xilinx has not published such numbers for Virtex4. Your customers are going to get themselves into big trouble if they pay attention to your marketing and produce thermal designs for typical leakage, rather than demanding complete power models from Xilinx. If your customers aren't heavily guardbanding their thermal designs, a large part of the silicon you ship them is going to result in operation outside the device thermal specifications. Of course, leakage is the smaller part of the power story. Dynamic power dominates in most designs, and about 65% of dynamic core power in a typical design comes from the logic and routing. According to your web tool, if I instantitate 72,000 slices (half using their FFs, half not) @ 200 MHz, 25% toggle, the dynamic power with medium routing is 9.05 W. We find that a Stratix II ALM implements more logic than a slice. However, even if I ignore that, our web calculator predicts a dynamic power for 72,000 ALMs @ 200 MHz, 25% toggle of 8.449 W. If I take into account the fact that an ALM implements, on average, 11% more logic than a slice, I only need 65,000 ALMs, for a total power of 7.63 W. This results is a small total power advantage for Stratix II: 13.1 W vs. 13.4 W. And I did this comparison at worst-case silicon, 85 C junction temperature, where leakage is the most important! Customers running at cooler temperatures will see leakage being less important. See http://www.altera.com/products/devices/stratix2/features/st2-competitive.html for more data, and some real silicon measurements comparing Virtex4 and Stratix II total power on real designs. Why do we have a dynamic power advantage? Simple: we used a low-k dielectric, as most of the industry has, to increase performance and cut power, while Xilinx did not. Lower k means lower capacitance on all the metal, which is now by far the dominant capacitance. Gives us both a speed and a dynamic power advantage. The last significant component of power is IO power. Here we also measure that we have an advantage, due to having half the pin capacitance of Virtex4. Also gives us a nice signal integrity advantage. Add it all up and you find that Stratix II has a power advantage for high speed designs (lots of dynamic power), while Virtex4 has a power advanage for most low-speed designs with low dynamic & IO power. The power differential is never all that large however, so I expect most customers will make their decisions based on performance, price, and features. Vaughn Betz Altera [v b e t z (at) altera.com]Article: 79165
All,
Please could someone explain how to implement the ATM Cell Payload
scrambler / descrambler defined in ITU-T I.432.1 (Section 7.3.4.1)
The standard / recommendation suggests a self-synchronising scrambler
with the polynomial X^43+1.
My current understanding is as shown below. However, I believe it to be
incorrect as I cannot recover my original data from my scrambled data.
Please advise.
Regards
Simon
Note:
XOR Function ( 0 XOR 0 = 0, 1 XOR 1 = 0, 1 XOR 0 = 1, 0 XOR 1 = 1 )
Unscrambled "data in" becomes Scrambled "data out"
Scrambled "data in" becomes Unscrambled "data out"
************************************************************************
Transmission
------------
data out
^
-------------------------------------------------|
| |
|
---->[X^0, X^1, X^2 ...... X^40,X^41,X^42]---> XOR
{43 bit shift register) ^
|
|
data in
1# Each bit of "data in" is XOR'ed with the MSB (Most Significant Bit)
of the "43 bit shift register"
2# The result of 1# is "data out" and becomes the LSB (Least
Significant Bit) of the "43 bit shift register"
3# The process is repeated for all the "data in" bits
************************************************************************
Reception
---------
data out
^
|
|
------>[X^0, X^1, X^2 ...... X^40,X^41,X^42]---> XOR
| {43 bit shift register) ^
|-------------------------------------------------|
|
data in
1# Each bit of "data in" is XOR'ed with the MSB (Most Significant Bit)
of the "43 bit shift register" and becomes the LSB (Least Significant
Bit) of the "43 bit shift register"
2# The result of 1# is "data out" and becomes the
3# The process is repeated for all the "data in" bits
************************************************************************
Article: 79166hi all, I use tsmc .13u library for pre layout synthesis. I have an option of selecting tsmc13_wl10,tsmc13_wl20,tsmc13_wl30,tsmc13_wl40,tsmc13_wl50 for this. TSMC didnt give any area range on which I can select the WL models. How do do select a model for my design. say my block area is 35kgates. Also I wanted to know that whether we can create a custom wirelaod model without floorpalnning and PnR ..If yes how.. Also please tell me how good is DC for .13u, do u think physical compiler is essential for this process? thanks JohnArticle: 79167
On 15 Feb 2005 06:43:28 -0800, "stockton" <simon.stockton@baesystems.com> wrote: >All, > >Please could someone explain how to implement the ATM Cell Payload >scrambler / descrambler defined in ITU-T I.432.1 (Section 7.3.4.1) > >The standard / recommendation suggests a self-synchronising scrambler >with the polynomial X^43+1. > >My current understanding is as shown below. However, I believe it to be >incorrect as I cannot recover my original data from my scrambled data. >Please advise. Your block diagram looks perfectly ok. You should be able to convince yourself of this by noticing that the shift registers in the Tx and Rx will contain identical bits, and that the output of the shift register gets xored with the data twice, recovering the original data. Are you aware that (assuming a different start state in the two shift registers) that the scrambler will take 43 clocks to synchronise? You will not see correct data on the output until 43 clocks into your simulation (plus additional clocks for pipelining, etc.). (Please tell me that you simulated this, rather than just downloading into an FPGA...) Regards, AllanArticle: 79168
"Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> a écrit dans le message de news: 42112cd6$0$1270$ba620e4c@news.skynet.be... > Jonathan Dumaresq wrote: >>> >>>ERROR:NgdBuild:604 - logical block 'wb2opb_0/wb2opb_0' with type 'wb2opb' >>>could >>>not be resolved. A Pin name mispelling can cause this, a missing edif or >>>ngc >>>file, or the mispelling of a type name. Symbol 'wb2opb' is not supported >>>in target >>>'spartan 3'. > >> >> I have the same probleme. I have copied you source code and try to make >> bitstream and i get the same error. >> >> do you have corrected ? > > Yes, I didn't notice that error because I didn't make a clean between my > tried > of yesterday and today's. > > After the generate bitstream failed, copy the .edn file of the opb2wb > wrapper > into the implementation directory of your edk project and rename it to > opb2wb.edn > > I didn't yet found why this is needed ... it should be done automatically > ! > (or an equivalent) > > >> I thing his happen because you remoce the C_FAMILY in the bbd file. but i >> really not shure about this. > > Don't think so. Not removing it leads to other problems earlier. And in > EDK-wizard generated core the C_FAMILY is not there. I also create a edk core from the wizard and take a look in the mpd file. I see in the mpd file under ## Generics for vhdl or Pa... PARAMETER C_FAMILY = virtex2p, DT = STRING This is probably what they need to the ncg build error ... And again i'm not shure regards Jonathan > > > SylvainArticle: 79169
"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message news:cusq4p$u8r$1@news.dialog.net.pl... > Leon Heller wrote: > >> You could amplify it with a MMIC (like the MInicircuits ERA-1) > > The original signal has about 6Vpp and the output is taken from > a divider connected to an emitter follower, so it is enough to > decrease attenuatnion. > >> and square it up with a Schmidt trigger. > > The problem is that I have no fast enough 3.3V CMOS trigger, > so I decided to use a squaring circuit made of a comparator or > even of discrete elements, like this (at the third picture): > > http://www.wenzel.com/documents/waveform.html How about using a couple of diodes to clip the 6V sine signal, and then amplify the square wave with a single fast transistor, even easier. LeonArticle: 79170
Hello Simon,
You wrote:
> Please could someone explain how to implement the ATM Cell Payload
> scrambler / descrambler defined in ITU-T I.432.1 (Section 7.3.4.1)
>
> The standard / recommendation suggests a self-synchronising scrambler
> with the polynomial X^43+1.
>
> My current understanding is as shown below. However, I believe it to be
> incorrect as I cannot recover my original data from my scrambled data.
Your figures look OK.
What exactly is the behaviour.
Does it never de-scramble or only after 43 bits.
What values are used when initializing the shift register.
What is the output of the scrambler when using an all ones
or all zero string of bits and what is the output of the
descrambler if the resulting string is descrambled.
Cheers, Huub.
--
reply to hhelvooort with 2 'o's
================================================================
http://members.chello.nl/hhelvoort/
================================================================
Always remember that you are unique...just like everyone else...
Article: 79171One thing to make sure is that you're only processing the data and not the header. Has the input side reached sync state yet? If not then the descra mbler can't work yet. Or are you just testing the x43+1 function on a pure serial stream? GlennArticle: 79172
I have 6 inputs to my entity, 4 switches (integer type), one clock, one reset. And a 4 bit o/p AN0-AN3 to control the anodes of the display and Data(6:0) which represents the data fed to the seven segments. I am trying to write a program where at each positive edge of the clock, I have to pass the values of the 4 integers to the 4 seven segment displays.for example. i/p i0 goes to the rightmost seven segment and i3 goes to the left most. I have a process statement with a slower clock in my sensitivity list. Anyone has any ideas of what construct would be the best to use to pass the data from i0,i1,i2 and i3 to the seven segment displays inside the process statement? thanks -VJArticle: 79173
Hello Huub, I am just simulating a serial bit stream not actually running the scrambler / descrambler with 'real' data. I am actually simulating this in excel (spreadsheet) probably not the best way but should still work following the rules and my diagrams above. 1) I make up a serial bit stream 2) I scramble the serial bit stream (following my understanding outlined above) 3) I descramble the serial bit stream (again following my understanding outlined) 4) I compare the original serial bit stream with the output from the de-scrambler The result of 4) doesn't match, I am aware that the value that I preset the scrambler and de-scrambler with wil effect the first 43 bits but after that I should be able to see a correlation between the original serial bit stream and the output from the de-scrambler. I don't. I originally was testing my simulation using the whole 43 bits but someone told me that I could reduce the length of the shift register to make the results more clear I chose a 4 bit shift register, following the same rules but with 4 bits instead of 43 bits, should this still work? Putting a string of 1's into my 4bit version of the simulation gives me a result of 4x 1's and then a 0 pattern that is repeated. (1111 0111 1111 0111 1111 0111 1111 0111 1111 0111 1111 0111 1111 0111 1111 0111 1111 0111 etc ...) Cheers SimonArticle: 79174
Hello, I'm having a hard time fitting the two fifo's I need into my StratixI device (EPS10) because of the power of 2 requirement on the depth. Are there any fifo variants that lift this requirement? Right now we're instantiating 2 sc_fifo's within a AHDL file. (I need two 3600 word fifos which would fit, but have to use two 4096 word fifos which do not fit) I'm aware of the FIFO Partitioner, but would like to avoid this if possible. Thanks, Ken
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