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Hello All, Still more problems with FIFOs. Today I tried to use the Coregen Wizard to generate a FIFO, hoping that the generated FIFO would be better than the one in my previous post. I clicked on Project, New Source, IP. Clicked on Synchronous FIFO, Blocked Memory, 32 Width, 2048 Depth (thinking one BRAM). I have some extra package that an FAE installed so I don't know if this is available to the Web Pack crowd. I tried to run a Waveform for this generated FIFO and got a message TestBench Waveforms are not currently supported for Arch Wizard or CoreGen sources. I have seen this problem before and generated a top level design with the generated FIFO as a component. This involves some cut and paste of the component and instantiation of the VHDL FIFO code into the top level, basically re copying the entity ports, the component declaration, and the instantiation of the FIFO in the top level. You have to get rid of the word "wrapped". I'll put this code at the end. Same problem however. The Simulate Behavior Model runs OK. The Simulate Post-Place and Route VHDL Model does not. Brad Smallridge b r a d @ a i v i s i o n . c o m library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity top is port ( clk: IN std_logic; sinit: IN std_logic; din: IN std_logic_VECTOR(31 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(31 downto 0); full: OUT std_logic; empty: OUT std_logic); end top; architecture Behavioral of top is component fifotest port ( clk: IN std_logic; sinit: IN std_logic; din: IN std_logic_VECTOR(31 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(31 downto 0); full: OUT std_logic; empty: OUT std_logic); end component; begin U0 : fifotest port map ( clk => clk, sinit => sinit, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty); end Behavioral;Article: 79176
On 15 Feb 2005 08:32:52 -0800, "stockton" <simon.stockton@baesystems.com> wrote: >Hello Huub, > >I am just simulating a serial bit stream not actually running the >scrambler / descrambler with 'real' data. > >I am actually simulating this in excel (spreadsheet) probably not the >best way but should still work following the rules and my diagrams >above. > >1) I make up a serial bit stream >2) I scramble the serial bit stream (following my understanding >outlined above) >3) I descramble the serial bit stream (again following my understanding >outlined) >4) I compare the original serial bit stream with the output from the >de-scrambler > >The result of 4) doesn't match, I am aware that the value that I preset >the scrambler and de-scrambler with wil effect the first 43 bits but >after that I should be able to see a correlation between the original >serial bit stream and the output from the de-scrambler. I don't. > >I originally was testing my simulation using the whole 43 bits but >someone told me that I could reduce the length of the shift register to >make the results more clear I chose a 4 bit shift register, following >the same rules but with 4 bits instead of 43 bits, should this still >work? Yes. It won't be a very good scrambler, but it shouldn't cause a mismatch. You have a bug somewhere... Do the values in the two shift registers match? >Putting a string of 1's into my 4bit version of the simulation gives >me a result of 4x 1's and then a 0 pattern that is repeated. >(1111 0111 1111 0111 1111 0111 1111 0111 1111 0111 1111 0111 1111 0111 >1111 0111 1111 0111 etc ...) You might need to specify *where* you observed that bit pattern. Is it on the output of the first scrambler, or on the output of the descramber? Regards, AllanArticle: 79177
Hi Austin,
> Not only is the static Iccint current > 7.568 amperes at 100C, but
the
> device is clearly doing a thermal runaway (in Excel!).
The particular case you point out is not thermal runaway. But with no
cooling solution at 36 degrees ambient, the junction temperature will
be out of spec (the spreadsheet indicates this with 100+). The reality
is that anyone using 180,000 Logic Elements and 1000 I/O pins toggling
at a couple hundred Mhz will be dissipitating a lot more dynamic power
than static, and a cooling solution of some sort will be necessary
irrespective of static power.
BTW, we test our chips without heatsinks. They do not go into thermal
runway.
> It looks as if the solution is iterative, and it keeps
> trying to converge with the formula for the Iccint being exponetial
with
> T, and the T just getting hotter, and hotter ...)
This iteration is a fundamental based on the physics at work here.
Static power is made up of a few components, but at 90 nm sub-threshold
leakage is the one that dominates. This occurs because transistors
aren't really "off". This is especially true on units that come out at
the fast end of the process spread (our Worst-Case numbers... you guys
don't seem to publish worst-case numbers), since these transistors are
leakier (due to lower threshold voltages, narrower channel lengths,
etc.). This sub-threshold leakage power increases exponentially with
junction (transistor) temperature.
But junction temperature (Tj) is a function of overall power
dissipation and the cooling solution employed. Cooling solutions
(package, thermal compound, heat sink, and air flow) can be represented
in the end by a "thermal resistance" expressed in degrees/Watt. This
thermal resistance times the total power consumed gives the temperature
gradient from Ambient (surrounding air) to the Junction. The parameter
used to express this resistance is ThetaJA -- the thermal resistance
between junction and ambient.
So we have:
Power = DynamicPower + StaticPower(Tj)
Tj = Ta (ambient) + Power * ThetaJA
As you can see, solving for the junction temperature requires
iteration. Let's say you've got a chip that burns 1 W of static power
@ 25C, and is generating 3W of dynamic power (temperature insensitive).
This is a total of 4W at 25C. With no cooling solution, let's say
there is a thermal resistance of 10 degrees per Watt between the
junction (transistors) and ambient (surrounding air). Let's say the
ambient temperature is 25C.
Iteration 1: Tj = 25C (ambient)
--> Static Power is 1W
Iteration 2: Tj = 25C + 4W * 10 deg/Watt = 65C
--> Static Power is now (say) 2W
Iteration 3: Tj = 25C + 5W * 10 deg/Watt = 75C
--> Static Power is now (say) 2.3W
Iteration 4: Tj = 25C + 5.3W * 10 deg/Watt = 78C
--> Static Power is now 2.4W
Iteration 5: Tj = 25C + 5.4W * 10 deg/Watt = 79C
--> ...
As you can see, we converge on a Tj of ~80C in this hypothetical
example.
Thermal runaway occurs when the this iteration reaches a point where
the incremental amount of static power for a 1 degree change in
temperature is greater than the cooling solution's ability to dissipate
that power. For example, with a 10 degrees per Watt ThetaJA solution,
if we were to ever reach a junction temperature where the Static Power
increased by more than .1 W/deg, then the static power would increase
faster than we could dissipate and this iteration would result in an
infinite junction temperature. In practice, the chip would release the
magic smoke that keeps it working.
> Sure, when the worst case static current is less than the surge, then
> there is no "surge...."
> Sure. So if the worst case static is 6 ameres, what is the 'surge'
at
> 25C? Less than 6 amperes, but still there?
At any temperature, worst-case or typical or best-case silicon, there
is no surge current. A power supply designed to meet operating
conditions will result in succesful device power-up.
- Paul
Article: 79178"fpgawizz" <bhaskarstays@yahoo.com> wrote in message news:a26ec650d1e4f5f819b4b561d738000e@localhost.talkaboutelectronicequipment.com... >I have 6 inputs to my entity, 4 switches (integer type), one clock, one > reset. And a 4 bit o/p AN0-AN3 to control the anodes of the display and > Data(6:0) which represents the data fed to the seven segments. > > I am trying to write a program where at each positive edge of the clock, I > have to pass the values of the 4 integers to the 4 seven segment > displays.for example. i/p i0 goes to the rightmost seven segment and i3 > goes to the left most. I have a process statement with a slower clock in > my sensitivity list. Anyone has any ideas of what construct would be the > best to use to pass the data from i0,i1,i2 and i3 to the seven segment > displays inside the process statement? > > thanks > -VJ > fpgawizz, I would look at the source code that represents the demo package that comes preloaded on the Spartan III starter kit. I believe the name of the file on the Xilinx Web site is : Spartan3_starter_PROM_source.zip Within that project directory, there is a file : ./pcores/opb_7segled_v1_00_a/hdl/vhdl/userlogic.vhd There is some OPB interface stuff in there that you are probably not interested in, but there is some stuff about how someone else thought the multiplexed 7segled should work. I have a question for you. Why do you open new threads in this newsgroup to ask essentially the same question in a different way. I would think that it makes it more difficult for someone else to benefit from the "conversations" at a later date. -newmanArticle: 79179
Excuse me. Spartan 3 4 BRAMs.Article: 79180
> If you mean this one, from 14 Feb > http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.html > > that's a harder call. Are these actually the SAME numbers, (press > released twice) or has two weeks resulted in another improvement ?. I don't expect Xilinx to include these numbers. They were after all just released yesterday. > They don't quite overlay, as the Jan spec says 45%, but the Feb one is > 47%, or is that 'really the same number' to marketing ? Two seperate releases for two seperate improvements. EPE 2.0 had a up to 45% reduction vs. 1.0, and EPE 2.1 has a up to 47% reduction vs. EPE 2.0. Sorry for the up to numbers -- the results do vary a lot across process, temperature and device used. Paul Leventis Altera Corp.Article: 79181
Your inputs should be std_logic. I know it's tough for beginners to cozy up with the manipulation of strings as a solution for modeling. The IEEE libraries were sort of a kludge to address some difficult questions about modeling, making VHDL one of the most verbose languages I have seen. However this is how it was done and it's best to accept it. Your question is hard to follow. Why don't you post your code and the group can sort it out for you. "fpgawizz" <bhaskarstays@yahoo.com> wrote in message news:a26ec650d1e4f5f819b4b561d738000e@localhost.talkaboutelectronicequipment.com... >I have 6 inputs to my entity, 4 switches (integer type), one clock, one > reset. And a 4 bit o/p AN0-AN3 to control the anodes of the display and > Data(6:0) which represents the data fed to the seven segments. > > I am trying to write a program where at each positive edge of the clock, I > have to pass the values of the 4 integers to the 4 seven segment > displays.for example. i/p i0 goes to the rightmost seven segment and i3 > goes to the left most. I have a process statement with a slower clock in > my sensitivity list. Anyone has any ideas of what construct would be the > best to use to pass the data from i0,i1,i2 and i3 to the seven segment > displays inside the process statement? > > thanks > -VJ >Article: 79182
Kenneth Land wrote: > Hello, > > I'm having a hard time fitting the two fifo's I need into my StratixI device > (EPS10) because of the power of 2 requirement on the depth. > > Are there any fifo variants that lift this requirement? > > Right now we're instantiating 2 sc_fifo's within a AHDL file. (I need two > 3600 word fifos which would fit, but have to use two 4096 word fifos which > do not fit) > > I'm aware of the FIFO Partitioner, but would like to avoid this if possible. Would it be thinkable to have multiple FIFOs behind each other ? EG a 2048 & 1024 & 512 ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 79183
Austin, I am an engineer. I do not knowingly put my name on a spec that could lead to system failures. When I say we do not have a power up surge, and that users only need to size their power supply to meet the operating requirements of the chip, I mean it. This is based on the data we have measured over a variety of conditions and ordering for power supply ramp up. > In denial, huh? Are you this annoying in real life? You thought you had a big advantage on this in-rush business (which was overblown anyway). You do not have an advantage here. Get over it and find something else to harp on. Paul Leventis Altera Corp.Article: 79184
Hi Peter, Ah! I'm being tag teamed! :-) > If they are prepared to back them up, > and to guarantee them. We guarentee all our specs. That is why we start with conservative estimates, and tighten the specs over time. You see this with our static power data. And you see this with our maximum Fmax specs. It is how we do things. This sucks for marketing, but it means our customer designs work. I can't expect you to stop liberally interpreting our specs. But I think we should all draw the line at questioning whether either company is cooking the numbers. > It is, however, just a little strange that their > leakage current evaporated the very moment Xilinx announced a seminar > about it. Cause and effect ? Marketing jitters? I have no control over when we release data. But I can assure you that the data collection and analysis was going on long before your seminar announcement -- it is part of our on-going characterization. Now that we have all family members out, we have the data we need to update our specs. Paul Leventis Altera Corp.Article: 79185
Brad, I've used the Synchronous FIFO's from Coregen, (block ram and distributed) and had pretty good success. ISE6.2 sp3, Modelsim PE5_8 Virtex2, Spartan III. Do you let the ISE projectnav compile all the Modelsim stuff for you from the GUI? It seemed to work OK for me. Are the FIFO inputs accessed directly from the FPGA I/O, and the timing controlled via the testbench? Has the Modelsim Resolution been set to "ps"? Any chance that there is a missing process sensitivity item missing? It is very difficult to debug a post place and route problem with Modelsim. I feel your pain. -Newman "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:1114apch4l4242c@corp.supernews.com... > Hello All, > > Still more problems with FIFOs. Today I tried to > use the Coregen Wizard to generate a FIFO, hoping > that the generated FIFO would be better than the > one in my previous post. > > I clicked on Project, New Source, IP. Clicked > on Synchronous FIFO, Blocked Memory, > 32 Width, 2048 Depth (thinking one BRAM). > > I have some extra package that an FAE installed > so I don't know if this is available to the Web Pack > crowd. > > I tried to run a Waveform for this generated FIFO > and got a message TestBench Waveforms are not > currently supported for Arch Wizard or CoreGen > sources. > > I have seen this problem before and generated a > top level design with the generated FIFO as a > component. This involves some cut and paste > of the component and instantiation of the VHDL > FIFO code into the top level, basically re copying > the entity ports, the component declaration, and > the instantiation of the FIFO in the top level. You > have to get rid of the word "wrapped". I'll > put this code at the end. > > Same problem however. The Simulate Behavior > Model runs OK. The Simulate Post-Place and > Route VHDL Model does not. > > Brad Smallridge > b r a d @ a i v i s i o n . c o m > > > > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > -- Uncomment the following lines to use the declarations that are > -- provided for instantiating Xilinx primitive components. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity top is > port ( > clk: IN std_logic; > sinit: IN std_logic; > din: IN std_logic_VECTOR(31 downto 0); > wr_en: IN std_logic; > rd_en: IN std_logic; > dout: OUT std_logic_VECTOR(31 downto 0); > full: OUT std_logic; > empty: OUT std_logic); > end top; > > architecture Behavioral of top is > > component fifotest > port ( > clk: IN std_logic; > sinit: IN std_logic; > din: IN std_logic_VECTOR(31 downto 0); > wr_en: IN std_logic; > rd_en: IN std_logic; > dout: OUT std_logic_VECTOR(31 downto 0); > full: OUT std_logic; > empty: OUT std_logic); > end component; > > > begin > > U0 : fifotest > port map ( > clk => clk, > sinit => sinit, > din => din, > wr_en => wr_en, > rd_en => rd_en, > dout => dout, > full => full, > empty => empty); > > end Behavioral; > > >Article: 79186
Allan, Thanks for the responce, you may need to view this as plain text (in notepad or something) so that all the numbers line up. ************************************************************************ A - Original Data B - 4 bit Shift Register (B1 = C^, B2 = B1^, B3 = B2^, B4 = B3^) C - Scrambled Data (C = A^ + B4^) D - 4 bit Shift Register (D1 = C^, B2 = B1^, B3 = B2^, B4 = B3^) E - Un Scrambled Data (E = C^ + D4^) ^ - previous iteration + - XOR A B C D E - 1234 - 1234 - 0 0000 1 0000 0 + 0 = 0 0000 1 0000 1 + 0 = 1 0000 0 + 0 = 0 1 1000 1 + 0 = 1 1000 1 + 0 = 1 0 1100 1 + 0 = 1 1100 1 + 0 = 1 1 1110 0 + 0 = 0 1110 1 + 0 = 1 1 0111 1 + 0 = 1 0111 1 + 0 = 1 1 1011 1 + 1 = 0 1011 0 + 1 = 1 0 0101 1 + 1 = 0 0101 1 + 1 = 0 0 0010 0 + 1 = 1 0010 0 + 1 = 1 1 1001 0 + 0 = 0 1001 0 + 0 = 0 1 0100 1 + 1 = 0 0100 1 + 1 = 0 1 0010 1 + 0 = 1 0010 0 + 0 = 0 0 1001 1 + 0 = 1 1001 0 + 0 = 0 0 1100 0 + 1 = 1 1100 1 + 1 = 0 1 1110 0 + 0 = 0 1110 1 + 0 = 1 ********************************************************** I think that I have included enough iteration to expect the original data to been identified in the un-scrambled stream. However this is not evident. Any thoughs on my method? Cheers SimonArticle: 79187
Brad, a synchronous FIFO design ( same clock for write and read) implemented in a Xilinx dual-ported BlockRAM is really trivial: Two binary counters and a comparator plus a simple circuit to distinguish between FULL and EMPTY. Even the partial full calculations can easily be done in binary. I would design your FIFO as four parallel BlockRAMs, each 8 bit wide. BTW, you never mentioned the clock rate. All the difficulty and trickiness of FIFO design comes when the two clocks are asynchronous, and you need Gray counters etc. Peter Alfke, Xilinx ApplicationsArticle: 79188
On 15 Feb 2005 09:42:41 -0800, "simon.stockton@baesystems.com" <simon.stockton@baesystems.com> wrote: >Allan, > >Thanks for the responce, you may need to view this as plain text (in >notepad or something) so that all the numbers line up. > > >************************************************************************ >A - Original Data >B - 4 bit Shift Register (B1 = C^, B2 = B1^, B3 = B2^, B4 = B3^) >C - Scrambled Data (C = A^ + B4^) >D - 4 bit Shift Register (D1 = C^, B2 = B1^, B3 = B2^, B4 = B3^) >E - Un Scrambled Data (E = C^ + D4^) >^ - previous iteration >+ - XOR > >A B C D E >- 1234 - 1234 - > >0 0000 >1 0000 0 + 0 = 0 0000 >1 0000 1 + 0 = 1 0000 0 + 0 = 0 >1 1000 1 + 0 = 1 1000 1 + 0 = 1 >0 1100 1 + 0 = 1 1100 1 + 0 = 1 >1 1110 0 + 0 = 0 1110 1 + 0 = 1 >1 0111 1 + 0 = 1 0111 1 + 0 = 1 >1 1011 1 + 1 = 0 1011 0 + 1 = 1 >0 0101 1 + 1 = 0 0101 1 + 1 = 0 >0 0010 0 + 1 = 1 0010 0 + 1 = 1 >1 1001 0 + 0 = 0 1001 0 + 0 = 0 >1 0100 1 + 1 = 0 0100 1 + 1 = 0 >1 0010 1 + 0 = 1 0010 0 + 0 = 0 >0 1001 1 + 0 = 1 1001 0 + 0 = 0 >0 1100 0 + 1 = 1 1100 1 + 1 = 0 >1 1110 0 + 0 = 0 1110 1 + 0 = 1 You've messed up your pipeline delays quite badly. The conceptual model all operates without pipeline delays, e.g. there is no delay through the xor gates. I expected to see your table 'flat' across the top, like this: >A B C D E >- 1234 - 1234 - > >0 0000 0 + 0 = 0 0000 0 + 0 = 0 >1 0000 1 + 0 = 1 0000 1 + 0 = 1 >1 1000 1 + 0 = 1 1000 1 + 0 = 1 >1 1100 1 + 0 = 1 1100 1 + 0 = 1 >0 1110 0 + 0 = 0 1110 0 + 0 = 0 >1 0111 1 + 1 = 0 0111 0 + 1 = 1 >1 0011 1 + 1 = 0 0011 0 + 1 = 1 >1 0001 1 + 1 = 0 0001 0 + 1 = 1 >0 0000 0 + 0 = 0 0000 0 + 0 = 0 >0 0000 0 + 0 = 0 0000 0 + 0 = 0 which, as you can see, does indeed recover the original data. The extra delay you added changed the Tx shift register from 4 bits to 5 bits, which then doesn't match the Rx. Of course, a real design in an FPGA would have pipeline delays, but these are normally inserted in a manner that doesn't change the functionality! ... at least I think that's what you've done. I didn't look at it too closely. Regards, AllanArticle: 79189
>From my testbench i can give you the following results to help isolate if the problem is with the scrambler or desccrambler. input scramble 00000001 00000001 00118000 00ee7fff 00076a6a fff897a5 696a6a6a 96959578 Note first bytes are ignored (header). Next 43 bits are unchanged (inital state of scrambler was all 0's). Output is inverted as per ITU-T I.432Article: 79190
Hi Ken, I've done this before by writing my own fifo using the altsyncram megafunction. altsyncram has a parameter MAXIMUM_DEPTH which allows non-power-of-2 depths. Adding single-clock FIFO functionality (read and write ptr management at a minimum) shouldn't be more than 20 lines of HDL. You can go one step further and implement "stacked" memory yourself, but then you have to write the muxing yourself, which altsyncram does implicitly with MAXIMUM_DEPTH. -- PeteArticle: 79191
Paul, nice tutorial. You are a good teacher! But let's look at the so-called reduction of 47% in the Altera leakage current specs: Here is the change in worst-case 85 degree static power (the only static parameter that really matters) from the previous 2.0 to the new 2.1: 2S15 increased (!) by 48 % 2S30 reduced by 1 % 2S60 increased by 4 % 2S90 unchanged 2S130 decreased by 6 % 2S180 decreased by 14 % It takes creative marketing to call that a 47% reduction in leakage current ! Peter AlfkeArticle: 79192
her is my code
entity Display is
Port ( clk : in std_logic;
rst : in std_logic;
d0 : in integer range 0 to 9;
d1 : in integer range 0 to 9;
d2 : in integer range 0 to 9;
d3 : in integer range 0 to 9;
seven_seg : out std_logic_vector(6 downto 0);
AN3 : inout std_logic;
AN2 : inout std_logic;
AN1 : inout std_logic;
AN0 : inout std_logic);
end Display;
architecture Behavioral of Display is
component countdecoder is
port( count: in integer range 0 to 9;
seven_seg : out std_logic_vector(6 downto 0));
end component;
signal count : integer range 0 to 9;
signal CTR : std_logic_vector(12 downto 0);
begin
-- make a copy of the decoder
decoder1: countdecoder port map(count => count, seven_seg => seven_seg);
Display_left_to_right: process(rst,clk)
begin
if rst = '1' then
count <= 0;
AN3 <= '0';
AN2 <= '0';
AN1 <= '0';
AN0 <= '0';
elsif clk'event and clk = '1' then
if (ctr = "0000000000000") then
if AN3 = '0' then
AN3 <= '1';
count <= d3;
AN0 <= '0';
elsif AN2 = '0' then
AN2 <= '1';
count <= d2;
AN1 <= '0';
elsif AN1 = '0' then
AN1 <= '1';
count <= d1;
AN2 <= '0';
elsif AN0 = '0' then
AN0 <= '1';
count <= d0;
AN3 <= '0';
end if;
end if;
ctr <= ctr + "0000000000001";
if (ctr > "1000000000000") then
ctr <= "0000000000000";
end if;
end if;
end process Display_left_to_right;
end Behavioral;
The component is a decoder that just spits out data for various integer
input values. the CTR is to delay the process block so the segments can be
refreshed at a slower rate.I could have used a slower clock in my process
statement i guess.
pls advise
Article: 79193Trivial for you perhaps. But I have done two designs now with the same problem. They model OK under Behavior models but the Post Place and Route Models do not work. The Clock Rate is a good question. Going back to the Waveform and clicking on the Rescale Timing button, I get these numbers: Clock High Time 10ns Clock Low Time 10ns Input Setup Time 5ns Output Valid Delay 5ns Offset 0ns If there is any documentation about what these all mean please point it out to me. The only thing I understand fully is the Clock High and Clock Low times. 50MHz is close to my target application. My devices are Spartan 3s. Brad Smallridge b r a d @ a i v i s i o n . c o mArticle: 79194
"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> schrieb im Newsbeitrag news:cusq4p$u8r$1@news.dialog.net.pl... > > and square it up with a Schmidt trigger. > > The problem is that I have no fast enough 3.3V CMOS trigger, What is fast enough?? AFAIK those 74LVC/LVT 14 are quite fast. Regards FalkArticle: 79195
Hi Simon,
I noticed something unexpected in the B shift register.
> ************************************************************************
> A - Original Data
> B - 4 bit Shift Register (B1 = C^, B2 = B1^, B3 = B2^, B4 = B3^)
> C - Scrambled Data (C = A^ + B4^)
> D - 4 bit Shift Register (D1 = C^, B2 = B1^, B3 = B2^, B4 = B3^)
> E - Un Scrambled Data (E = C^ + D4^)
> ^ - previous iteration
> + - XOR
>
> A B C D E
> - 1234 - 1234 -
>
> 0 0000
> 1 0000 0 + 0 = 0 0000
> 1 0000 1 + 0 = 1 0000 0 + 0 = 0
> 1 1000 1 + 0 = 1 1000 1 + 0 = 1
> 0 1100 1 + 0 = 1 1100 1 + 0 = 1
> 1 1110 0 + 0 = 0 1110 1 + 0 = 1
> 1 0111 1 + 0 = 1 0111 1 + 0 = 1
> 1 1011 1 + 1 = 0 1011 0 + 1 = 1
> 0 0101 1 + 1 = 0 0101 1 + 1 = 0
> 0 0010 0 + 1 = 1 0010 0 + 1 = 1
> 1 1001 0 + 0 = 0 1001 0 + 0 = 0
> 1 0100 1 + 1 = 0 0100 1 + 1 = 0
> 1 0010 1 + 0 = 1 0010 0 + 0 = 0
> 0 1001 1 + 0 = 1 1001 0 + 0 = 0
> 0 1100 0 + 1 = 1 1100 1 + 1 = 0
> 1 1110 0 + 0 = 0 1110 1 + 0 = 1
> **********************************************************
This is what I had expected:
0 0000
0 + 0 = 0
1 0000 0000
1 + 0 = 1 1 + 0 = 1
1 1000 1000
1 + 0 = 1 1 + 0 = 1
1 1100 1100
1 + 0 = 1 1 + 0 = 1
0 1110 1110
0 + 0 = 0 0 + 0 = 0
1 0111 0111
1 + 1 = 0 0 + 1 = 1
1 0011 0011
1 + 1 = 0 0 + 1 = 1
1 0001 0001
1 + 1 = 0 0 + 1 = 1
0 0000 0000
0 + 0 = 0 0 + 0 = 0
0 0000 0000
0 + 0 = 0 0 + 0 = 0
1 0000 0000
1 + 0 = 1 1 + 0 = 1
1 1000 1000
1 + 0 = 1 1 + 0 = 1
1 1100 1100
1 + 0 = 1 1 + 0 = 1
0 1110 1110
0 + 0 = 0 0 + 0 = 0
0 0111 0111
0 + 1 = 1 1 + 1 = 0
1 1111 1011
1 + 1 = 0 1 + 0 = 1
Cheers, Huub.
--
reply to hhelvooort with 2 'o's
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Article: 79196> I also create a edk core from the wizard and take a look in the mpd file. > I see in the mpd file under ## Generics for vhdl or Pa... > > PARAMETER C_FAMILY = virtex2p, DT = STRING > > This is probably what they need to the ncg build error ... And again i'm not > shure > Nope look at the additionnal step I posted today a few hour ago. It now builds fine. But it doesn't seem to work ... Has someone ever managed to use it ? SylvainArticle: 79197
> Do you let the ISE projectnav compile all the Modelsim stuff for you from > the GUI? YES. > Are the FIFO inputs accessed directly from the FPGA I/O, and the timing > controlled via the testbench? YES. Well, as much as my previous post suggest with a Top level module. > Has the Modelsim Resolution been set to "ps"? AHA! It was set to ns, which I guess is the default, but for grins I set it for us and voila! the post place and route does work. Apparently there are some setups in there that take longer than 5ns. Why I didn't see any Warnings baffles me because I was getting them when my settings were at the default 2ns setup. Thank you. Thank you. > Any chance that there is a missing process sensitivity item missing? Would that not effect the Behavior model as well? > It is very difficult to debug a post place and route problem with > Modelsim. I feel your pain. What is the best software for post place and route problems? Thanks again, Brad Smallridge b r a d @ a i v i s i o n . c o mArticle: 79198
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:1114hkl50qr0gc0@corp.supernews.com... >> Do you let the ISE projectnav compile all the Modelsim stuff for you from >> the GUI? > > YES. > >> Are the FIFO inputs accessed directly from the FPGA I/O, and the timing >> controlled via the testbench? > > YES. Well, as much as my previous post suggest with a Top level module. > >> Has the Modelsim Resolution been set to "ps"? > > AHA! It was set to ns, which I guess is the default, but for grins I set > it for us > and voila! the post place and route does work. Apparently there are some > setups in there that take longer than 5ns. Why I didn't see any Warnings > baffles > me because I was getting them when my settings were at the default 2ns > setup. I would think that you only get warnings when the data transition falls within the setup_hold window. > > Thank you. Thank you. > >> Any chance that there is a missing process sensitivity item missing? > > Would that not effect the Behavior model as well? Typically, the synthesis tool will issue a warning, and insert the missing item in the sensitivity list. This results in a mismatch between the behaverial and post place and route sims. I believe this to be my number one reason why my simulations mismatch. > >> It is very difficult to debug a post place and route problem with >> Modelsim. I feel your pain. > > What is the best software for post place and route problems? Perhaps the dataflow option from Modelsim. I'm too cheap to buy it, so I cannot tell you much about it. > > Thanks again, > > Brad Smallridge > b r a d @ a i v i s i o n . c o m > >Article: 79199
Paul, OK. I'll reserve my judgement until I see the scope pictures. No more comments on power ON surge. And, yes, I have been told that I am extremely annoying 'in real life.' Usually by people that are trying to divert attention from real issues. Austin Paul Leventis wrote: > Austin, > > I am an engineer. I do not knowingly put my name on a spec that could > lead to system failures. When I say we do not have a power up surge, > and that users only need to size their power supply to meet the > operating requirements of the chip, I mean it. This is based on the > data we have measured over a variety of conditions and ordering for > power supply ramp up. > > >>In denial, huh? > > > Are you this annoying in real life? > > You thought you had a big advantage on this in-rush business (which was > overblown anyway). You do not have an advantage here. Get over it and > find something else to harp on. > > Paul Leventis > Altera Corp. >
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