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"John_H" <johnhandwork@mail.com> wrote in message news:fOXHd.15$ML4.350@news-west.eli.net... > Since your synthesis shows 15 LUTs used, I expect that the sum is the > cascade of 2 9-bit adders. ... sorry: Two 8-bit adders with 9-bit results.Article: 77951
Hi, Supposing a top-level design was comprised of module A,module B,module C & module D. Now I wanna apply modular design method to the design. In the top-level design synthesis process,only module A & module B synthesized as black boxes and module C & module D expanded.Then apply the modular design flow.Is this modular design method fasible? Thanks, fireArticle: 77952
> I have a legacy design for an XC4000 that I'm trying to program through the X-checker pod, and this has not worked under Windows 2000 or XP. Windows 98 works fine. What can I do to get this to work under the new OS? I'm not familiar with the X-checker pod, but have you tried running the program as administrator? The reason I ask is because the main difference between windows 98 and 2000/XP is that windows 98 is built on top of a DOS core, whereas 2000/XP are based on an NT core. AFAIU, the result of this is that in windows XP/2000 you can have permissions problems with the serial/parallel ports - I have hit a similar problem before, trying to program COP8 microcontrollers. (I'm assuming that the X-checker cable is something that plugs into a serial or parallel port - you could also check that no other program is trying to use the port at the same time if this is the case) To confirm whether it is purely a software issue, I guess you could put a 'scope on the outputs and confirm whether or not there's any signals going through. JeremyArticle: 77953
Kryten wrote: > "logjam" <grant@cmosxray.com> wrote in message > news:1106249347.233017.138400@f14g2000cwb.googlegroups.com... > >I am trying reproduce a Macintosh 128k using CMOS parts. It has some > > 16R4, 16R8, and 16L8 PALs. If you could give me any advice about how I > > should "learn" the logic in these that would be GREAT! Maybe a method > > of bit twiddling all the inputs to see what happens? The 16L8 should > > be simple, but that is only one of the 6. I have signal names and a > > schematic, but the internal design of the 'R' chips scares me. :) A company in Brazil did what you suggested and it took them a few months. I did a new design from publicly available sources plus the schematic and it only took me three days and the result was faster than the original (see http://www.lsi.usp.br/~jecel/mac512.html for more details). My version depended on faster memories than what the 128K Mac used, but it would be equally easy to come up with a compatible timing. > Hmm. I think that noting the connections to the CPU will provide some useful > clues. Is the circuit diagram online? http://www.digibarn.org/collections/diagrams/mac-512klogicboard/index.html > I have a copy of the 3rd edition of "The Programmable Logic Handbook" by > MMI. > Antique technology but since it was from the dawn of PLD days it has very > useful code examples. Like connecting the 68K to Zilog peripheral chips. I > can scan the notes that you want. That level of detail is nice, but not really needed for this job. > MikeJ of FPGA arcade is resurrecting the Atari ST, so some fundamentals may > match the Mac. Pretty much. My own Merlin 2 was my model, for example. The Amiga would be an entirely different story, however. -- JecelArticle: 77954
Hi Roger, > Compared with a normal Stratix, is a HardCopy version immune to SEUs? The short answer to your question is that yes, a HardCopy device will have no susceptability to SEUs affecting the "programming" of the device. Configuration memory cells are replaced with hard-wired connections, thus eliminating any possibility that the programming of the device is upset by a particle collision. Memory storage cells are still present in the block memories, so I imagine that some SEU is possible in the *state* of the chip, as it is with any ASIC. Regards, Paul Leventis Altera Corp.Article: 77955
On 19 Jan 2005 17:29:13 -0800, "Marc Randolph" <mrand@my-deja.com> wrote: >Georgi Beloev wrote: >> Hi all, >> >> I'm designing a system in which a 4-bit + clock LVDS point-to-point >bus >> has to connect two FPGAs. The two FPGAs are on two different >boards--one >> is on a mainboard and the other is on a plug-in board. >> >> What kind of board-to-board connector is recommended for high-speed >> (~400 Mbps) LVDS signals? Connector parameters to look for? Signal >> integrity issues? Board layout with regard to the connectors? Rules >of >> thumb? > >Howdy Georgi, > >I hate to say that it doesn't matter, but in the grand scheme of >things, the type or style of the connector is not of huge importance at >that speed, as long as one pin isn't massively longer than another >(which occurs with some types of right angle connectors). We run many >times that speed using the worst connector you can imagine. > >Much more important is the stuff that Brad mentioned: keep _p/_n pair >trace length the same and routed as a diff pair into and out of the >connector - and routed against a ground plane if possible. Give >yourself a ground pin next to each pair within the connector. >Have fun, > > Marc I'll mostly agree with you. We are running three LVDS pairs (200MHz) plus power over standard 6' shielded Cat5 patch cords with RJ45 jacks at each end. We were very careful with the PCB layouts to run the pairs together, to match the lengths, and to avoid vias. Works fine. BTW, we use the common-mode filter termination (see figure 3.3 in the National Semiconductor LVDS Owner's Manual). ================================ Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 77956
"Jecel" <jecel@merlintec.com> wrote in message news:1106269932.965110.285140@f14g2000cwb.googlegroups.com... > > A company in Brazil did what you suggested and it took them a few > months. I did a new design from publicly available sources plus the > schematic and it only took me three days and the result was faster than > the original (see http://www.lsi.usp.br/~jecel/mac512.html for more > details). Very impressive. Might we get to see your equations? Pretty please? :-) > http://www.digibarn.org/collections/diagrams/mac-512klogicboard/index.html Interesting. Diagram not great (jpg artefacts). I'd like to redraw it. >> I have a copy of the 3rd edition of "The Programmable Logic Handbook" > That level of detail is nice, but not really needed for this job. Well, it's a nice book and I wondered if other people (esp. students) might benefit.Article: 77957
I guess you already said something about not keeping the resources at the time, but do you by any chance have Apple's Pal equations now? Know how I can find them or what to search for? I've been talking about this over at avrfreaks http://www.avrfreaks.com/index.php?name=PNphpBB2&file=viewtopic&t=26198 and someone said he once had all 6 chips in his computer. Grant Jecel wrote: > A company in Brazil did what you suggested and it took them a few > months. I did a new design from publicly available sources plus the > schematic and it only took me three days and the result was faster than > the original (see http://www.lsi.usp.br/~jecel/mac512.html for more > details). My version depended on faster memories than what the 128K Mac > used, but it would be equally easy to come up with a compatible timing. > > > Hmm. I think that noting the connections to the CPU will provide some > useful > > clues. Is the circuit diagram online? > > http://www.digibarn.org/collections/diagrams/mac-512klogicboard/index.html > > > I have a copy of the 3rd edition of "The Programmable Logic Handbook" > by > > MMI. > > Antique technology but since it was from the dawn of PLD days it has > very > > useful code examples. Like connecting the 68K to Zilog peripheral > chips. I > > can scan the notes that you want. > > That level of detail is nice, but not really needed for this job. > > > MikeJ of FPGA arcade is resurrecting the Atari ST, so some > fundamentals may > > match the Mac. > > Pretty much. My own Merlin 2 was my model, for example. The Amiga would > be an entirely different story, however. > > -- JecelArticle: 77958
Is there a simple denotation in VHLD of "and" logic between one bit and a
vector of bits? The single bit will be extended to the length of
the vector first, then a bit-by-bit "and" logic is perform. For example,
I have single bit A_OE, B_OE, C_OE and D_OE, and vectors A, B, C, D,
I want to do (A_OE and A) or (B_OE and B) or (C_OE and C) or (D_OE and D).
Thank you.
vax, 9000
Article: 77959Just out of curiosity, is it possible to pipeline successive reads and writes to SDRAM? For example, I want to send a read command and then a write command, where the memory address will be different for reads and writes. After the necessary latency after the first read command, will there also be a delay between when I clock in data from that read and when I can start outputting write data?Article: 77960
I haven't seen such declaration before in generic C or C++.....
BluetoothReceiver::BluetoothReceiver()
: bandpassFilter(BPLENGTH), //---?
differentiatorFilter(DIFFLENGTH) //---?
{
Thanks.
"Mark McDougall" <msmcdoug@no.spam.iinet> wrote in message
news:41f01a3a$0$31122$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
> Fat Cat wrote:
>
> > I am a bit confused. I have never seen such syntax even though I read a
> > lot of C++ codes.
>
> I am a bit confused. I don't know how you could've read more than 1 or 2
> examples of C++ code without coming across everything in your example?!?
>
> Regards,
>
> --
> | Mark McDougall | "Electrical Engineers do it
> | <http://to be announced> | with less resistance!"
Article: 77961Hi vax, 9000, > Is there a simple denotation in VHLD of "and" logic between one bit and a > vector of bits? The single bit will be extended to the length of > the vector first, then a bit-by-bit "and" logic is perform. For example, > I have single bit A_OE, B_OE, C_OE and D_OE, and vectors A, B, C, D, > I want to do (A_OE and A) or (B_OE and B) or (C_OE and C) or (D_OE and D). Can't think of anything built-in or in the standard packages, but assuming A, B, C and D are of equal length, how about for i in A'LOW to a'HIGH loop result(i) <= (A(i) and A_OE) or (B(i) and B_OE) ... end loop; Can't think of anything shorter save writing a function myself. Best regards, BenArticle: 77962
This is simple to achieve using the for n in m loop type structure.Simply loop along the length of the bit vector performing the #and# at each loop iteration.Article: 77963
"Peter" <pdstroud@gmail.com> wrote in message
news:1106228263.951310.203610@z14g2000cwz.googlegroups.com...
> Which part, in particular, is confusing?
>
> "BluetoothReceiver::BluetoothReceiver() : bandpassFilter(BPLENGTH),
> differentiatorFilter(DIFFLENGTH) {...}" is the default constructor. The
> stuff after the ":" is the initialization list and may be used to
> initialize member objects or base class portions of a derived object.
>
> My guess is that bandpassFilter and differentiatorFilter are both
> contained by BluetoothReceiver and are initialized with BPLENGTH and
> DIFFLENGTH upon construction.
>
This is multiple inheritance and the code snippet is from the top of the
code definition of the BluetoothReceiver class constructor.
The colon operator is the syntax used to call the appropriate base class
constructor and this case two are being called which is multiple inheritance
instead of normal, single inheritance.
Ken
Article: 77964
"vax, 9000" <vax9000@gmail.com> wrote in message
news:cspqv4$hkm$1@charm.magnus.acs.ohio-state.edu...
> Is there a simple denotation in VHLD of "and" logic between one bit
and a
> vector of bits? The single bit will be extended to the length of
> the vector first, then a bit-by-bit "and" logic is perform. For
example,
> I have single bit A_OE, B_OE, C_OE and D_OE, and vectors A, B, C, D,
> I want to do (A_OE and A) or (B_OE and B) or (C_OE and C) or (D_OE
and D).
> Thank you.
>
> vax, 9000
>
You could try doing
subtype T is STD_LOGIC_VECTOR(A'RANGE);
A and T'(others => A_OE)
It might work,
Or even
A and (A'RANGE => A_OE)
though I think the compiler will then complain that it doesn't
know the type of the aggregate,
regards
Alan
--
Alan Fitch
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The contents of this message may contain personal views which are not
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Article: 77965Hi,Salvatore, First,download the newest version of Xapp290,find out the nmc file for your FPGA type. You can easily distinguish them by their name. Remember,each nmc file serves for one FPGA FAMILY! As to the ucf constraints for busmacros,read xapp290 document,in appendix,there is explanation for it. That's to say,do not constraint busmacro in floorplanner or fpga-editor,instead,add syntax manually in your ucf file! Remember,take care of your signal flow direction,keep in mind the busmacro should exactly straddle the dividing line of the communicating modules(i.e.,boundary of two modules is X15 for leftside module,X16 for rightside module,then you should place your busmacro X12Yy. In this way,busmacros should occupy X12,X14,X16,X18 four columns,two columns in leftside module,two colunms in the rightside module). good luck! If not clear,welcome discuss with me by email. cheers, jeffsenArticle: 77966
Dear All, I am looking into the possibility of running nested interrupts. Effectively what I have at the moment is a single thread of control and an external non critical irpt which does some comms stuff. I now want to add a critical interrupt handler but what would happen if I was executing my non-crit handler and the crit irpt went off. I am under the impression that I need to complete my handler before the other one would start. There is a query like this on the Xolinx web page but it is a one sentence, non-helpful answer. Thanks In AdvanceArticle: 77967
If you have a netlist which I am guessing is mainly ANDs, ORs or even technology specific elements. You can model each gate/element to an equivalent in the FPGA. We do this kind of thing for clients from time to time. More often the biggest issues come in ASIC designs that use a lot of clocks and have a lot clock boundary crossing. When you get into this type of design you need to be careful of how it will work in the FPGA. It isn't impossible but care is needed in designs with large numbers of clocks. As a side point it is worth looking at Virtex4 for this kind prototyping of as the family has features aimed at designs with lots of clocks and even clock boundary crossing assistance. If at all possible when starting a new design try structure the design to be friendly to both types of target. If do it early enough is can be a painless process and does not cost ASIC resource if done properly. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "gretzteam" <david.lamb@gmail.com> wrote in message news:1106241119.166667.167990@z14g2000cwz.googlegroups.com... > Hi, > We are currently using virtexIIpro and virtex4 fpga to prototype a dsp > processor. All the code is synthesizable verilog and we are using > Xilinx ISE to do synthesis and place and route. Everything works fine > and the processor runs at full speed (50Mhz). However, this is only > good for functionnal verification on the bench. The ASIC flow and the > FPGA flow are very different so the actual gates in the FPGA are > different than what will be on the ASIC. For example, we can't use the > FPGA to verify the test vectors and scan chains that the test engineer > is working on. > > Is it possible to prototype the EXACT same gates that will be in the > ASIC? We use Synopsys Design Compiler to generate the ASIC gates. > Basically is there a way to take the gates generated by Design > Compiler, and map them in the FPGA? We don't really care if this runs > slower, but it would allow the test engineer to start working on all > the test vectors before we receive silicon. > > Thank you very much, > David >Article: 77968
Yes, it would seem to be a software issue, as nothing goes over the serial port. I have tried a utility such as userport, which allows the old inb/outb commands in Win2000, but to no avail. I was indeed logged inn as an administrator... I was really hoping that Xilinx put something out that corrected this, but it seems that Xchecker is meant to wither and die away.Article: 77969
dear In EDK6.3 XPS, microblaze netlist generation, Following 'out of memory' error occurred. Memory is 3GB, (sufficient enough, i think) Someone who has experience like me, how did you manage this problem? ---------------------------------------------------------- ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 2044740 kb. Memory problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround. To troubleshoot or remedy the problem, first: Try increasing your system's RAM. Alternatively, you may try increasing your system's virtual memory or swap space. If this does not fix the problem, please try the following: Search the Answers Database at support.xilinx.com to locate information on this error message. If neither of the above resources produces an available solution, please use Web Support to open a case with Xilinx Technical Support off of support.xilinx.com. As it is likely that this may be an unforeseen problem, please be prepared to submit relevant design files if necessary. make: *** [implementation/microblaze_0_wrapper.ngc] Error 19 --------------------------------------------------------- thx regardsArticle: 77970
I once saw a Classic Mac for £10. I'd have bought it for reverse engineering purposes but I'm desperately trying to reduce the mass of junk I own. Out of curiosity, can the CRT and PSU be replaced by a PC monitor and PSU? That way I would only need the main board which I presume would be fairly small and light. I could justify keeping that much. Knowing Apple, they probably went their own way on video...Article: 77971
Hi Doug, I've had this problem before. The trick is to add a path-based assigment. See this thread: http://tinyurl.com/683qe So for your mesher, add the path * -> * to the LogicLock region. Any fitter-created nodes will then be placed inside the LL region. I think Quartus 4.1 has a bug where having only the path-based assignment together with outputs defined as virtual pins causes the LL region to be ignored. To get around this I include the node assignment (which you've done by dragging the mesher onto the region) as well as the path assignment. I'd like to think Quartus 4.2 has fixed this so that only the path assignment is required, but I haven't tried it yet on that. As for virtual IOs, these disappear when they .vqm is instantiated in an upper level and become wires. HTH, -- PeteArticle: 77972
Thanks. And how much does Synplify cost?Article: 77973
An answer not posted to the group: Macros are not components that can be instantiated in HDL. Macros are only available in ECS, the Xilinx schematic entry tool. One way to see how Xilinx implements the ADD8 macros is to create the macro using ECS and then looking at the HDL output of ECS (*.VHF file generated after synthesis).Article: 77974
I don't have experience with this platform but from the information you provided, I would conclude it is a memory conflict. Why: The error message indicates that it could be from either an 'out of memory condition' or a 'memory conflict'. You have stated that you have set memory at 3 Gb. In the memory message it said that it is using 1.95 Gb. Therefore I would conclude it is some kind of memory conflict sense it is using less memory than you have allocated. Have you checked for a conflict? Hur wrote: > dear > > In EDK6.3 XPS, microblaze netlist generation, > > Following 'out of memory' error occurred. > Memory is 3GB, (sufficient enough, i think) > > Someone who has experience like me, how did you manage this problem? > > ---------------------------------------------------------- > ERROR:Portability:3 - This Xilinx application has run > out of memory or has encountered a memory conflict. > Current memory usage is 2044740 kb. Memory problems > may require a simple increase in available system > memory, or possibly a fix to the software or a special > workaround. To troubleshoot or remedy the problem, > first: Try increasing your system's RAM. > Alternatively, you may try increasing your system's > virtual memory or swap space. If this does not fix > the problem, please try the following: Search the > Answers Database at support.xilinx.com to locate > information on this error message. If neither of the > above resources produces an available solution, please > use Web Support to open a case with Xilinx Technical > Support off of support.xilinx.com. As it is likely > that this may be an unforeseen problem, please be > prepared to submit relevant design files if necessary. > > make: *** [implementation/microblaze_0_wrapper.ngc] > Error 19 > --------------------------------------------------------- > > thx > > regards
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