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Hello, I'm looking for the XAPP769 that is referenced from other application notes. But I can't find it on xilinx site anywhere and not much reference from google either ... Can some one tell me where it's hidden ? Thanks, SylvainArticle: 77201
Hi all ! I am trying to implement a filter in a spartan III. I have several multipliers to put inside :-( Is it possible to tell the compiler to use the mult18x18 elements, and then, when all are used, to implement multipliers using for example LUT ?? Or to choose what kind of multipliers to implement by hand ? Because I simply use y <= a*b and this implements mult18x18. But there only are 16 in a 400k gates spartan ! So there's not enough mult18x18, but I only use a few percent of the slices... Thank you in advance ! SamArticle: 77202
Jae, I would recommend the FSL connections, as they make good point-to-point type of communication that you describe. In a separate email, I will send you a MHS file of a dual-MicroBlaze system, along with C code. You should extend this system by adding FSL interfaces to other MicroBlaze nodes in your system. Also, consult the EDK FSL and MicroBlaze documentation for information on parameterizing the FSL links and the different ways to access FSL via MicroBlaze (e.g. get, put, blocking vs. non-blocking, etc.). Also, keep in mind that each FSL connection is a one-way street, so that if you require 2-way message passing from each MB to another, this will require 2 FSL links (master being the producer side, and slave being the consumer side). Matt Hur wrote: > hello > > I am looking for the methods to set the interconnection between microblazes > (MB). > > For example of MESH, Consider 4 MBs. > > MB1 - MB2 - MB4, > MB1 - MB3 - MB4 > > Could anyone guide me to preset this interconnection ? > > Thankyou in advance > > >Article: 77203
I have been trying to get through to somebody at Altera to answer a question before ordering an Altera NIOS II/Stratix II development kit but they seem to give priority to existing customers vs. new customers. My Question Is: Some of the information I have downloaded from the Altera web site describes the kit as having EP2S30 and the technical documentation describes it as having an EP2S60. This is a deciding factor for me to order it. If I were to order one today (I need to order before the first of the year) which device would come on it? I also would like to know if the channel I go through to order the NIOS II Development Kit can I also order the Lancelot VGA board? I have read some criticisms about Xilinx's ISE compared to Altera's Quartus II. I'm not as familar with Xilinx's software tools but do they have similar products Altera's SOPC Builder? If I'm considering buying the Altera NIOS Devlopment kit is there a similar Xilinx product with about the same price tag I should be considering? Thanks, DerekSimmons at FrontierNet dot netArticle: 77204
Hi Derek, Our first Nios II/Stratix II development kits, including the one I'm working with now on my desk (coincident to your inquiry about Lancelot, I'm doing some video-related-work), feature the Stratix II 2S60ES (engineering sample) devices. As the 2S30 (non-ES) becomes available we will revise the development boards to ship with this smaller device. Our long-term plan is for the $995USD Nios II/Stratix II kits will have the 2S30, and this is why the literature you're seeing says that; however if you'd like to use the ES devices (limitations/errata available through the Altera website) we provide the larger device at the same price to compensate. As far as schedules are concerned, the 2S60ES kits are what are currently shipping; the 2S30's are scheduled to roll-out later in 2005 (we have to revise the Nios II kit software to include example designs for the 2S30 boards as well). Regarding the Lancelot cards: According to www.fpga.nl they can be ordered from AleaRep (http://www.alearep.com/) I am probably less familiar with the Xilinx tools compared to you (haven't used ISE in several years). However, it is no secret that FPGA-based processors and the tools to build such systems are a new technology; our tools have been around longer than our competitor (read: have had the usability kinks worked out) and I believe this is a substantial strength for us. We put substantial effort into making it easy to run through a complete design the first time as well as provide many examples (HW & SW) that start with a few mouse-clicks to get the user up to speed, but please don't take it from me (the biased-Altera-guy); there are plenty of people who post to this site who have experience with both sets of tools. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 77205
Hello all. Apologize if I'm in the wrong area but this seemed to be the tech topic area for Rocket I/O questions. We are implementing an Interface Upgrade to a radar system and Rocket I/O seems to be the candidate of choice for the data transfers involved. On the test side, I need to be able to assure data accuracy, timeliness and redundancy. I'm looking for some pointers on what the expected failure modes of a rocket I/O datalink can entail beyond a physical transceiver or cable h/w failure? Does anyone know of other failure modes to watch out for in this application? Thanks. jbs80922@yahoo.comArticle: 77206
avrbasic wrote: > "Purvesh" <purveshkhona@yahoo.com> wrote in message > news:1104002898.931299.49860@z14g2000cwz.googlegroups.com... > > Hi All, > > > > Anyone implemented SATA/SAS with FPGAs. Seems that neither rocketIO nor > > MGT in stratix GX are capable of handling OOB signalling of SATA/SAS. > > > > My question is : Which serdes did you use to work around the OOB > > problem ? > > > > -Purvesh > > > http://xilinx.openchip.org/ChipScope/ > > scroll down and look. > SATA OOB with real SATA chip - on VP20 board no external components rocketIO > direct to SATA. > can be done. > Hi. I'm interested in this, but the link doesn't work. Can you post the correct link? Thanks, DavidArticle: 77207
Hi Hur, You don't mention exactly what you are trying to do here. If it is a high-speed point-to-point data link between a MicroBlaze and another, I would recommend the FSL. This is a non-arbitrated link with a Fifo style, so would be a good fit for fast communication between processors. Each MicroBlaze has up to 8 FSL connection pairs. Add FSL ports to each MicroBlaze with the parameter C_FSL_LINKS. I think your diagram shows upto 3 connections per MicroBlaze, in which case, set C_FSL_LINKS = 3. Then add FSL busses, parameterize the FIFO depth, and then connect up your point-to-point links as needed! Picoblaze has output and input ports. You would need to do some simple decoding of the inputs and outputs, but this is also possible. You would need to create a register or FIFO interface between the ports - Picoblaze has possibility of up-to 255 ports using binary decoding of the port address, however simpler decoding structures are also possible, for example one-hot. Hope this helps, KrisArticle: 77208
Thank you for the quick reply. Based on the information you gave me I did order a NIOS II Development Kit with the EP2S60 ES (you can tell your boss you made a sale while surfing the web). Right now the additional resources are important to me. I do like the Altera tools better than the Xilinx's but the maybe because I original cut my teeth on with MAX+Plus II. Quartus seems more polished. The only thing that worries me is the use of third party libraries and frameworks. A company I use to work for use to provide support for Coral's Office sweet (made heavy use of third party software) when a customer installed another application that used the same software but a different version or revision then the headaches began. But I have been using your Wed Edition and Evaluation software without any of those bumps or bruises. Thanks again, Derek SimmonsArticle: 77209
this link is working now, sorry our site was attacked by the PHP worm vulnerability so I had to make clean reinstall of the whole server. Antti "unfrostedpoptart" <david@therogoffs.com> wrote in message news:1104355333.054285.130900@z14g2000cwz.googlegroups.com... > > avrbasic wrote: > > "Purvesh" <purveshkhona@yahoo.com> wrote in message > > news:1104002898.931299.49860@z14g2000cwz.googlegroups.com... > > > Hi All, > > > > > > Anyone implemented SATA/SAS with FPGAs. Seems that neither rocketIO > nor > > > MGT in stratix GX are capable of handling OOB signalling of > SATA/SAS. > > > > > > My question is : Which serdes did you use to work around the OOB > > > problem ? > > > > > > -Purvesh > > > > > http://xilinx.openchip.org/ChipScope/ > > > > scroll down and look. > > SATA OOB with real SATA chip - on VP20 board no external components > rocketIO > > direct to SATA. > > can be done. > > > Hi. I'm interested in this, but the link doesn't work. Can you post > the correct link? > > Thanks, > > David >Article: 77210
Hi Sam,
I would consider using a each multiplier for a several multiplications
actions by placing a mux before the mul inputs that way you will be
able to use each mult18x18 for two or more multiplication actions just
by changing the mux select input.
another sugessttion is to connect the mult18x18 to a memory block and
that way using it as a mux and for the varaibles and result registers.
all of the above suggestions are valid if the filter sampling time
enables you to do your multiplication in steps and not in one clock.
Another suggestion is to use MAC ("multiply and accumulate") unit that
can be very efficient for implementing filters (you can look for it in
the web).
Hope its helpful.
Moti.
Article: 77211Thanks Ray - Its always educating to read your answers. However In this kind of applications I tend to be a little lazy so I eventually found a xilinx core generator block calld a "ram based shift register" that completly suits my application so I went for the easy way.. Regards, Moti.Article: 77212
Hi Martin, The picoblaze compiler take your code (psm file) and uses it to create a vhdl component. then, you instantiate that component in your vhdl design and synthesize it as it was a regular block. afterwards you generate a bit file and download it to your FPGA as usual (either directly or using a configuration prom). Reagrds, Moti.Article: 77213
jbs80922 wrote: > > We are implementing an Interface Upgrade to a radar system and Rocket I/O > seems to be the candidate of choice for the data transfers involved. On > the test side, I need to be able to assure data accuracy, timeliness and > redundancy. I'm looking for some pointers on what the expected failure > modes of a rocket I/O datalink can entail beyond a physical transceiver or > cable h/w failure? Does anyone know of other failure modes to watch out > for in this application? These are not Rocket I/O specific, but could influence Rocket I/O operation: - Power supply failure or regulation - Ground bounce - Too many high current outputs switching at the same time (SSO) - Bit errors due to tight timing requirements OR getting close to temperature limits - Clock failure(s) - Glitches or overshoot/undershoot on any signal feeding into the FPGA (clock or otherwise) Have fun, MarcArticle: 77214
<DerekSimmons@FrontierNet.net> wrote in message news:1104357918.526189.6560@z14g2000cwz.googlegroups.com... > Thank you for the quick reply. Based on the information you gave me I > did order a NIOS II Development Kit with the EP2S60 ES (you can tell > your boss you made a sale while surfing the web). Right now the > additional resources are important to me. > > I do like the Altera tools better than the Xilinx's but the maybe > because I original cut my teeth on with MAX+Plus II. Quartus seems more > polished. The only thing that worries me is the use of third party > libraries and frameworks. A company I use to work for use to provide > support for Coral's Office sweet (made heavy use of third party > software) when a customer installed another application that used the > same software but a different version or revision then the headaches > began. > > But I have been using your Wed Edition and Evaluation software without > any of those bumps or bruises. > > Thanks again, > Derek Simmons > Derek, I think you made the right decision as far as tools go. I doubt you'll find anything close in terms of getting up and going quickly. I've found that each release of Quartus+SOPC Builder+Nios IDE gets substantially better and it started out pretty good. We didn't much care for the first release of the NiosII Eclipse based IDE, but the first service pack (1.01) has made it very usable. Altera is just now releasing 1.1. Make sure you join and follow the Nios Forum (www.niosforum.com) to avoid the gotchas and get answers quickly. We wasted a lot of time and money by discovering too many details ourselves - not recommended :) KenArticle: 77215
Andi wrote: > Did you try to use the ppc internal timer? Well, that might be a good idea. I just watched the API and using the PIT seems pretty easy, although i cannot try until january, and using the opb-timer was looking pretty easy, too. And i hope the PIT will work as expected/described: if i understand the docs right then the ppc405 on the fpga is some sort of 'lightweight'-ppc, missing some of the oroginal features. Although using the PIT might save some fpga-resources (at least the opb-timer, the interrupt-controller is needed elsewhere, too). But it won't solve the problem of the missing opb-timer-interrupt, for i really would like to know what my/the mistake is. Regards PatrickArticle: 77216
> Reading the newsgroup for a few weeks, I am obviously not in the same > league as most who frequent here, but it just seems very hard for a new > entrant to programmable logic to get a CPLD going. I'd love to go > straight to FPGAs, but the entire circuit is a 5 FF, 20 gate design, so > an FPGA and an EPROM seems overkill. I can certainly relate. In my case I bought a Altera Max 7000 ... along with the Devry Esoc board (Thank God for Ebay) then realized they were OVERKILL for what I wanted to do (simple state machines, and decode/glue logic) so I purchased a bunch of reprogrammable 22v10's (amd palce') and BPmicro's PLD-1128. I have been using them since and learning a lot, and my goal of designing a 6502 based SBC (that I FULLY understand) edges closer and closer to fruition. The fun aspect of this approach is that once I go OUTSIDE the PLD I am forced to revisit my old books on dc/ac analysis,circuit theory etc. (Its an interesting perspective for someone with a Software Background). > Am I going about this the wrong way? Should I avoid CUPL like the > plague? Is ABEL my best bet for CPLD design, or is there a reasonable > VHDL tool that will give me files I can program into a 750 or 1504, or > industry std PAL/GALs? Personally I chose to avoid VHDL because I felt CUPL would give me a better understanding of what is going on AT THAT level. I can "see" what I am doing ... when I am writing/simplifying the logic equation. Besides the book I used began with CUPL and its focus was on the PAL/PLA of yesteryear. Do you have a choice with CPLD's? I dont know any CPLD's supported by CUPL.Article: 77217
On Thu, 30 Dec 2004 16:34:10 GMT, sam <sam@here.com> wrote: [snip...snip...] >Do you have a choice with CPLD's? I dont know any CPLD's supported by >CUPL. Atmel's ATF15xx-series are supported by their free version of WinCUPL. Not huge devices but, like the more common 22V10s, they do fill a niche with 32 to 128 macrocells. There's a "ATF15XX-DK2 CPLD Development/Programmer Kit" available from Digikey, Arrow, etc. that includes an ISP cable, CUPL, and a 30-day trial of their HDL compiler. -- Rich Webb Norfolk, VAArticle: 77218
Hello, Well, the title might not be very exact. I have programmed big states machines in VHDL with quartus 4.1sp2. They all have an asynchronous reset, and i have leds to see what's going on for debug purpose. When i'm in the reset state, i must have a pattern on my leds. BUT, the bigger my state machine got, the stranger the behaviour. If I remove some access to the leds later in my state machine (not in the reset, but in a true state), all my leds are off during my reset, or sometimes only some are off, given the operation I add or remove IN COMPLETLY OTHER STATES, or even in others modules. I have really no idea of what is going on. My design is not yet very big (900 LE) and there are no really speed constraint on it. Could someone please explain me what I can do so wrong ? Best regards, and happy new year NickArticle: 77219
Sam wrote:
> Hi all !
>
> I am trying to implement a filter in a spartan III. I have several
> multipliers to put inside :-(
>
> Is it possible to tell the compiler to use the mult18x18 elements, and
> then, when all are used, to implement multipliers using for example
> LUT ?? Or to choose what kind of multipliers to implement by hand ?
>
> Because I simply use y <= a*b and this implements mult18x18. But there
> only are 16 in a 400k gates spartan ! So there's not enough mult18x18,
> but I only use a few percent of the slices...
>
> Thank you in advance !
>
> Sam
Unless you break up the filter, no you can't automatically select
multipliers until used then slices. What is your sample rate and
availble clock rate? If you can over clock by several times, then you
can either reuse the multipliers for several of the coefficient
multiplies (use a look up for the coefficient input to the multiplier),
accumulating the products, or you can go with a distributed arithmetic
architecture using the regular logic slices. Very often, the sample
rate is much smaller than the possible clock rate for the multipliers.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 77220Vhdl library named grlib at gaisler.com has some stuff related to AMBA. try google site:gaisler.com AMBA AHB However please note that given code is GPL i.e. you must open source(GPL) your own code if you use given code. Thanks, Etem Tezcan praveen wrote: > Hello, > 1.Can anyone provide me with some AMBA AHB VHDL models?or is there > anyone who has designed one? > > > 2. What is role played by wrapper??? > > Thanks and regards > PraveenArticle: 77221
Sounds like a logic race.
Maybe you don't have a clock input.
Maybe you have a clock, but
some inputs are not synchronizied to it.
Consider posting your code.
-- Mike Treseler
Article: 77222Hi, I'm working on a buffer-type application using a Spartan-III that requires six bytes of data to be read and written to memory at rates of about 100MHz. I was wondering two things: 1) Whether a Spartan-III is fast enough to send the required timing signals for a multiported memory at this speed. If not, I'll probably have to look into spending more money on a Virtex. 2) What companies sell multiported ram? Any suggestions will help. Regards, Jack MehinskyArticle: 77223
I am trying to use modelsim to do a timing simulation on a VHDL file I
generated using xilinx. I generated the: ecc.sim.sdf and the ecc_sim.vhdl.
However in modelsim with I use these commands it give me an error at the 5th
command. It will not vsim.
cd {c:/ecc/lab1test/ecc_multiply}
vlib work
vmap simprim c:/modeltech_6.0b/examples/Modeltech_6.0bxilinx/simprim
vcom ecc_sim.vhd
vsim -sdftyp /=c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf work.multiply
The error I get is:
** Warning: (vsim-SDF-3440) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf:
Failed to find any of the 85 instances from this file.
# ** Warning: (vsim-SDF-3442) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf: Try
instance '/multiply/nlwblockroc'. It contains all instance paths from this
file.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file
"c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf".
# Time: 0 ns Iteration: 0 Region: /multiply File: ecc_sim.vhd
Please help.
I am using modelsim 6.0b
Article: 77224
qudhs wrote:
> for all other location, the data is writting correctly. could someone
> point out what could be problem of those "wrong" writing? thank you!
Consider running a simulation with
a walking '1' and walking '0' address.
-- Mike Treseler
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