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Hi, I have created a periperal IP device using the "Create/Import.." wizard of the EDK 6.3. The IP has 4 32 bit registers. I have been able to connect the IP as a slave to the OPB and write a small program that can write and read these registers. However when I make changes in the vhdl files of the IP it seems to have no effect. I tried reading one of the four registers return a constant value but it still returns the value I previously read .. Do I have do soemthing to make the EDK update the IP? thanksArticle: 78676
jjohnson@cs.ucf.edu wrote:
> Anyone who has used the Power PC cores on Xilinx FPGAs has undoubtedly
> paid some dues... I selfishly ask if anyone has compiled a quick set of
> recipes, lessons-learned, or other guides for *quickly* getting up to
> speed on using these.
>
> There is no shortage of documentation available, especially from
> Xilinx. The problem (in classic Xilinx style) is that I don't have all
> year to read it. Thus, any pointers to the most-recommended,
> quickly-effective reading material would be appreciated.
>
> Specific scenario and questions:
>
> 1) I will soon have a board (with V2P30) on it. I wasn't originally
> planning to use the PPC, so no buses were routed for external memory.
> Hope to use on-chip memory only, now that I have a use for the PPC...
That is fine. Simple programs can run entirely in internal memory.
>
> 2) My tool set includes Mentor ModelSim, Synplicity (Synplify Pro), and
> Xilinx ISE. Do I need other $non-free$ tools in order to use the PPC?
> (i.e., Xilinx EDK, etc...)
I suppose it might theoretically be possible to implement only with ISE.
But that would be a painful process. EDK provides two things. It will
compile simple code into the necessary bitfiles for storage into the
internal block memory. And it comes with lots of "cores" for simple
modules to attach to the internal processor bus, and a relatively simple
method for interconnecting them. EDK is actually rather inexpensive, and
you do want it, IMO.
>
> 3a) I first want to instantiate one PPC, load some instructions in
> memory via ModelSim, tie the PPC core to the rest of the FPGA fabric,
> and simulate enough instructions to make sure the flow works.
>
> 3b) Next, I'd like to create some real short test programs, compile
> them with gcc (no RTOS required, but if easy to configure and use,
> that's a bonus), load the memory image (via ModelSim) and simulate.
That is probably more trouble than it is worth, at least I did not go
that far. I notice that Mikhail wrote:
> I am about to start a similar excercise, but haven't done much yet. I think
> you should begin with getting the EDK and perhaps one of the cheaper eval
> boards, e.g. V2Pro LC by Memec Design. Together with the board you will get
> access to several complete sample projects including C source code on the
> Memec web site. I am not sure about the simulation. I believe this sort of
> simulation will be extremely slow.
I in fact started with an Avnet board, which included EDK. I think this
is the best way to get started.
For simulating systems (using Modelsim), I took the approach of not
using the complex PPC models provided by EDK. I do use the provided
models for all the other pieces; the PLB bus, arbiters, bridges, etc.
For the PPC model, I basically wrote my own. That was down by creating a
PPC wrapper, of which here is an excerpt:
entity ppc405_top is
generic (
C_ISOCM_DCR_BASEADDR : std_logic_vector;
C_DSOCM_DCR_BASEADDR : std_logic_vector;
C_DISABLE_OPERAND_FORWARDING : integer;
C_DETERMINISTIC_MULT : integer;
C_MMU_ENABLE : integer;
C_DCR_RESYNC : integer
);
port (
C405CPMCORESLEEPREQ : out std_logic;
...
);
end ppc405_top;
architecture STRUCTURE of ppc405_top is
begin
PLB_Clk <= PLBCLK;
TST: entity work.bd_test
generic map (
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH
)
port map (
M_ABus => M_ABus(0 to C_PLB_AWIDTH-1),
M_BE => M_BE,
...
);
end architecture STRUCTURE;
Notice that about all this wrapper does is to instantiate the entity
bd_test. In board test, I have a couple of procedures for reading and
writing the bus. They look like this, along with the beginning of the
test bench:
entity bd_test is
generic (
C_PLB_NUM_MASTERS : integer := 1;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64
);
port (
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1 );
...
);
end entity bd_test;
architecture tester of bd_test is
...
begin
testit: process is
procedure sread(addr : in std_logic_vector(0 to C_PLB_AWIDTH-1)) is
-- data : in unsigned(7 downto 0)) is
begin
wait until rising_edge(PLB_Clk);
M_request <= '1';
M_RNW <= '1';
if addr(29) = '1' then
M_BE <= X"0F";
else
M_BE <= X"F0";
end if;
M_size <= (others => '0');
M_type <= (others => '0');
M_ABus <= addr;
if PLB_MAddrAck = '0' then
wait until PLB_MAddrAck = '1';
end if;
wait until rising_edge(PLB_Clk);
M_request <= '0';
M_RNW <= '0';
M_BE <= X"00";
M_ABus <= (others => '0');
if PLB_MRdDAck = '0' then
wait until PLB_MRdDAck = '1';
end if;
if addr(29) = '1' then
RD_DATA <= PLB_MRdDBus(32 to 63);
else
RD_DATA <= PLB_MRdDBus(0 to 31);
end if;
wait until rising_edge(PLB_Clk);
end procedure sread;
procedure swrite(addr : in std_logic_vector(0 to 31);
data : in std_logic_vector(0 to 31)) is
begin
wait until rising_edge(PLB_Clk);
M_request <= '1';
M_RNW <= '0';
M_size <= (others => '0');
M_type <= (others => '0');
M_ABus <= addr;
if addr(29) = '1' then
M_BE <= X"0F";
-- M_wrDBus(0 to 31) <= (others => '0');
M_wrDBus(0 to 31) <= data;
M_wrDBus(32 to 63) <= data;
else
M_BE <= X"F0";
M_wrDBus(0 to 31) <= data;
-- M_wrDBus(32 to 63) <= (others => '0');
M_wrDBus(32 to 63) <= data;
end if;
if PLB_MAddrAck = '0' then
wait until PLB_MAddrAck = '1';
end if;
wait until rising_edge(PLB_Clk);
M_request <= '0';
M_RNW <= '0';
M_BE <= X"00";
M_ABus <= (others => '0');
if PLB_MWrDAck = '0' then
wait until PLB_MWrDAck = '1';
end if;
wait until rising_edge(PLB_Clk);
M_wrDBus <= (others => '0');
end procedure swrite;
begin
M_request <= '0';
M_RNW <= '0';
M_BE <= (others => '0');
M_size <= (others => '0');
M_type <= (others => '0');
M_ABus <= (others => '0');
M_abort <= '0';
M_busLock <= '0';
M_compress <= '0';
M_guarded <= '0';
M_lockErr <= '0';
M_MSize <= (others => '0');
M_ordered <= '0';
M_priority <= (others => '0');
M_rdBurst <= '0';
M_wrBurst <= '0';
M_wrDBus <= (others => '0');
wait for 6.5 uS;
TEST_ID <= "01"; ---------------------------------------------
wait for 10 nS;
report "Test ID "&TEST_ID&" --------------------------------";
swrite(SADDR_C, X"40000100"); -- set start address
...
>
> 4) Load the PPC memory instruction via the bitfile when I power up the
> real hardware, have the PPC boot and start running my code when I
> toggle an input, so I can watch some outputs toggle on a scope.
> (Eventually this board will serve as a stimulus/waveform generator for
> another board.)
Yes, the PPC code is part of the bitfile. It will start running
immediately after the bitfile is loaded. There is not normally any
action required to "start" it.
>
> 5) Where might I find an appropriately configured copy of gcc and
> libraries?
That is included with EDK. You only need something fancy if you plan to
run a full operating system, like Linux. But that would require external
memory to do.
>
> That's it in a nutshell. I don't expect this to be a one-weekend
> project, but I don't have all year either. C code, VHDL code,
> Synplicity scripts, etc... for getting up to speed fast would be ideal.
>
> Thanks very much for *any* help you can provide.
>
> mj
>
--
My real email is akamail.com@dclark (or something like that).
Article: 78677Hi I have the following question: I have built a "coprocessor" which performs some special arithmetic operation. Until now I used Microblaze as my main processor which sends data to my coprocessor over the FSL link. Now I wanna try to run my core without Microblaze. But I have to admit I havnt a clue, how I can send input data to my core which I have downloaded on my FPGA board. This was until now done by my Microblaceprocessor. My core takes 2 input signals and I want to read out one output after computation is done. So I would be greatful if somebody could suggest me an easy way how I can access my input and output signals of my core. Could this perhaps be done with Chipscope? Is there perhaps some useful tutorial or example online? I am using a Virtex2P Board and for doing the synthese I have ISE 6.2 Thanks PatrickArticle: 78678
Peter Soerensen wrote:
> Hi,
>
> I have created a periperal IP device using the "Create/Import.."
> wizard of the EDK 6.3. The IP has 4 32 bit registers. I have been
> able to connect the IP as a slave to the OPB and write a small
> program that can write and read these registers. However when I make
> changes in the vhdl files of the IP it seems to have no effect. I
> tried reading one of the four registers return a constant value but
> it still returns the value I previously read .. Do I have do
> soemthing to make the EDK update the IP?
>
First, let me say that I am not using the EDK GUI except to create an
initial project. Thereafter, I make all changes with a normal text
editor, and compile by executing make commands at the command line (on
Linux). So keep that in mind when reading my comments.
I also noticed that when I made changes to one of the cores in my
project's pcores directory, that the changes were not automatically
compiled in. Eventually, I discovered somewhere in the EDK documentation
that you had to set a flag somewhere for that to happen (I don't
remember the flag, or where it was in the docs). Unfortunately, once I
set the flag, EDK insisted on recompiling the core every time, rather
than when a change had been made to the code.
So instead I hand edited the makefiles. In system_incl.make, I added
lines that look like:
MY_DDR_CLOCKS_IMPLN = implementation/my_ddr_clocks_wrapper.ngc
MY_DDR_CLOCKS_FILES = pcores/ddr_clocks_v1_00_a/hdl/vhdl/ddr_clocks.vhd \
pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.mpd \
pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.pao
MY_DIMM_IMPLN = implementation/my_dimm_wrapper.ngc
MY_DIMM_FILES = pcores/wsoa_dimm_v1_00_a/hdl/vhdl/clock_gen.vhd \
pcores/wsoa_dimm_v1_00_a/hdl/vhdl/command_statemachine.vhd \
pcores/wsoa_dimm_v1_00_a/hdl/vhdl/coregen_comp_defs.vhd \
...
MY_BITS_IMPLN = implementation/my_bits_wrapper.ngc
MY_BITS_FILES = pcores/plb_bits_v1_00_a/hdl/vhdl/bits_core.vhd \
pcores/plb_bits_v1_00_a/hdl/vhdl/plb_ipif_ssp1.vhd \
pcores/plb_bits_v1_00_a/hdl/vhdl/plb_bits.vhd \
...
MY_WRAPPER_NGC_FILES = $(MY_DDR_CLOCKS_IMPLN) \
$(MY_DIMM_IMPLN) $(MY_BITS_IMPLN)
MY_DEVELOPMENT_FILES = $(MY_DDR_CLOCKS_FILES) \
$(MY_DIMM_FILES) $(MY_BITS_FILES)
Then in system.make, I have lines that look like:
#################################################################
# HARDWARE IMPLEMENTATION FLOW
#################################################################
$(MY_DDR_CLOCKS_IMPLN): $(MY_DDR_CLOCKS_FILES)
rm -f implementation/my_ddr_clocks_wrapper.ngc
rm -f implementation/cache/my_ddr_clocks_wrapper.ngc
$(MY_DIMM_IMPLN): $(MY_DIMM_FILES)
rm -f implementation/my_dimm_wrapper.ngc
rm -f implementation/cache/my_dimm_wrapper.ngc
$(MY_BITS_IMPLN): $(MY_BITS_FILES)
rm -f implementation/my_bits_wrapper.ngc
rm -f implementation/cache/my_bits_wrapper.ngc
implementation/$(SYSTEM).bmm \
$(CORE_WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
$(MY_DEVELOPMENT_FILES)
@echo "****************************************************"
@echo "Creating system netlist for hardware specification.."
@echo "****************************************************"
platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE)
A little extra effort, but well worth it in the end for me.
--
My real email is akamail.com@dclark (or something like that).
Article: 78679Hi! I was wondering why my EDK 6.3 doesn't include this controller although it is listed here: http://www.xilinx.com/ise/embedded/edk_ip.htm#memory Was it removed from the EDK? Thanks, MatthiasArticle: 78680
Looking at the NIOS2 1.1 design examples I wonder why in the "standard" design the SDRAM pll is of type "Stratix" though the design is for the Cyclone board... And did anyone manage to clock it at more than those lousy 50MHz? rickArticle: 78681
Does anybody know where I can find out which pins on the parallel port are used by the JTAG cable included with the Spartan 3 board? C3Article: 78682
Hi You can reach 100 MHz without any problems. I will recommend to use "Timing Optimization Advisor" for hints how to improve fmax. After synthesis with clock constraints, I get ~102 MHz in Cyclone (C7 speed grade). MichalArticle: 78683
On Sun, 6 Feb 2005 11:13:16 +1100, "C3" <_> wrote: >Does anybody know where I can find out which pins on the parallel port are >used by the JTAG cable included with the Spartan 3 board? AFAIK, it's this: http://www.xilinx.com/support/programr/files/0380507.pdf -- Rich Webb Norfolk, VAArticle: 78684
Hi Nick, > Looking at the NIOS2 1.1 design examples I wonder why > in the "standard" design the SDRAM pll is of type "Stratix" > though the design is for the Cyclone board... Cyclone uses a PLL that is functionally equivalent to one of the PLL types from Stratix. Us software engineers are kind of lazy -- we reuse code where we can, and in this case it means that there is a rather unintuitive "stratix" flag for the PLL! > And did anyone manage to clock it at more than those > lousy 50MHz? Make sure you've applied a timing constraint to the clock in question. - PaulArticle: 78685
> Yeah, the 39% seems cooked to me, especially with no way to check it > for the interested public. > Where is that Altera guy hiding ? I have posted all I need to say on the subject. Clearly, I believe the +39% is real. We have invested years of engineering time to gather benchmark designs, fairly convert them between architectures, and figured out how to get the best out of both tools, and to produce comparisons. We have disclosed how we run our tests, and the results we achieved. But short of releasing the actual designs, which we cannot do, we will never be able to convince those people (such as you) who believe we are cooking the numbers when we are not. I can't blame you for being in disbelief -- trust me, we double- and triple-checked our results because we were so surprised that Virtex-4 came out so poorly. Do I believe 39% tells the whole story of comparing these two device families? No; it is just one (very important) parameter. Regards, Paul Leventis Altera Corp.Article: 78686
"Jedi" <me@aol.com> wrote in message news:HvcNd.554$Bx1.215@read3.inet.fi... > Looking at the NIOS2 1.1 design examples I wonder why > in the "standard" design the SDRAM pll is of type "Stratix" > though the design is for the Cyclone board... > > > And did anyone manage to clock it at more than those > lousy 50MHz? > > > rick > I clocked a NiosI on my Cyclone board at 140MHz running from onchip sram and 112MHz running from sdram. Haven't rerun the test with NiosII. But MHz isn't that important here. The problem is that it takes a minimum of 5 clocks to access onchip sram and 11-12 clocks to access sdram. KenArticle: 78687
According to Answer Record 20591 (http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=20591), this core has indeed been removed from EDK. Paul Matthias Alles wrote: > > Hi! > > I was wondering why my EDK 6.3 doesn't include this controller although > it is listed here: > http://www.xilinx.com/ise/embedded/edk_ip.htm#memory > Was it removed from the EDK? > > Thanks, > MatthiasArticle: 78688
Paul, let me help you. There are three ingredients to this "surprise": 1. Altera used its fastest (of three) speed grade against the middle of three Xilinx speed grades. ( I have previously explained your reason for, and the much stronger reason against doing that.) 2. Altera did not exercise the Xilinx software as strongly as they pushed their own. The software tools are quite different, and require a different approach if absolute highest speed is the goal. Which it was. 3. It is reasonable to assume that Altera's stored designs are more Stratix-friendly. So, don't you guys play the surprised innocent onlookers. Nobody expected Altera to be fair. Hell, I think the whole business of competitive benchmarks being run and promoted by an interested party is a sham and a disgusting deception. That's why I refused to enter the mudbath... Peter AlfkeArticle: 78689
Peter Alfke wrote: > Paul, let me help you. > There are three ingredients to this "surprise": > 1. Altera used its fastest (of three) speed grade against the middle of > three Xilinx speed grades. > ( I have previously explained your reason for, and the much stronger > reason against doing that.) Correct me if I am wrong, but didn't Altera use the most current speed file data that was available at the time? Or was the data available in the speed file and just the parts are not available? Lets face it. Even if the speed file data was available, data based on estimates is pretty pointless. We have seen significant changes in speed files even *after* a chip is in production. So the data is pretty meaningless *before* the parts are in production. > 2. Altera did not exercise the Xilinx software as strongly as they > pushed their own. The software tools are quite different, and require a > different approach if absolute highest speed is the goal. Which it was. This is a point that no one can prove either way. Xilinx does not release their benchmark designs and Altera does not either. So the users are left not knowing if any of the info is correct. > 3. It is reasonable to assume that Altera's stored designs are more > Stratix-friendly. That sounds like marketing-speak. Regardless, until we get a set of benchmarks that are open *and* useful, this is all just a tempest in a teapot. > So, don't you guys play the surprised innocent onlookers. Nobody > expected Altera to be fair. > Hell, I think the whole business of competitive benchmarks being run > and promoted by an interested party is a sham and a disgusting > deception. That's why I refused to enter the mudbath... But here you are... :) -- Rick Collins rick.collins@XYarius.com Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave. 301-682-7772 Voice Frederick, MD 21701-3110 GNU tools for the ARM http://www.gnuarm.comArticle: 78690
Paul Leventis (at home) wrote: <snip> > But short of releasing the actual designs, which we cannot do, we will never be able to > convince those people (such as you) who believe we are cooking the numbers > when we are not. And there you have the best possible argument for Public (WEB) Source code. - I cannot believe the designers at Altera feel happy to have "invested years of engineering time", and find themselves unable to publicly verify the numbers. ( and even have them openly laughed at ? ) - To me, that is a total waste of time. You, and your customers deserve better. Simple solution: Get some designs you CAN release !? -jgArticle: 78691
I know it's very obvious if you search by the title of that pdf, but how did you come to find this? I recall seeing it when I first got my FPGA board, but I didn't keep a copy of it, and could not subsequently locate it by searching the web. thanks C3Article: 78692
"Gary J. Tait" wrote: > > On Sat, 05 Feb 2005 14:23:50 GMT, Robert Baer > <robertbaer@earthlink.net> wrote: > > > > > France?? > > No Canada, where ATI and Matrox hail from. I understood that. However, when one hears French over the phone on such a call, it is possible that the help desk could also be in France...or in parts of Africa (theoretically).Article: 78693
Hi Peter, I think that the easy way for you to update your peripheral functionally is to re-import your peripheral(using the wizard) after updating your vhdl files (user_logic.vhd and the peripheral_name??.vhd) that way (i believe..) it will work just fine. Regards, Moti.Article: 78694
Hi I'm making a design and my top uses 2 differents models of memory (ROM) that I declare in vhdl using an array structure. But I got an error at the end of the top's synthesis: " FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. " I don't know what it is due to but if i comment one of the component ROM (only the instantation not declaration) there is no error , it's only when there is the two memories block. I chek up for for name signal in each component, name are different. Does someone know this problem ?? Thank You alexisArticle: 78695
ok i found the error
I have made an shift register with an array of std_logic_vector and I tried
to access directly to a part of it
cpt_V_reg(6)(8 downto 3),
and i use this signal to adress the memory block with an intermediate
signal for the adress and it seem to be not very good to do that.
But I found in xilinx website that this problem should have been fixed since
the 6.1i release of foundation and I got the 6.2i so it's not so fix , but i
don't know for 6.3i version
Should I advice a Xilinx FAE?? And if yes who (i'm french student so...)?
exemple:
component memoire_symbole is
Port ( clk : in std_logic;
adress_V : in std_logic_vector(5 downto 0);
adress_H : in std_logic_vector(6 downto 0);
symbole : out std_logic_vector(7 downto 0));
end component;
mem1 : memoire_symbole
Port map(
clk,
adress_V(8 downto 3), <- new code
adress_H(9 downto 3),
--cpt_V_reg(6)(8 downto 3), <- old code with problem
--cpt_H_reg(6)(9 downto 3),
symb
);
and the component code
process(clk)
begin
if rising_edge(clk) then
adress_symbole <= adress_V & adress_H ;
data_out_symbole <=
memoire_symbole(to_integer(unsigned(adress_symbole)));
symbole <= data_out_symbole;
end if;
end process;
"KCL" <kclo4@free.fr> a écrit dans le message de news:
42060ca4$0$25784$8fcfb975@news.wanadoo.fr...
> Hi
> I'm making a design and my top uses 2 differents models of memory (ROM)
> that I declare in vhdl using an array structure.
> But I got an error at the end of the top's synthesis:
> "
> FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application
> has discovered an exceptional condition from which it cannot recover.
> Process will terminate.
> "
> I don't know what it is due to but if i comment one of the component ROM
> (only the instantation not declaration) there is no error , it's only when
> there is the two memories block. I chek up for for name signal in each
> component, name are different.
>
> Does someone know this problem ??
>
> Thank You
>
> alexis
>
>
Article: 78696On Sun, 6 Feb 2005 22:18:11 +1100, "C3" <_> wrote: >I know it's very obvious if you search by the title of that pdf, but how did >you come to find this? I recall seeing it when I first got my FPGA board, >but I didn't keep a copy of it, and could not subsequently locate it by >searching the web. Originally found it linked from another site that sells Parallel 3 compatible dongles: http://www.fpga4fun.com/shop_FPGAcables.html The parent site has some interesting content and I noticed the schematic link while browsing it not long after my own Spartan 3 dev kit arrived. Synergy... -- Rich Webb Norfolk, VAArticle: 78697
Hi Jim, > And there you have the best possible argument for Public (WEB) Source > code. > - I cannot believe the designers at Altera feel happy to have "invested > years of engineering time", and find themselves unable to publicly verify > the numbers. ( and even have them openly laughed at ? ) - > To me, that is a total waste of time. You, and your customers deserve > better. From a marketing perspective, yes it makes life difficult. That is only a secondary goal of our benchmarking effort. The primary reasons we collect designs and measure our performance is to (a) improve our CAD tools and (b) experiment on new architectures. When developing new cad algorithms and new architectures, we need to be able to compare the new vs. the old to see if the change is a useful one. For example, there is no way we could have ever made the radical change of moving from our old Stratix 4-LUT based LE to the Stratix II decomposable 6-LUT with shared LUT function capability. There is a lot of pain (synthesis effort, IP changes, customer impact, etc.) associated with changing the logic architecture of a family, and we need good, solid data to back it up. Similarly, when we make changes to our synthesis, placement and routing algorithms, every such change must be validated for functionality and quality. Hopefully someone out there will put together some new public domain big benchmarks (like the old MCNC benchmarks, still quoted so often in academic literature). It would do the academic community some good to see what real designs look like these days. Paul Leventis Altera Corp.Article: 78698
On Sun, 06 Feb 2005 11:22:54 GMT, the renowned Robert Baer <robertbaer@earthlink.net> wrote: >"Gary J. Tait" wrote: >> >> On Sat, 05 Feb 2005 14:23:50 GMT, Robert Baer >> <robertbaer@earthlink.net> wrote: >> >> > >> > France?? >> >> No Canada, where ATI and Matrox hail from. > > I understood that. > However, when one hears French over the phone on such a call, it is >possible that the help desk could also be in France...or in parts of >Africa (theoretically). If you're getting lousy service, perhaps it's in Vientiane.Article: 78699
Hi all, My problem is as follows: when I'm inserting a mdm (debug module) to my microblaze project it automatically adds two bufg components to my design (for the use of the mdm). I dont have any free bufgs so i would like to know how can I order it no to use these bufgs (I think that it uses them for the JTAG/Bscan) . I hope that it can be done. I will appriciate it if someone will help me to resolve that annoying issue. Thanks in advance, Moti.
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