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Joerg Ritter <ritter@informatik.uni-halle.de> writes: > the compilation of the kernel module windrv6.ko under kernel 2.6.x > using the distribution SuSE 9.2 fails. > Here are my steps to get it work: [...] > Maybe you should add this to the description of Hein Roehrig. Thanks, I updated <http://www.fpga.de/tiki/tiki-index.php?page=XilinxSoftwareLinux> -HeinArticle: 78901
>My questions is - >What happens if the second flop (int_reset_l[1]) goes metastable or >if it cannot then why? You don't have to worry about the leading edge of reset making the second FF go metastable. That case is cleanly asynchronous. The rest of the FSM might go metastable, but that will only last one clock. The next cycle will fix things up. (More likely is a bogus state because of setup timings not reaching all FFs at the same time - simple timing violation.) You do have to worry about what happens during that clock. Most of the time, the next step downstream will recover. It might be more complicated than that in safety critical applications. On the trailing edge of reset, you don't have to worry about metastability since the second FF is going from 0 to 0. The first FF might go metastable. You do have to make sure there is enough time on the clock between the first and second FFs to cover that case. You can't get it perfect, just good enough for your application. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 78902
Thank you for your quick response Peter. I'm not saying that we are going to use distributed RAM, infact we are going to use Block RAMs just as you pointed out. But, since Coregen generates Async or Sync FIFO based on either RAM, I was curious to know what the Timing model was if we ever have to use distributed RAM based FIFOs in the future. If you have any info on this I'd very much appreciate it. I have a few more questions on the Block RAM FIFO but, I will address them through Webcase. As an aside, I remember you from my AMD days way back in 1983-84 timeframe. I was in Clive Ghest/Steve Dines organization working on the QPDM graphics processor. Thanks.Article: 78903
Nope, please see my response to Peter Alfke in this forumArticle: 78904
Hello: I want to design a board with an altera FPGA and DDR (about 2Gigabytes) so that I can read and write from this RAM at high data rates. From what I understand Altera provides users with cores for interfacing with DDR. My questions are: 1) Are there any daughterboards already in existence (with DIMM sockets) that I can interface to a development board from Altera? 2) Has anybody done this with success? Are there any resources on the net that I can read on precautions that must be taken when attempting to interface an FPGA with DDR, layout ideas, etc.? Thanks. JohnArticle: 78905
Here's one more reference on the ALM. It was published at last year's FPL conference. Mike Hutton, Jay Schleicher, David Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim and Rahul Saini, "Improving FPGA Performance and Area Using an Adaptable Logic Module", Proc. 14th International Conference on Field-Programamble Logic, Leuven, Belgium, pp. 135-144, Sept 2004. LNCS 3203. Paul Leventis Altera Corp. "Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message news:joGdnWYVqLWB35XfRVn-vw@rogers.com... > Hi Glen, > >> I do wonder if the optimal LUT size has changed over the years. >> Is there work showing the optimal LUT size as a function of silicon >> resources needed to implement such LUTs? > > Elias Ahmed & Jonathan Rose from the Unversity of Toronto published "The > Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and > Density". See http://www.eecg.toronto.edu/~jayar/pubs/ahmed/fpga00.pdf. > Elias's M.A.Sc. thesis was on clustering and optimal lut sizes. This > paper contains many references to previous work in the area and is > probably a good starting point. The paper's conclusion is that a LUT size > between 4 and 6 is and cluster sizes of between 3 and 10 LEs are best from > a balanced area-delay perspective. If you want higher speed, larger LUTs > are better. One suggested area of future research is finding a way to > reduce logic levels without the area cost of large LUTs -- and this is > what we have done in Stratix II with the ALM. Figure 12 is particularly > interesting. > > I think Guy Lemieux had some work in this area from his PhD -- not sure if > its published anywhere yet. > > At the FPGA 2005 conference in two weeks, the Stratix II logic > architecture and some experimental results will be presented in a paper by > David Lewis et al. > > Regards, > > Paul Leventis > Altera Corp. > >Article: 78906
Hello Peter, I changed my mind and am submitting two more questions here on Virtex4 Async FIFO for you : 1. On the Coregen tool, we could not find a button to choose between First Word Fall Through (FWFT) and Standard modes of operation 2. We have a file in our XilinxCoreLib directory called FIFO_GENERATOR_V1_1.v and it does not seem to understand FWFT either. is there a newer version of this file as well as Coregen/Fifogen tool that we need to upgrade to to get these features ? ThanksArticle: 78907
I just graduated from the University of Maryland with a degree in Computer Engineering. I am currently doing QA for a software developer and I realize that this is definately not what I want to do. The more I think about doing hardware design, the more I hear a voice in my head subtly whispering to me: "WEST ... GO WEST...". Sure, there is some hardware design over here on the east coast, but I am just so freaking sick of this cold weather. Can anyone offer any advice on making the move from the east coast to the west coast in hopes of landing that hardware job of my dreams? Sincerely, Oren F.Article: 78908
Thank you if you watched the previous story on Virtex-4 performance. Now please click on http://seminar2.techonline.com/s/xilinx_feb1505 and sign up for the next presentation in this series, where Matt Klein of Xilinx Applications will explain the three aspects of power consumption. This is again an engineering presentation: Matt has been a "power user" of Xilinx FPGAs for over 17 years, he even published a Xilinx app note in 1990, while working at hp. We have been friends since 1988, and I was thrilled when he decided to join Xilinx Applications last year. The previous talk on performance had excellent participation, and a spirited follow-up debate in this newsgroup. Thank you, Paul, for providing spice with the contrary point of view ! I hope many of you will join us again coming Tuesday at noon, Pacific Time. Peter Alfke, Xilinx ApplicationsArticle: 78909
I haven't been able to find the junction-to-board thermal resistance numbers for the FG676 package (or any other package). I know that theta(jc) is about 2degC/W, and we're curious as to how much thermal power might be going into our pcb. We can measure the theta(ba) of our pcb, and we do know the theta(sa) for our heatsinks. We could probably deduce the (jb), but we'd like some correlation from Xilinx. Also, are any psi(jt) numbers available? Thanks, BobArticle: 78910
Rick Fox wrote: > Hello, > > Some time ago I bought a box of surplus EPM7128SLC84 CPLD's for the > more advanced pupils at my school to have a play with. It was to be a > learning exercise for us all, something different to MCU's. > > Unfortunately, I've just found out (I think) that they all have their > jtag pins programmed as user I/O. I can't program them with my > byteblaster, although it works fine with a smaller (new) CPLD I > bought. I wasn't aware of this potential problem before. > > The error from Quartus Programmer is: > Info: Unrecognized Device > Error: JTAG ID code specified in JEDEC STAPL Format File does not > match any valid JTAG ID codes for device > Error: Operation failed > > Nor will the Quartus programmer auto-identify the devices, saying > "Can't scan jtag chain", again it works fine with the new one. > > First, does my assumption here sound correct? > > Second, is there any way to clear the jtag pins without a Master > Programmer? (Google thinks the answer is no, but it's worth asking) > > Third, is there anyone who has a Master Programmer or other capable > programmer (in the UK, preferably near Manchester) and would be > prepared to help me out and reprogram about 25 CPLD's? I don't mind > donating a few beer tokens if it will help! > > Rick Fox > (Belmont Special School) > Manchester, UK. Hi Rick, Unfortunately, the 'S' in the EPM7128SLC84 part indicates that this part cannot be programmed with a byteblaster cable. The new part that can be programmed is probably an 'A' part i.e EPM7128Axxx. It might be worth contacting an Altera FAE to see whether they are willing to program these parts for you. Regards BenArticle: 78911
Ben Popoola <ben.popoola@remove.recontech.co.uk> wrote: > Hi Rick, > > Unfortunately, the 'S' in the EPM7128SLC84 part indicates that this part > cannot be programmed with a byteblaster cable. The new part that can be > programmed is probably an 'A' part i.e EPM7128Axxx. > > It might be worth contacting an Altera FAE to see whether they are > willing to program these parts for you. > > Regards > Ben Read the first paragraph of the ByteBlasterMV datasheet. The MAX 7000S is the second device mentioned. -- Wing Wong. Webpage: http://wing.ucc.asn.auArticle: 78912
Yes and no. The GT3200 is UTMI PHY so it would sync on valid SYNC and receive whatever comes afer that and on transmit similarly. A custom protocol could be implemented. Thats on the GT3200 side. On the PC side its almost a FULL NO to your question. Depending on the host controller this may or may not pe physically possible, and even if it is, then would require custom very specific low level driver. Easeir would be to makea very simple PCI board with GT3200 and use it as PHY only that would be possible. AnttiArticle: 78913
Dave Colson wrote: > Hi, > > Just wondering if anyone has used, or tried to use > this device yet. I have a design I did for the ProAsic+ > that I converted to use the PA3 as a test. Went fairly well. Only > real issue I had was that when I set the option for Designer or move > flip flops to the IO cells, it did not implement them correctly. > Specifically the async resets where the wrong sense. Since The device I > am targeting is not in production yet so I can only simulate the back > annotated > design. This is where I discovered the problem so I do not know if the > problem > is with the simulation model or with designer. > > I had a couple of problems with the Plus and notice some changes to the PA3 > data sheet; primarily concerned with the JTAG TRST pin. Under the pin > description > section, They "recommend" the following: > > "TRST Boundary Scan Reset Pin > > The TRST pin functions as an active low input to > asynchronously initialize (or reset) the boundary scan > circuitry. There is an internal weak pull-up resistor on the > TRST pin. In the operating mode, a 100 ? external pulldown > resistor should be placed between TRST and GND > to ensure that the chip does not switch into a different > mode." > > I had a power-up problem on some of the Plus device and found out > that if I ground the TRST pin , the device would start working. I > report this to Actel and had them evaluate the parts that exhibited the > problem. > There recommendation: "ground the TRST pin". Sounds to me like there is a > problem with the TAP port on both the Plus and PA3 devices and the > 100 ? resistor is the "patch" to fix it. I am curious if anyone else has had > problems with the TRST pin. > > The other problem I have had is a high programming failure rate > while using the FlashPro programmer, mostly exit 11 errors. > Actel was not able to helps us solve this problem. We did > not press them on this since eventually we would be getting the > devices programmed by our supplier and it would become > a non-issue after that. The curious thing is that if a device successfully > programmed the first time, it would more then likely always program > successfully. I have reprogram a single device 50 to 60 times > with no problem. I suspect a marginal problem with the device itself or > a problem with the programming algorithm and not with my programming > fixture. > > It bothers me that Actel will not admit problems with their devices. Xilinx > has no problem with admitting problems with devices and then publishing > a work around to the problem until a permanent fix to the silicon is > implemented. > Why is Actel reluctant to do this. Maybe this problem with the TRST was > already > know to them, and if they had published an errata on this then maybe I would > not have > spent over a week debugging this problem. > > Why do I use Actel if I am unhappy with there devices? the truth is it is > the only > reprogrammable FPGA that fit the application. > > Would like to hear about any experiences that other people have had with the > Actel > Flash parts. I am meeting with a sales rep and FAE on these products tomorrow, opps, today. My main concern is that they are not slated to be out until Q4 although I was told possibly Q3 (meaning end of Sept). I also want to hear some real pricing instead of the "as low as xxx in quantity". I was told that the larger parts would be out first. So if you want a $1.50 part you will need to wait until '06, I expect. The data sheet talks about being 5 volt tolerant, but they aren't. They just do the same game of using resistors like the Virtex, etc. parts. I don't see the pulldown on the TRST as being much of a bug myself. My experience has been that every part handles the JTAG signals in different, often incompatible ways. But if you use the spec'd pull ups or downs and use their cable the JTAG should work just like TI DSPs and Xilinx FPGAs. I'll let you know what I find out from the FAE.Article: 78914
"sdaq" <orenfromberg@gmail.com> schrieb im Newsbeitrag news:1108011168.056299.119610@o13g2000cwo.googlegroups.com... > I just graduated from the University of Maryland with a degree in > Computer Engineering. I am currently doing QA for a software developer > and I realize that this is definately not what I want to do. The more I > think about doing hardware design, the more I hear a voice in my head > subtly whispering to me: "WEST ... GO WEST...". Sure, there is some > hardware design over here on the east coast, but I am just so freaking > sick of this cold weather. Can anyone offer any advice on making the > move from the east coast to the west coast in hopes of landing that > hardware job of my dreams? > > Sincerely, > Oren F. The only advice for you: Do whatever it takes to make your dreams true - www.truedream.org :) My dream at school was - best looking girl from my class, also first love (100% single sided) - palm trees - white sand - blue lagoon only many years after school I did make that dream true (kind of) she had a family already, but I did take her to world-around PANAM first class from Tokyo to Hawai, a few weeks on the westcoast... It wasnt easy to arrange (Estonia was part of former ex-USSR at that time!) A job itself is hardly something to be dream of. Its mostly hard work as reward some of your real dreams may be fulfilled. I am 40years old in few month, I have never used a paid vaccation and I have never had vaccation with my family. So my dream is that some time, hopefully as soon as 2006 I can afford to have a vaccation with my Family. You can land a job anywhwere, dont "hope to land a job" do something! Like write some really cool IP-Core something that makes some "news" turbulence, that coud help ;) Hm I already have a project for you... a bit-serial implementation of ARM processor - it is doable, it would be working full ARM useable on small FPGAs, sure it would run about 40 times slower than parallel ARM, but hehe a 1MHz effective clock ARM core that is smaller than MicroBlaze or NIOS-IIe ? And capable to execute in-place code from serial memories or MMC/SD Card? That would be a real nice thing! Besides anyone who does it, will deserve some "attention" from ARM lawers, in my opinion such attention (if it comes) would be funny and only serve as good advertizing! Want to take that project? I can help you get started and mentor the verification. Its doable thing, it should not even take too long to implement. I guarantee that I help you if needed to get it finished, should you volounteer to try. No but really before deciding, try to fully implement some useable and useful IP-Core, including testbench hardware verification, after that revise your dreams once again.. AnttiArticle: 78915
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:Wrqdneo8FpgSkpbfRVn-jw@adelphia.com... > Dave Colson wrote: > > Hi, > > > > Would like to hear about any experiences that other people have had with the > > Actel > > Flash parts. > > I am meeting with a sales rep and FAE on these products tomorrow, opps, > today. My main concern is that they are not slated to be out until Q4 > although I was told possibly Q3 (meaning end of Sept). I also want to > hear some real pricing instead of the "as low as xxx in quantity". > > I was told that the larger parts would be out first. So if you want a > $1.50 part you will need to wait until '06, I expect. > > The data sheet talks about being 5 volt tolerant, but they aren't. They > just do the same game of using resistors like the Virtex, etc. parts. > > I don't see the pulldown on the TRST as being much of a bug myself. My > experience has been that every part handles the JTAG signals in > different, often incompatible ways. But if you use the spec'd pull ups > or downs and use their cable the JTAG should work just like TI DSPs and > Xilinx FPGAs. > > I'll let you know what I find out from the FAE. Please do so! The first part out is 600E that was known already at Electronica 2004 (that is nov 2004) hm are you saying no parts will be available til Q4 ? that would be pitty! Most vendors dont admit silicon bugs! You need to prove their silicon is faulty then in some case with long delay they might agree yes there is a problem. AnttiArticle: 78916
Try 'On the road'. A perfect winter's night read to teach you how to travel coast-to-coast! Maybe not! Syms. "sdaq" <orenfromberg@gmail.com> wrote in message news:1108011168.056299.119610@o13g2000cwo.googlegroups.com... >I just graduated from the University of Maryland with a degree in > Computer Engineering. I am currently doing QA for a software developer > and I realize that this is definately not what I want to do. The more I > think about doing hardware design, the more I hear a voice in my head > subtly whispering to me: "WEST ... GO WEST...". Sure, there is some > hardware design over here on the east coast, but I am just so freaking > sick of this cold weather. Can anyone offer any advice on making the > move from the east coast to the west coast in hopes of landing that > hardware job of my dreams? > > Sincerely, > Oren F. >Article: 78917
Hal Murray wrote: >>My questions is - >>What happens if the second flop (int_reset_l[1]) goes metastable or >>if it cannot then why? (snip) > On the trailing edge of reset, you don't have to worry about > metastability since the second FF is going from 0 to 0. > The first FF might go metastable. You do have to make sure > there is enough time on the clock between the first and > second FFs to cover that case. You can't get it perfect, > just good enough for your application. The probability of metastability effects decreases exponentially with time. Assuming that you have logic between FFs elsewhere in the design there should be plenty of time when there is no logic. That is, when the probability is less than once in the life of the universe, maybe a lot less, that is usually enough. -- glenArticle: 78918
Hi, "Dave Colson" <dscolson@rcn.com> wrote: > It bothers me that Actel will not admit problems with their devices. Xilinx > has no problem with admitting problems with devices and then publishing > a work around to the problem until a permanent fix to the silicon is > implemented. I'm not sure, but I think, the fact that Actel has mostly highpriced devices means that the applications were the fpgas are used, are also high valued. This means that systematically failure tend to be more expensive for Actel. > Would like to hear about any experiences that other people have had with the > Actel > Flash parts. I use some for prototyping and I am very satisfied with. The only wish I had are 5V IO Buffer. Unfortunately there seems to be no reprogrammable device with 5V IO and sufficient cells on market to do prototyping for Asics with 5V IO. bye ThomasArticle: 78919
Hallo to everyone, I should develop a microcontroller based on microblaze with keypad and 320x240 graphic LCD for an university exam. I should also make a printer interface to print datas displayed on LCD. There is someone who could help me? Many Thanks in advance MarcoArticle: 78920
Hi David thanks for ur info....I have visited suggested site...found quite useful.... sudheerArticle: 78921
Another idea: What do you guys think about adding a slot for a SD Card [1]. They are cheap (about EUR 10,- for 128MB) and you get them up to 1GB! However, the impact on the board is high: The connector is 'big' and increases the board hight. A FPGA with a higher pin-count is needed. For the solution without the SD Card a 100pin TQFP would fit, but now a 144pin is needed - again a larger board. And this adds again a few EUR/$. All these design decissions! You start with a minimal core design and than start adding (unnecesssary) features again. BTW: Has somebody inplemented an SD Card interface in an FPGA. It should not be too hard [2]. The simplest solution would be the SPI bus. [1] http://www.sdcard.org/sd_memorycard/index.html [2] http://www.sandisk.com/pdf/oem/AppNoteMMC_SDv1.0.pdf Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/ "Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag news:sO%Nd.34738$2e4.30046@news.chello.at... > Hi all, > > I'm thinking about a new board for JOP (or MB, NIOS). The board should be small and > cheap (below the S3 Starter Kit). It should only contain the absolute necessary parts for a > CPU design. Here is the suggested part list: > > FPGA: Cyclone EP1C3 or Spartan XC3S200 > 256Kx16 15ns SRAM > 2 MBit serial Flash > 3.3V linear regulation > switching regulator for the core voltage > 20MHz clock to the PLL input > > I've not yet decided about a X or A device. > > A remaining question is about the form factor. I still think it makes sense to build > the board as a module that can be integrated in a board with the peripherals (similar > to the ACEX and Cyclone modules I've done). There are two 'standards' available: > > 1.) SimmStick, where the boards are designed as the 'old' PC SIMMs (see [1]). > > 2.) The 'Basic Stamp' design is a board in the form of an old 40-pin (or less) DIL IC. > An example (from a Java processor competitor): [2] > > For a Java solution in an FPGA this board should beat the Systronix aJ100 Java processor > modules (JStamp or JStick [3] - they have both form factors) in performance and price. > One nice thing about the SimmStick is that there are plenty of I/O boards already available > (see [4, 5, 6]). > It seems a relative 'old' design, but it's a bus and I can build my first JOP cluster with those > boards ;-) > > What do you guys think about this idea? Does it make sense to build a another FPGA board? > > [1] http://www.simmstick.com/ > [2] http://jstamp.systronix.com/jstamp_photos.htm > [3] http://www.jstik.com/ > [4] http://www.dontronics.com/dt.html > [5] http://www.hobbyengineering.com/SectionSS.html > [6] http://www.simmstick.com/simmstic1.htm > > Martin > ---------------------------------------------- > JOP - a Java Processor core for FPGAs: > http://www.jopdesign.com/ >Article: 78922
Hi is it possible to connect any secondary board to ml310 through its expansion slots.If so which cable I have to use and where can I get it. I want to connect USB and Firewire i/o ports to main PPC through its gpio pins directly not through pci slots (which are available on ml310 already) as I need to analyze the processor and peripheral interaction. Does anyone had an idea which simple board is available in market , I dont mind if the secondary board doesnt have an USB and firewire PHY ...I can put some load on ports through simulators. so any `simple board with FPGA`s on it will meet my requirement. software: any idea where can I get firewire IP core for cheap.finaly I want to run linux over the system (ml310 and secondary board). kindly suggest me if anyone has experienced similar before.... Hmmm.. hope my questions are not silly as my experience with hardware design is not much. thanks a lot.. sudheerArticle: 78923
Hi, I'm trying to do reads/writes to a flash device on our board using the Microblaze processor. The part itself is the same as featured on the Insight board for the XC2V1000 eval board. When I simply try and read back the manufacturer and id codes, I get the value 0x00AA00AA instead - incorrect value. Any erase or write operations also fail. I'm using EDK 6.3 and an opb_emc peripheral - I used to use an opb_memcon (I think) on previous versions of the EDK and this worked ok with the same board. It's a combined SRAM/Flash device and the SRAM works ok. I've no clue why it now fails. Cheers, Pete.Article: 78924
not that I like to kill the joy but: 1) Fireware - NO IP Core (free or cheap) available, opencores project dead and remains dead 2) ML310 possible no boards exist (that suite your wishes) that connect to the personality slots 3) USB testing with 2 FPGA boards - doesnt really make sense anyway, if you are into anything serious you need to have the PHYs and work with real USB devices sorry, maybe I did not understand your goals, Antti "sudheer" <sudheer_sanna@yahoo.com> schrieb im Newsbeitrag news:ee8bb96.-1@webx.sUN8CHnE... > Hi is it possible to connect any secondary board to ml310 through its expansion slots.If so which cable I have to use and where can I get it. > > I want to connect USB and Firewire i/o ports to main PPC through its gpio pins directly not through pci slots (which are available on ml310 already) as I need to analyze the processor and peripheral interaction. > > Does anyone had an idea which simple board is available in market , I dont mind if the secondary board doesnt have an USB and firewire PHY ...I can put some load on ports through simulators. so any `simple board with FPGA`s on it will meet my requirement. > > software: any idea where can I get firewire IP core for cheap.finaly I want to run linux over the system (ml310 and secondary board). > > kindly suggest me if anyone has experienced similar before.... > > Hmmm.. hope my questions are not silly as my experience with hardware design is not much. > > thanks a lot.. > > sudheer
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