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Hallo Sewook Wee thank you for replay ! I have fixed the problem :-) But just for Info! I have on my Board 64MB SDRAM. But i have initialize only 32MB im EDK and so there was i timing problem! After i initialize 64MB in EDK the interrupt is going! buyArticle: 79851
Hello,everyone. I am doing my thesis on the ML310 board..it's so hard.. Lots,lots of pdf for reading.. :!: My first target is transfer data between processors using the FPGA Block-SelectRAM (BRAM). 1.-----Prove data flow between the processors (from processor A to processor B and vice versa). After BSB, I open up the PBD file, see that the two ppcs have already connected with brams..plbs..ocm-ctrl.. But how could I prove the data flow.. Shall I write a short C test program in EDK, and saw the result with hyper terminal? or shall I write a vhdl program to see the result with modelsim... confusing... :( 2.-----If possible make also use of the Rocket-IO (MGT). why should I use the rocket-IO..is that the same procedure to prove the data flow with rocket I/O as with Brams.... Great appreciate your help!!!!!!!!! :DArticle: 79852
Yes you can make it generic, assuming that B is a constant. I have removed A, and changed B and cpt to naturals. When this is synthesized, the synthesizer will change this to an n-bit counter, where n is log2(B). generic ( B : natural ); .. signal cpt : natural range 0 to B; if (cpt = B) then cpt <= 0; else cpt <= cpt + 1; end if;Article: 79853
stella <xun.xu@student.groept-dot-be.no-spam.invalid> wrote: > Hello,everyone. > I am doing my thesis on the ML310 board..it's so hard.. > Lots,lots of pdf for reading.. :!: > Me too! I'm also using that same board. :) Sorry but I don't really have anything useful to add other than I sympathise with you. -- Wing Wong. Webpage: http://wing.ucc.asn.auArticle: 79854
Hi Partha, > (2) The system clock frequency is 50 MHz. However, there were several > warnings reported of the kind: "WARNING:Power:91 - Can't change frequency > of net sys_clk to 5000.00Mhz." I don't know what to infer from there? I ran in to similar errors with XPower recently and opened a webcase on it. Xilinx told me that they found a couple of bugs related to the message above and this should be fixed in the next ISE release (not long now...?). So, I am waiting for that! :-) KenArticle: 79855
vax, 9000 <vax9000@gmail.com> wrote: > Today I searched google news for Altera and found the news saying that > Altera signed contract with Digikey in Feb. 15th, 2005. Now hobbists don't > need to ask where to buy Altera again on the list. And they don't sell it on their germany web site (de.digikey.com), as digi does not sell Linear Technology in Germany. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 79856
Hi, I would like to how much money does an engineer win in Serbia (more exactely Belgrade) ? Because I'd like to make a VIE in a French companie wich have a design center there. Regards AlexisArticle: 79857
Göran Bilski <goran.bilski@xilinx.com> wrote in message news:<cvkuvu$bje3@cliff.xsj.xilinx.com>... > Hi, > > If you don't want to express the constant value as binary, you can also do this. > > PORT FSL0_S_DATA = 0x00000001 That's great! Thank you very much for the help.Article: 79858
On Thu, 24 Feb 2005 13:23:34 -0800, Partha Biswas wrote:
> spartan wrote:
>> I have been looking at the idea of implementing the microcontroller
>> function into the FPGA using either Microblaze or NiosII. Does anyone
>> have
>> experience with these two products?How good is the software development
>> environment. Does it include breakpoints and examination of register and
>> memory variables? I do appriciate to tell me your experience with
>> Microblaze and NiosII.
>>
>>
> Hi,
>
> The report in
> http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf
> might come handy to you at this point.
>
> Regards,
> Partha.
That report might give the OP some ideas about synthesizable cores in
general, but it has a lot of flaws ("portability" is judged by "how did I
get it running on my single Xilinx demo card"), and doesn't even mention
the NiosII.
I don't know about the Microblaze, but the Nios II comes with a
substantial software development environment based around Eclipse, with
gcc as the compiler and gdb for debugging (with Eclipse as the gui). You
get full software breakpointing, a few hardware breakpoints, reading and
writing of memory and variables, and everything else you would expect from
a modern debugger. You can buy extra tracing functionality (some using
internal fpga resources, others using external equipment) if you need it.
Article: 79859"spartan" <startix_tm@nospam.yahoo.ca> writes: This not a NIOS-II Microblaze issue, but a related Altera SOPC-Builder vs. Xilinx XPS issue. In SOPC-Builder you can select if you want to generate Verilog or VHDL. Since I'm using Synopsys VCS for my simualtions I've used Verilog as target. All the generated files are Verilog source files. However, with Xilinx XPS it appears that only the top level module is Verilog and it consists of several wrapper modules. The actual code for the IP are written mostly in VHDL. Hence I can't use VCS for my simulations (unless I spend several tens of thousands of dollars per license to get the MX version). Alternatively, I'll have to do gate level simulations only. Is my understanding correct, or is there some kind of conversion I can do in XPS? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 79860
"spartan" <startix_tm@nospam.yahoo.ca> wrote in message news:<8a052749b6d8126f391f63acad407c36@localhost.talkaboutelectronicequipment.com>... > I have been looking at the idea of implementing the microcontroller > function into the FPGA using either Microblaze or NiosII. Does anyone > have > experience with these two products?How good is the software development > environment. Both toolchains are based on GNU (GCC, binutils), so not many differences. NIOS II comes with eclipse (an IDE), but you can download that separatly for MicroBlaze anyway, > Does it include breakpoints and examination of register and > memory variables? I do appriciate to tell me your experience with > Microblaze and NiosII. Both toolchains use GDB, so you get the same set of features. Cheers, JonArticle: 79861
stella wrote: > Hello,everyone. > I am doing my thesis on the ML310 board..it's so hard.. > Lots,lots of pdf for reading.. :!: > > My first target is transfer data between processors using the FPGA > Block-SelectRAM (BRAM). > > 1.-----Prove data flow between the processors (from processor A to > processor B and vice versa). > > After BSB, I open up the PBD file, see that the two ppcs have already > connected with brams..plbs..ocm-ctrl.. > > But how could I prove the data flow.. Shall I write a short C test > program in EDK, and saw the result with hyper terminal? or shall I > write a vhdl program to see the result with modelsim... > > confusing... > :( > 2.-----If possible make also use of the Rocket-IO (MGT). > why should I use the rocket-IO..is that the same procedure to prove > the data flow with rocket I/O as with Brams.... > > > Great appreciate your help!!!!!!!!! :D I have done something like this in the past on a ML310 board. I'd go with option #1. I would write a simple C program. To get something working quickly, write two versions of the simple program--one for processor 0 and another for processor 1. You create two software projects in XPS and have the linker script put the programs in two different BRAM's. The shared data must be in the same BRAM obviously. Sample Program ----------------- -Processor 0 writes to location x with value y. Meanwhile, Processor 1 is in a while loop reading location x. If mem[x] == y, then Processor 1 writes mem[x] <= z. -After processor 0 wrote mem[x] <= y, it sits in a while loop until mem[x] changes to z. At which point, processor 0 prints to Uart a happy message. Processor 0 cannot print the message until processor 1 changes mem[x] to z. Likewise, processor 1 cannot change mem[x] until processor 0 changes it to y, so it proves that the sharing is working properly. Things to watch out for: -caches should be turned off for the region of memory that x lies in. This is to prevent the processors from reading their own cached value. -the PLB bus serializes reads and writes, so no read/write can interfere with each other.Article: 79862
"Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0502250306.7ecde5a1@posting.google.com... > "spartan" <startix_tm@nospam.yahoo.ca> wrote in message > news:<8a052749b6d8126f391f63acad407c36@localhost.talkaboutelectronicequipment.com>... >> I have been looking at the idea of implementing the microcontroller >> function into the FPGA using either Microblaze or NiosII. Does anyone >> have >> experience with these two products?How good is the software development >> environment. > > Both toolchains are based on GNU (GCC, binutils), so not many > differences. > > NIOS II comes with eclipse (an IDE), but you can download that > separatly for MicroBlaze anyway, >From press release: -------------------------------------------------------------------------- The Platform Studio tool suite automates a host of architecture-level design steps and offers a powerful new software environment based on the industry-standard Eclipse integrated design environment (IDE). The Platform Studio 6.3i release supports the Xilinx processor solutions, including the MicroBlaze and immersed PowerPC cores. -------------------------------------------------------------------------- What does the download of eclipse buy you? -Newman > >> Does it include breakpoints and examination of register and >> memory variables? I do appriciate to tell me your experience with >> Microblaze and NiosII. > > Both toolchains use GDB, so you get the same set of features. > > Cheers, > JonArticle: 79863
> Oh ok. Next state is not a registered output. The state machine is a 2 > process state machine ie the clocked process registers state from next > state, and the next state process is a combinatorial process. > > Can you help me to understand the problem and what has been > synthesised? Consider posting (part of) your code. It's easier to see what you do and to explain what is going on. JanArticle: 79864
"Petter Gustad" <newsmailcomp6@gustad.com> schrieb im Newsbeitrag news:87is4g6hup.fsf@filestore.home.gustad.com... > "spartan" <startix_tm@nospam.yahoo.ca> writes: > > This not a NIOS-II Microblaze issue, but a related Altera SOPC-Builder > vs. Xilinx XPS issue. > > In SOPC-Builder you can select if you want to generate Verilog or > VHDL. Since I'm using Synopsys VCS for my simualtions I've used > Verilog as target. All the generated files are Verilog source files. > > However, with Xilinx XPS it appears that only the top level module is > Verilog and it consists of several wrapper modules. The actual code > for the IP are written mostly in VHDL. Hence I can't use VCS for my > simulations (unless I spend several tens of thousands of dollars per > license to get the MX version). Alternatively, I'll have to do gate > level simulations only. > > Is my understanding correct, or is there some kind of conversion I can > do in XPS? > > Petter NO. There is not the difference is in the way the IP cores are delivered. SOPC ip cores are written in Perl and use special package "Europa" to generate either VHDL or Verilog, so thats why it is possible to choose either verilog or VHDL in SOPC in EDK the IP cores are delivered in either VHDL or Verilog or BOTH but mostly the IP cores are VHDL only. Only in the case ALL the IP cores you are using are delivered BOTH (that is both VHDL and Verilog versions are delivered) you can not create a full verilog simulation model, as there is never a conversion done from verilog to/from VHDL if the IP core used as HDL that matches the desired simulaton language it will be choosen, if it does not exist then resulting model will be mixed language. As the primary language for EDK cores is VHDL so you have no way to create full simulation model with pure verilog gate level sim could do, but thats not always fun I guess AnttiArticle: 79865
Hi FPGA people, I am trying to map my VHDL design on a Lattice-EC FPGA. (LFEC20E-5F672CES) The following error warning occurs: ********************************* Map checkpoint failed. Design's logic delay (97 percent of total delay) exceeds the 60 percent limit set in the map checkpoint options ********************************* Process Stopped. Done: failed with exit code: 0001. Unfortunately there is no direct "double click" HELP for this error message and I could not find any hint in the HELP menu. Has someone of you any idea what this message could mean ? Thank you in advance. Rgds AndrésArticle: 79866
Hi, Does anyone have already heard about VIE (Volontariat International en Entreprise: kind of professionnal volunteer in an other country than France, little bit like trainee) in their firm? Because as I am looking for a (first) job as possible in FPGA design, and also interested to do it abroad rather than France, I actually search informations about VIE and firms that use it because it seems to be a good ways to find out an interesting position. Regards, AlexisArticle: 79867
I've got some Spartan-3 IP from a vendor which uses a DCM. However, the DCM doesn't appear to be doing anything. The DCM is wired up as follows: 1) A global clock pin on the device drives signal CLK1, which goes into the IP block, where it connects to DCM/CLKIN . CLK1 is not used anywhere else in the design. 2) DCM/CLK0 drives signal CLK2 3) signal CLK2 drives an instantiated BUFG, and comes out as CLK3 4) CLK3 is connected back to DCM/CLKFB So far, so good; this is exactly the "On-chip with CLK0 feedback" setup shown in fig 15(a) on p23 of the datasheet (as an aside, 15(a) shows CLKIN coming from a BUFG, which doesn't seem to be correct in this case; it doesn't fit with the diagram on p30). The problem is that none of the other outputs from the DCM are used: all the clock outputs, apart from CLK0, are open. Now, I'm a bit rusty on Xilinx, but it seems to me that this DCM is doing nothing if the other clock outputs are unused. Is this correct? The DCM is set for 1X operation. Some other info: 1) CLK3 drives all the logic in the IP block 2) CLK3 is driven out of the IP block, and drives all my logic 3) My logic doesn't communicate with the IP, except via an asynchronous FIFO. The vendor expects my side of the FIFO to be driven with CLK3. TIA - RickArticle: 79868
"Richard Thompson" <nospam@nospam.com> schrieb im Newsbeitrag news:hkbu119khjirll6gmjc1qa0l0diekld4p1@4ax.com... > I've got some Spartan-3 IP from a vendor which uses a DCM. However, > the DCM doesn't appear to be doing anything. The DCM is wired up as > follows: > > 1) A global clock pin on the device drives signal CLK1, which goes > into the IP block, where it connects to DCM/CLKIN . CLK1 is not used > anywhere else in the design. > > 2) DCM/CLK0 drives signal CLK2 > > 3) signal CLK2 drives an instantiated BUFG, and comes out as CLK3 > > 4) CLK3 is connected back to DCM/CLKFB > > So far, so good; this is exactly the "On-chip with CLK0 feedback" > setup shown in fig 15(a) on p23 of the datasheet (as an aside, 15(a) > shows CLKIN coming from a BUFG, which doesn't seem to be correct in > this case; it doesn't fit with the diagram on p30). > > The problem is that none of the other outputs from the DCM are used: > all the clock outputs, apart from CLK0, are open. > > Now, I'm a bit rusty on Xilinx, but it seems to me that this DCM is > doing nothing if the other clock outputs are unused. Is this correct? > The DCM is set for 1X operation. > > Some other info: > > 1) CLK3 drives all the logic in the IP block > > 2) CLK3 is driven out of the IP block, and drives all my logic > > 3) My logic doesn't communicate with the IP, except via an > asynchronous FIFO. The vendor expects my side of the FIFO to be driven > with CLK3. > > TIA - > > Rick the DCM works as 0 - delay buffer thats the only function it has. that is not the same "doing nothing" CLK3 is buffered (0 delay!) version of CLK1 without the DCM the phase relation of CLK3 to CLK1 would be different and dependant on routing etc.. the DCM cancels out that dependancy AnttiArticle: 79869
Andrew Greensted <ajg112@ohm.york.ac.uk> writes: > Not sure who can do this, but I think this extra info for FPGA-FAQ > entry 0044 will help. [...] Thanks, I incorporated this into <http://www.fpga.de/tiki/tiki-index.php?page=XilinxSoftwareLinux> -HeinArticle: 79870
Right now I'm not using anything fancy. I created a 28x28 multiplier and a 56x56 adder with coregen and wired them together. I used the multiplier component and it is supposed to use the XtremeDSP slices. Maybe it is not wise enough to make use of other dedicated interconnects. I will look at this "XtremeDSP Design Consdierations". Thank you, DavidArticle: 79871
Xilinx V4 doc says one can expect 40% speed improvement over previous generation (and nearest competing FPGA as well? ;-)) Ok, but what kind of improvement may I get when upgrading from a V2Pro-7 to a V4-10? and what about -11 or latest -12 speed grades? any figure?Article: 79872
On Fri, 25 Feb 2005 15:26:35 +0100, "Antti Lukats" <antti@openchip.org> wrote: >the DCM works as 0 - delay buffer thats the only function it has. >that is not the same "doing nothing" >CLK3 is buffered (0 delay!) version of CLK1 >without the DCM the phase relation of CLK3 to CLK1 would >be different and dependant on routing etc.. the DCM cancels >out that dependancy > >Antti In this case, there seems to be no point in having a 0-delay buffer. The only place that CLK1 is used is at the DCM's CLKIN pin, so the whole setup seems pointless to me. There's a second issue here, which is that zeroing out a delay (if that was the IP vendor's intent) is dangerous anyway. The only place at which the delay is zeroed is at the DCM's inputs; it's not going to be 'zero' anywhere else on the die. RickArticle: 79873
"Richard Thompson" <nospam@nospam.com> schrieb im Newsbeitrag news:4ffu1157bk82ksv2nb9s5sseu3215moamo@4ax.com... > On Fri, 25 Feb 2005 15:26:35 +0100, "Antti Lukats" > <antti@openchip.org> wrote: > > >the DCM works as 0 - delay buffer thats the only function it has. > >that is not the same "doing nothing" > >CLK3 is buffered (0 delay!) version of CLK1 > >without the DCM the phase relation of CLK3 to CLK1 would > >be different and dependant on routing etc.. the DCM cancels > >out that dependancy > > > >Antti > > In this case, there seems to be no point in having a 0-delay buffer. > The only place that CLK1 is used is at the DCM's CLKIN pin, so the > whole setup seems pointless to me. > > There's a second issue here, which is that zeroing out a delay (if > that was the IP vendor's intent) is dangerous anyway. The only place > at which the delay is zeroed is at the DCM's inputs; it's not going to > be 'zero' anywhere else on the die. > > Rick you probably right, if there is not external to FPGA circuitry driven by CLK1 then DCM isnt needed here, could be just BUFG as well anttiArticle: 79874
Rick, Oh, but it is. The idea behind the feedback is to cause there to be a known phase realtionship so one can do system synchronous IO. The timing is within the data sheet limits for the distribution over the clock tree to the IOBs. But, I agree, with async fifo's it looks like this is just a leftover from another core that was left in. Austin Richard Thompson wrote: > On Fri, 25 Feb 2005 15:26:35 +0100, "Antti Lukats" > <antti@openchip.org> wrote: > > >>the DCM works as 0 - delay buffer thats the only function it has. >>that is not the same "doing nothing" >>CLK3 is buffered (0 delay!) version of CLK1 >>without the DCM the phase relation of CLK3 to CLK1 would >>be different and dependant on routing etc.. the DCM cancels >>out that dependancy >> >>Antti > > > In this case, there seems to be no point in having a 0-delay buffer. > The only place that CLK1 is used is at the DCM's CLKIN pin, so the > whole setup seems pointless to me. > > There's a second issue here, which is that zeroing out a delay (if > that was the IP vendor's intent) is dangerous anyway. The only place > at which the delay is zeroed is at the DCM's inputs; it's not going to > be 'zero' anywhere else on the die. > > Rick
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