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Pablo Bleyer Kocik wrote: > Hello people. > > Since some of you started asking about the Java programs I use to > control the BSC registers in my designs that I mentioned in a post last > week, I have released them as a Java.net project. The official URL is > http://jjtag.dev.java.net/, but while it receives approval you can > access a temporary repository at my web site, http://bleyer.org/jjtag/. > > Basically, the tool consists of a JTAGController class that defines > the API and works over 'String' or 'Bits' objects. There is an example > for a JNI Wiggler-like parallel port interface that implements the TAP > pins control routines. There is also a 'Scan' utility class that > packs/unpacks JTAG bitstreams and aids in the development of boundary > scan register descriptions. > > The complete package has been licensed under the BSD license. It has > been used successfully to implement an ARM JTAG/ICE debugger and debug > interfaces for a couple of custom FPGA designs. > > I also have a USB JTAGController class that uses my jd2xx package with > FTDI USB chips via their MPSSE interface (http://jd2xx.dev.java.net/). > I look forward to release it as soon as I work out some licensing > issues with my previous employer (which reminds me -- I could really > use some knowledge about currently open positions ;) ). > > Don't hesitate to write me if you have any questions or problems using > it. > > Enjoy. > > -- > PabloBleyerKocik / > pablo /"Simplicity is prerequisite for reliability." > @bleyer.org / -- Edsger Wybe Dijkstra > Hi Pablo, Nice work, we will try it! Note, maybe change the jd2xx-msw-20050803.zip by jd2xx-msw-20050308.zip . ;-) Laurent www.amontec.comArticle: 80626
Oops... I thought the aliens left me here in August after abducting and doing those terrible things to me ;) Thanks for noticing that. Should be fixed by now. -- /"Scilab is french, and 'homeland security' PabloBleyerKocik / will put spy cams in your bog, and swap your pablo / wife for an android if you use it." @bleyer.org / -- simon at comp.soft-sys.math.scilabArticle: 80627
Giorgos P. wrote: > Hello, > > I am interested in opinions concerning advantages and disadvantages of the > hardware (FPGAs) and developing software (Quartus vs ISE) for high-end (very > demanding designs). > I was under the impression that xilinx was ahead but I've done some reading > lately and StratixII seems to have made a step ahead in comparison to > Virtex4. The devices I am interested in are Stratix and StratixII from one > side and VirtexII pro, Virtex4 one the other. > > There is not one specific parameter that I need to investigate. Procesing > power, memory and I/O data rates are all significant. > > Of cource the role of the EDA tools is important so if someone could give me > his opinion one advantages and week points of each one I would be grateful. Howdy Giorgos, Asking such generic questions are bound to either get you generic answers, or FUD from the vendors. The short answer is that after availability, quantity, price, and features are all factored in, each has its own strengths and weaknesses, yet each is also a capable FPGA. For some things, Stratix II will be fastest, other things Virtex-4 will be fastest, and a few others, VirtexII-Pro will be fastest. Without a fair amount of detail on the "specific parameters" of your design, it is impossible to guess which might match up best. Or beter yet, get the tools for both and try targetting your design to each. Good luck, MarcArticle: 80628
Laurent Gauch wrote: > Andy Main wrote: > >> > I looked on the web for XCF01SVO20C and got a web price of $3.15 >> >>> If this is expensive to you, I don't see what you're going to do with >>> the AT29 flash. This is a 1Mbit part big enough to program about 5 >>> of your XC2S15's if you chain them. It has JTAG and works with the >>> Xilinx iMPACT software. Good luck doing better with less effort. >> >> >> >> Much better, though I can't find any in the UK (RS/Farnell) - only the >> huge Virtex proms that made me think all this in the fist place. If >> anybody knows a suitable supplier for low quantity purchases please >> let me know. I'd be very grateful. >> >> Andy. > > > Hi Andy, > > Maybe goto www.nuhorizons.com > > Laurent Gauch > www.amontec.com Looked good until I got to the checkout - $75 delivery charge for 8 of these!! Thanks anyway, Andy.Article: 80629
Eric Smith <eric@brouhaha.com> wrote: >Is there any reason why using an LM317S adjustable linear regulator with >1% resistors wouldn't be satisfactory for the Spartan 3 power supplies, >particularly Vccint and Vccaux? > >I have a cost-sensitive application for which the LM317S looks to be >much less expensive than using fixed-output LDO regulators, e.g., >$0.58 for the LM317S vs. $4.45 for an LP3881ES-1.2 for Vccint. Recently someone posted mentioning a Spartan 3 development board available from Altium (for their Protel/Nexar stuff). You can download a full design package for this board and interestingly they use the same LDO adjustable regulator for all supplies. I can't remember the exact part, an LM1048 or LT1048? something like that. For Vccint they pull the regulator ground pin slightly below ground by tapping down the -ve rail from a MAX232 type driver on the board.Article: 80630
On Wed, 09 Mar 2005 15:25:45 +0700, Rudolf Usselmann wrote: > B. Joshua Rosen wrote: >> >> They screwed up the installer on 7.1 and made it distribution dependent. >> Specifically the installer requires some out of date libraries. I wasn't >> able to install 7.1 on Fedora Core 3 or Mandrake 10.1 because of library >> issues. I ended up putting Whitebox Linux on one of my older machines >> (Whitebox is RHEL 3.0) and doing the install there. Once I'd done the >> install on the WB system I rsynced the directory over to my FC3 systems >> and it works fine. The tools themselves don't seem to have any >> distribution dependencies, the cock-up is limited to the installer. > > > I wonder if xilinx could provide an updated installer (only) > so that we all could install the tools on our favorite linux > distro. > > It should be just a recompile of xilsetup ... > > How about it ? > > I'll volunteer to beta test on 32 and 64 bit AMD platforms ... > > Best Regards, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis I've filed a webcase for Fedora Core 3. I've suggested that they statically link the installer so that it's not library dependent. It would probably be useful if other people would file cases for other distributions. There is no reason for there to be any distribution dependencies, the code can either be statically linked or the libraries included with the tools. In fact I think they have done the right thing when it comes to the tools themselves, I'm not having any trouble running them on Fedora Core 3. It is just the installer that has a problem.Article: 80631
"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:86OWd.7125$MK5.4250@newsfe5-gui.ntli.net... > > "Hendra" <u1000393@email.sjsu.edu> wrote in message > news:1110153552.755274.22750@l41g2000cwc.googlegroups.com... > >> That's a very good point, Kryten! I am very disappointed with the board >> layout of Digilent S3 starter kit. Its board layout should have been >> the same with their D2SB and D2FT board. D2SB and D2FT are bare bone >> FPGA boards. > > Yes, the whole point of buying an FPGA board is because you have your own > purposes for those pins. > > But there's always some pointy haired sales droid who wants more features. > > > I never thought I'd object to something having more stuff for less than > half the price of a competing product, but I can't help suspecting some > unconventional business ethics here. > I'd expect the Digilent board to cost at least three times its price, > given that it has more bits than the > 210 USD BurchEd board. from typical > mark-ups (3x), I'd say the board was being sold at cost price. In which > case, who is paying the production costs? > > It is okay for Xilinx to give away software only they produce, but if they > are paying Digilent to sell boards at cost then it is an underhand blow to > the other manufacturers of Xilinx dev kits. Surely that would put them out > of business eventually. Maybe Xilinx want to reduce the number of players > to just their own favourite? Look at where Digilentinc came from, education market. Basically boards that a student can afford to buy themselves. Its lot easier for lecturers/tutors if the board has a basic set of fixed peripherals. Less likely to get fpgas blown up as well. More advanced / capable students can design and build their own addons. I'd expect Digilentinc / Xilinx are selling a lot more than Tony Birch. Also for the future expose as many students as possible, so they become fimiliar with your products. AFAIK here in Australia most universities use Xilinx products. How long before Altera comes out with a similar competing kit with their newer parts rather than their existing student kits based on old products? AlexArticle: 80632
"Hendra" <u1000393@email.sjsu.edu> wrote in message news:1110139344.378413.55420@o13g2000cwo.googlegroups.com... > KJ wrote: >> For those (like me) who has no experience in FPGA programming, can > you >> suggest which SW tool(s) (free or low-cost) would be good to start > with for >> vendor independent learning ? > > Xilinx offers their free version of synthesis tool called Webpack which > can be downloaded at www.xilinx.com/ise/webpack . In the webpage, you > can also download a third party simulator called ModelSim for free. The > free software are more than enough for beginners. Webpack supports up > to 1.5 Million gates, which is quite HUGE. ModelSim free version > simulates at full speed up to 500 lines of code, after that it slows > down but still works. If you want to spend a little bit of money you > can buy Xilinx 6.3i Student Version from Prentice Hall > vig.prenhall.com/catalog/academic/product/0,1144,0131858394,00.html >>From what I have been told, the Student Version is basically the same > with the professional version called Xilinx ISE BaseX but at huge > discount price. The only limitation is you can not use it for > commercial purposes and you are not eligible for tech support. > The software are very much vendor independent, as long as you don't use > the vendor specific primitive library or the Core Generator. Just use > standard Verilog or VHDL keywords. > Altera also offers their free old software called MaxPlusII and newer > one called Quartus. But the simulator that comes with MaxPlusII has > severe limitation, it doesn't supports testbench at all. I won't > recommend it for anyone. Perhaps the free version of Quartus doesn't > have such limitaton, I don't know, you can try. > > Hendra I'm wondering if xilinx will keep supplying modelsim with webpack for 7.1 now they have gone back to having a builtin simulator ? >Article: 80633
John_H wrote: > If you want the exact average frequency, you can also have a smaller > implementation with more deterministic performance (when you have a 13-clock > cycle versus when you have a 14-clock cycle) by implementing a 48/625 DDS > instead of a 329853488/2^32 DDS. Rather than using a 32-bit accumulator, > use a 10-bit accumulator and add 48 on most cycles but when the accumulator > overflows, add 48+1024-625=447 for the single cycle instead. Coded > properly, the only extra resources needed in most FPGAs is the overflow > detect; the two constants are hard-coded and selected with a single bit > within the accumulator logic. > > Closer to 50% duty cycle with the MSbit of the accumulator can be achieved > with other tricks. When I want to generate a fixed fractional frequency like this rather than generating a general purpose DDS, I usually code it with two counters. First I figure the divide ratio as a compound fraction, in this case 13 1/48. Then the first counter is coded as divide by 13 or 14 with 1 input to select the divide ratio. The second counter divides the output of the first by 48 in this case and selects the divide-by-14 mode of the first counter every 48th cycle as it wraps. When I'm looking for a baud rate clock, I generally want a single cycle output to use as a clock enable, so the wrap of the first counter is easy to use for this. Generating a 50% (mostly) duty cycle is not too hard for the divide by 13 or 14 counter. This whole discussion is of course off the original thread, which was about generating a stable (as in low jitter) clock using the DCM's.Article: 80634
Jon Elson wrote: > Hello, all, > > I am working on an update for a board that now uses an original 5-V Spartan > (XCS30) part. To reduce cost, I'm looking at using the Spartan II XC2S30 > part, which is less than half the price. (I'd go with the Spartan IIE, > but the smallest > is 50K gates, and config bitstream is about double the 2S30's > requirement, which > negates the price advantage.) Be sure your design fits in the part you are choosing, first. Note that the XCS30 has a lot more CLB's than the XC2S30. The "30" K-gate number in the Spartan II comes partially from the block RAM you didn't have in the older part. Look at PlatformFlash (1 Mbit minimum size at about $3 in quantity). If you go this way the Spartan IIE looks better unless you have 5V interfacing issues. Using a cheaper PROM loses its advantage if you need to add a CPLD to interface it. Also the PlatformFlash is easy to program in system using iMPACT. > Anyway, there are some 512KBit serial PROMs > available from some other makers that are 1/10th the cost of the Xilinx > parts. > But, they max out at 400 Kbits/second, and the SpartanII starts > configuring at > 2.5 MBits /second in master serial mode. I think I have come up with a very > simple circuit to divide my system clock down and sync INIT/ to it, so > that I can > run the SpartanII in slave serial mode with a clock rate appropriate for > the slow > SPROM. I think I can do it in 2 74HCxx packages. Does anyone have any > comments > on this? Have you done something similar? > Before the PlatformFlash came along I used Atmel Dataflash parts for large bitstreams (16Mbits +), but in that case I had a tiny micro to help with the job. For something like a 2-wire serial EEPROM (24C512) you could add a PIC micro for under $1 and get the job done if you're not too worried about the total configuration time. > (This particular product has no CPU onboard. I suppose I could come up > with a way > to configure the FPGA from a host CPU, but there are a few reasons I > might want > to avoid that.) > > Thanks, > > JonArticle: 80635
Well yesterday I tried something like :
const XIo_Address sflag_PORT = XPAR_DSBRAM_IF_CNTLR_0_BASEADDR + 0;
Xuint32 sflag;
sflag = XIo_In32( (XIo_Address)sflag_PORT);
putnum(sflag);
//////////////////////////////////////
it still hangs :(
is there someone that encountered this problem .. because the above I almost
copy pasted out of an example code
thx in advance !
"Mindroad" <mindroad@hotmail.com> schreef in bericht
news:422dfa37$0$20677$ba620e4c@news.skynet.be...
> Hi,
>
> After I builded my design in EDK and made a toplevel VHDL in ISE, I
started
> writing code for both PPC on my V2P20 ... the first PPC serves as an
> Communication unit which transfers data in between memories, accessible by
> external device ... I have no problem whatsoever accessing these memories,
> either on opb or plb busses
> When I started the part of interconnecting the two PPC with a BRAM memory
> using DSOCM I encountered the following problem, which up to know I cannot
> solve (this is the first time I design on FPGA) ...
>
> To access the BRAM from the first PPC serving as Comm Unit I used the code
> which worked for accessing memories on the PLB since I suppose the
> addressing of memories is always in the same way, as if we address one big
> memory
>
> code :
> Xuint32 * bram_Ptr = XPAR_BRAM_BASE_ADDR;
> Xuint32 value = *bream_Ptr;
>
> When I download the bit file on the FPGA, the system hangs, when executing
> these commands
>
> can someone help me with this problem, I spend some time looking for the
> solution and I found some macros in xio.h, but I have no clue how to use
> them, and when I look into application notes, it appears nothing is ever
> said about how accessing BRAM, so it must be straightforward
>
> thx in advance
>
> could be I miss some parameters or connections in the MHS file, but I
doubt
> it since all should almost be set by default
>
> BEGIN dsocm_v10
> <--- connected to the PPC405 through bus interface
> PARAMETER INSTANCE = dsocm_v10_0
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_DSCNTLVALUE = 0x85
> PORT DSOCM_Clk = sys_clk
> PORT sys_rst = sys_rst_l
> END
>
> BEGIN dsbram_if_cntlr
> PARAMETER INSTANCE = dsbram_if_cntlr_0
> PARAMETER HW_VER = 3.00.a
> PARAMETER C_BASEADDR = 0xF0000000
> PARAMETER C_HIGHADDR = 0xF0001fff
> BUS_INTERFACE DSOCM = dsocm_v10_0
> BUS_INTERFACE PORTA = dsbram_if_cntlr_0_porta
> END
>
> BEGIN bram_block
> PARAMETER INSTANCE = bram_block_0
> PARAMETER HW_VER = 1.00.a
> BUS_INTERFACE PORTA = dsbram_if_cntlr_0_porta
> BUS_INTERFACE PORTB = dsbram_if_cntlr_1_porta
> END
>
>
>
>
> could be I made some mistake in my linker script :
>
> _STACK_SIZE = 1k;
> _DOCM_SIZE = 8k;
>
> MEMORY
> {
> plb_bram_if_cntlr_1_bram : ORIGIN = 0xFFFF0000, LENGTH = 16K
> plb_bram_if_cntlr_2_bram : ORIGIN = 0xFFFF8000, LENGTH = 32K
> dsbram_if_cntlr_0_porta : ORIGIN = 0xF0000000, LENGTH = 8K
> }
> ...
>
>
Article: 80636Hi everyone... I wonder if there is any simple way to send the data from a block-ram to the RS232-interface, without the need to write all the RS232 VHDL-code myself! Thanks everyone!Article: 80637
B. Joshua Rosen wrote: > On Wed, 09 Mar 2005 15:25:45 +0700, Rudolf Usselmann wrote: > > >>B. Joshua Rosen wrote: >> >>>They screwed up the installer on 7.1 and made it distribution dependent. >>>Specifically the installer requires some out of date libraries. I wasn't >>>able to install 7.1 on Fedora Core 3 or Mandrake 10.1 because of library >>>issues. I ended up putting Whitebox Linux on one of my older machines >>>(Whitebox is RHEL 3.0) and doing the install there. Once I'd done the >>>install on the WB system I rsynced the directory over to my FC3 systems >>>and it works fine. The tools themselves don't seem to have any >>>distribution dependencies, the cock-up is limited to the installer. >> >> >>I wonder if xilinx could provide an updated installer (only) >>so that we all could install the tools on our favorite linux >>distro. >> >>It should be just a recompile of xilsetup ... >> >>How about it ? >> >>I'll volunteer to beta test on 32 and 64 bit AMD platforms ... >> >>Best Regards, >>rudi >>============================================================= >>Rudolf Usselmann, ASICS World Services, http://www.asics.ws >>Your Partner for IP Cores, Design, Verification and Synthesis > > > I've filed a webcase for Fedora Core 3. I've suggested that they > statically link the installer so that it's not library dependent. It would > probably be useful if other people would file cases for other > distributions. There is no reason for there to be any distribution > dependencies, the code can either be statically linked or the libraries > included with the tools. In fact I think they have done the right thing > when it comes to the tools themselves, I'm not having any trouble running > them on Fedora Core 3. It is just the installer that has a problem. Well, they also screwed up the WebPack installer apparently ;( A don't have any RHEL 3.0 handy to install and copy, I'll have to find another way. SylvainArticle: 80638
> I wonder if there is any simple way to send the data from a block-ram to
> the RS232-interface, without the need to write all the RS232 VHDL-code
> myself!
There you go. And can we now stop requesting RS232 stuff? ;)
Jan
================ filename="EIA232_TX_bridge.vhd"
--
-- ***Author***
-- Jan De Ceuster
--
-- *** File ***
-- EIA232_TX_bridge.vhd
--
-- *** Entity ***
-- EIA232_TX_bridge
--
-- *** Port list ***
-- nrst (in, 1) Active low reset
-- clk (in, 1) System Clock
--
-- EIA232_TXD (in, 1) EIA232 Receive Serial Data from PC
-- EIA232_CTS (out, 1) EIA232 Stop Receiving
--
-- ParallelIN_Data (out, 8) ParallelIN sends the data from EIA232 interface.
-- ParallelIN_Ack (out, 1) protocol: synchronous Full Handshake, device
-- ParallelIN_Req (in, 1) is slave.
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_arith.all;
library work;
use work.shift_registers.all;
use work.EIA232.all;
entity EIA232_TX_bridge is
generic (
DATASIZE : in integer := 8;
CLKFREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_TXD : in std_logic;
EIA232_CTS : out std_logic;
ParallelIN_Data : out std_logic_vector(DATASIZE-1 downto 0);
ParallelIN_Req : in std_logic;
ParallelIN_Ack : out std_logic
);
end EIA232_TX_bridge;
architecture RTL of EIA232_TX_bridge is
constant BITCOUNTER_SIZE : integer := DATASIZE - 1;
constant TIMECOUNTER_SIZE : integer := CLKFREQ/BAUDRATE-1;
constant HALF_TIMECOUNTER_SIZE : integer := TIMECOUNTER_SIZE/2 - 1;
signal timecounter : integer range 0 to TIMECOUNTER_SIZE;
signal bitcounter : integer range 0 to DATASIZE-1;
signal ParallelIN_Data_reg : std_logic_vector(1 to DATASIZE);
signal EIA232State, nextEIA232State : EIA232State_type;
signal timecounter_pulse : std_logic;
signal StartReceive : std_logic;
signal sync_EIA232_TXD : std_logic_vector(2 downto 1);
signal faling_edge_EIA232_TXD : boolean;
signal buffer_empty : boolean;
begin
process (EIA232State, StartReceive, bitcounter)
begin
nextEIA232State <= EIA232State;
case EIA232State is
when E_EIA232State_Waiting =>
if StartReceive = '1' then
nextEIA232State <= E_EIA232State_Start;
end if;
when E_EIA232State_Start =>
nextEIA232State <= E_EIA232State_Data;
when E_EIA232State_Data =>
if bitcounter = 0 then
nextEIA232State <= E_EIA232State_Stop;
end if;
when E_EIA232State_Stop =>
nextEIA232State <= E_EIA232State_Waiting;
when others =>
end case;
end process;
-- sample signal into flipflops
process (clk)
begin
if rising_edge(clk) then
ShiftL2H(EIA232_TXD,sync_EIA232_TXD);
end if;
end process;
faling_edge_EIA232_TXD <= sync_EIA232_TXD(sync_EIA232_TXD'high-1) = '0'
and sync_EIA232_TXD(sync_EIA232_TXD'high) = '1';
timecounter_pulse <= '1' when timecounter = 0 else '0';
process (clk, nrst)
begin
if nrst = '0' then
timecounter <= TIMECOUNTER_SIZE;
StartReceive <= '0';
elsif rising_edge(clk) then
-- endless timer with conditional preload (when detecting a startbit)
-- StartReceive indicates the detection of the startbit
if faling_edge_EIA232_TXD -- faling edge TXD,
and nextEIA232State = E_EIA232State_Waiting then -- detect start bit
timecounter <= HALF_TIMECOUNTER_SIZE;
StartReceive <= '1';
elsif timecounter = 0 then -- counter reset
timecounter <= TIMECOUNTER_SIZE;
StartReceive <= '0';
else
timecounter <= timecounter - 1; -- count down
end if;
end if;
end process;
process (clk, nrst)
begin
if nrst = '0' then
EIA232State <= E_EIA232State_Waiting;
ParallelIN_Data_reg <= (others => '-');
bitcounter <= BITCOUNTER_SIZE;
elsif rising_edge(clk) then
if timecounter_pulse = '1' then
EIA232State <= nextEIA232State;
bitcounter <= BITCOUNTER_SIZE;
-- shift register
ShiftL2H(sync_EIA232_TXD(sync_EIA232_TXD'high),ParallelIN_Data_reg);
if EIA232State = E_EIA232State_Start
or EIA232State = E_EIA232State_Data then
-- counter for the shiftregister
if bitcounter = 0 then
bitcounter <= BITCOUNTER_SIZE;
else
bitcounter <= bitcounter - 1;
end if;
end if;
end if;
end if;
end process;
process (clk, nrst)
begin
if nrst = '0' then
buffer_empty <= TRUE;
EIA232_CTS <= '1';
ParallelIN_Ack <= '0';
elsif rising_edge(clk) then
if buffer_empty then
EIA232_CTS <= '0';
else
EIA232_CTS <= '1';
end if;
if EIA232State = E_EIA232State_Data then
buffer_empty <= FALSE;
end if;
-- Output the shiftregister directly.
if timecounter_pulse = '1' and EIA232State = E_EIA232State_Stop then
ParallelIN_Data <= ParallelIN_Data_reg;
end if;
-- The shiftregister now contains the received byte.
-- => give an ack for 1 clock cycle (done with timecounter_pulse)
if ParallelIN_REQ = '1' and not buffer_empty and EIA232State = E_EIA232State_Waiting then
ParallelIN_Ack <= '1';
buffer_empty <= TRUE;
else
ParallelIN_Ack <= '0';
end if;
end if;
end process;
end RTL;
======================== filename="EIA232_package.vhd"
--
-- ***Author***
-- Jan De Ceuster
--
-- *** File ***
-- EIA232_constants.vhd
--
-- *** Entity ***
--
-- *** Port list ***
--
-- *** Description ***
--
-- *** History ***
--
library ieee;
use ieee.std_logic_1164.all;
package EIA232 is
-- enumerations
type EIA232State_type is (E_EIA232State_Waiting, E_EIA232State_Start,
E_EIA232State_Data, E_EIA232State_Stop);
-- constants
-- functions
-- procedures
-- components
component EIA232_TX_bridge
-- receive data via a FullHndshk protocol
-- bridge is master on EIA232 lines
generic (
DATASIZE : in integer := 8; -- size can be anything from 5 to 8
CLKFREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_TXD : in std_logic;
EIA232_CTS : out std_logic;
ParallelIN_Data : out std_logic_vector(DATASIZE-1 downto 0);
ParallelIN_Req : in std_logic;
ParallelIN_Ack : out std_logic
);
end component;
component EIA232_RX_bridge
-- send data via a FullHndshk protocol
-- bridge is master on EIA232 lines
generic (
DATASIZE : in integer := 8; -- size can be anything from 5 to 8
CLKFREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_RXD : out std_logic;
EIA232_RTS : in std_logic;
ParallelOUT_Data : in std_logic_vector(DATASIZE-1 downto 0);
ParallelOUT_Req : in std_logic;
ParallelOUT_Ack : out std_logic
);
end component;
component EIA232_ASCIIfileio
-- model using files to send and get ASCII data to/from the system.
generic (
DATASIZE : in integer := 8; -- size can be anything from 5 to 8
CLKFREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200;
READFILE : string := "";
WRITEFILE : string := ""
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_RXD : in std_logic;
EIA232_RTS : out std_logic;
EIA232_TXD : out std_logic;
EIA232_CTS : in std_logic;
done : out boolean := false
);
end component;
end EIA232;
package body EIA232 is
end EIA232;
================== filename="EIA232_RX_bridge.vhd"
--
-- ***Author***
-- Jan De Ceuster
--
-- *** File ***
-- EIA232_RX_bridge.vhd
--
-- *** Entity ***
-- EIA232_RX_bridge
--
-- *** Port list ***
-- nrst (in, 1) Active low reset
-- clk (in, 1) System Clock
--
-- EIA232_RXD (out, 1) EIA232 Transmit Serial Data to PC
-- EIA232_RTS (in, 1) EIA232 Stop Sending
--
-- ParallelOUT_Data (in, 8) ParallelOUT sends the data to EIA232 interface.
-- ParallelOUT_Ack (out, 1) protocol: synchronous Full Handshake, device is slave
-- ParallelOUT_Req (in, 1)
--
-- *** Description ***
-- This block will translate the parallel data from a generic interface to
-- a serial output according the EIA232 standard with RXD and RTS.
-- The size of the parallel data (generic paramter DATASIZE) can be anything
-- from 5 to 8. This is also as specified in the EIA232 standard.
-- One start and stopbit is provided.
-- The generic parameter CLK_DIV is used to set the correct baudrate:
-- baudrate = inputfreq/CLK_DIV
--
-- *** History ***
-- 001 27-06-2003 Initial version
-- Fully tested and optimized
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_arith.all;
library work;
use work.shift_registers.all;
use work.EIA232.all;
entity EIA232_RX_bridge is
generic (
DATASIZE : in integer := 8; -- size can be anything from 5 to 8
CLKFREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_RXD : out std_logic;
EIA232_RTS : in std_logic;
ParallelOUT_Data : in std_logic_vector(DATASIZE-1 downto 0);
ParallelOUT_Req : in std_logic;
ParallelOUT_Ack : out std_logic
);
end EIA232_RX_bridge;
architecture RTL of EIA232_RX_bridge is
constant TIMECOUNTER_SIZE : integer := integer(real(CLKFREQ/BAUDRATE)-1.0);
signal timecounter : integer range 0 to TIMECOUNTER_SIZE;
signal bitcounter : integer range 0 to DATASIZE;
signal EIA232ShiftRegister : std_logic_vector(1 to DATASIZE);
signal EIA232State, nextEIA232State : EIA232State_type;
signal StartSending : std_logic;
signal timecounter_pulse : std_logic;
signal sync_EIA232_RTS : std_logic_vector(3 downto 1);
begin
-- The EIA232State statemachine controls the correct flow for the start, data
-- and stop bit(s).
process (EIA232State, StartSending, bitcounter)
begin
nextEIA232State <= EIA232State;
case EIA232State is
when E_EIA232State_Waiting =>
-- Req for sending data received.
if StartSending = '1' then
nextEIA232State <= E_EIA232State_Start;
end if;
when E_EIA232State_Start =>
nextEIA232State <= E_EIA232State_Data;
when E_EIA232State_Data =>
-- Last databit send.
if bitcounter = DATASIZE and StartSending = '0' then
nextEIA232State <= E_EIA232State_Waiting;
end if;
when others =>
end case;
end process;
-- Generate a pulse when timecounter is 0.
timecounter_pulse <= '1' when timecounter = 0 else '0';
-- Sample the inputsignal from physical EIA232 interface into a flipflop.
process (clk)
begin
if rising_edge(clk) then
ShiftL2H(EIA232_RTS,sync_EIA232_RTS);
end if;
end process;
process (clk,nrst)
begin
if nrst = '0' then
timecounter <= TIMECOUNTER_SIZE;
ParallelOUT_Ack <= '0';
StartSending <= '0';
EIA232ShiftRegister <= (others => '1');
elsif rising_edge(clk) then
ParallelOUT_Ack <= '0';
-- Counter to devide the clk input.
if timecounter_pulse = '1' then
timecounter <= TIMECOUNTER_SIZE;
else
timecounter <= timecounter - 1;
end if;
case EIA232State is
when E_EIA232State_Waiting =>
-- Req received and ready to transmit data.
if StartSending = '0' and ParallelOUT_Req = '1'
and sync_EIA232_RTS(sync_EIA232_RTS'high) = '0' then
-- Load the shiftregister
EIA232ShiftRegister(1 to DATASIZE) <= ParallelOUT_Data;
ParallelOUT_Ack <= '1';
StartSending <= '1';
end if;
when E_EIA232State_Start | E_EIA232State_Data =>
StartSending <= '0';
-- The shiftregister can shift every timecounter_pulse.
-- This register runs on clk because it must be possible to load
-- external data assynchronous to timecounter_pulse.
if timecounter_pulse = '1' then
ShiftL2H('1',EIA232ShiftRegister);
end if;
when others =>
StartSending <= '0';
end case;
end if;
end process;
process (clk,nrst)
begin
if nrst = '0' then
EIA232_RXD <= '1';
EIA232State <= E_EIA232State_Waiting;
bitcounter <= 0;
elsif rising_edge(clk) then
if timecounter_pulse = '1' then
EIA232State <= nextEIA232State;
case nextEIA232State is
when E_EIA232State_Waiting =>
EIA232_RXD <= '1';
when E_EIA232State_Start =>
EIA232_RXD <= '0';
when E_EIA232State_Data =>
EIA232_RXD <= EIA232ShiftRegister(DATASIZE);
if bitcounter = DATASIZE then
bitcounter <= 0;
else
bitcounter <= bitcounter + 1;
end if;
when others =>
end case;
end if;
end if;
end process;
end RTL;
================= filename="EIA232_ASCIIfileIO.vhd"
--
-- ***Author***
--
-- *** File ***
-- EIA232_fileio.vhd
--
-- *** Entity ***
-- EIA232_fileio
--
-- *** Port list ***
--
-- *** Description ***
--
-- *** History ***
-- 001
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_arith.all;
library nicethings;
use nicethings.ASCII.all, nicethings.overloaded_std_logic_arith.all;
library communication;
use communication.EIA232.all;
entity EIA232_ASCIIfileio is
generic (
DATASIZE : in integer := 8; -- size can be anything from 5 to 8
CLKFREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200;
READFILE : string := "";
WRITEFILE : string := ""
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_RXD : in std_logic;
EIA232_RTS : out std_logic;
EIA232_TXD : out std_logic;
EIA232_CTS : in std_logic;
done : out boolean := FALSE
);
end EIA232_ASCIIfileio;
architecture model of EIA232_ASCIIfileio is
--signals of the EIA232 side
signal in_Data : std_logic_vector(DATASIZE-1 downto 0);
signal in_REQ, in_ACK : std_logic;
signal out_Data : std_logic_vector(DATASIZE-1 downto 0);
signal out_REQ, out_ACK : std_logic;
signal RXstate : integer := 0;
signal TXstate : integer := 0;
begin
TX_test : EIA232_TX_bridge
generic map (DATASIZE,CLKFREQ,BAUDRATE)
port map (nrst=>nrst,clk=>clk,
EIA232_TXD=>EIA232_RXD,EIA232_CTS=>EIA232_RTS,
ParallelIN_Data=>in_Data,ParallelIN_Req=>in_REQ,
ParallelIN_Ack=>in_ACK);
RX_test : EIA232_RX_bridge
generic map (DATASIZE,CLKFREQ,BAUDRATE)
port map (nrst=>nrst,clk=>clk,
EIA232_RXD=>EIA232_TXD,EIA232_RTS=>EIA232_CTS,
ParallelOUT_Data=>out_Data,ParallelOUT_Req=>out_REQ,
ParallelOUT_Ack=>out_ACK);
RX_SIDE : if READFILE /= "" generate
-- EIA232 RX side
process (clk, nrst)
file Fread : TEXT open READ_MODE is READFILE;
variable L : line;
variable char : character;
begin
if nrst = '0' then
out_REQ <= '0';
out_Data <= (others => '0');
RXstate <= 0;
done <= FALSE;
elsif rising_edge(clk) then
case RXstate is
when 0 =>
readline(Fread,L);
RXstate <= 1;
when 1 =>
if L'length = 0 then
char := LF;
else
read(L,char);
end if;
out_REQ <= '1';
out_Data <= conv_std_logic_vector(char,DATASIZE-1);
RXstate <= 2;
when 2 =>
if out_ACK = '1' then
out_REQ <= '0';
if char = LF then
if endfile(Fread) then
RXstate <= 3;
else
readline(Fread,L);
RXstate <= 1;
end if;
else
RXstate <= 1;
end if;
end if;
when others =>
done <= TRUE;
end case;
end if;
end process;
end generate;
TX_SIDE : if WRITEFILE /= "" generate
-- EIA232 TX side
process (clk, nrst)
file Fwrite : TEXT open WRITE_MODE is WRITEFILE;
variable L : line;
variable char : character;
begin
if nrst = '0' then
in_REQ <= '0';
TXstate <= 0;
elsif rising_edge(clk) then
case TXstate is
when 0 =>
in_REQ <= '1';
TXstate <= 1;
when 1 =>
if in_ACK = '1' then
in_REQ <= '0';
TXstate <= 0;
if in_DATA /= C_ASCII_LF then
write(L,conv_character(in_DATA));
else
writeline(Fwrite,L);
end if;
end if;
when others =>
end case;
end if;
end process;
end generate;
end model;
Article: 80639"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:2fvXd.6$ox4.2@newsfe4-gui.ntli.net... > > "Pete Fraser" <pfraser@covad.net> wrote in message > news:112ssmdbnlbe11e@news.supernews.com... > >> The first field buffer I used (in 1976) took 60 Amps of clock at 12 MHz. > > Crikey. Do tell more! My memory of it is slightly hazy (I didn't design it, I only used it.) It used 1024 bit dynamic shift registers, which had a multi-phase clock. The clock had a swing of something like 16 or 20 volts, and had quite strict (fast) risetime requirements into a rather large input capacitance. We never measured the current, but doing the calculations with voltage, risetime, and typical input capacitance gave a peak clock current of 60 Amps. The r.m.s. was clearly much less. I just did a quick google,and found a paper on it: http://www.bbc.co.uk/rd/pubs/reports/1977-09.pdf If I understand it correctly I was off by a factor of eight; the current was closer to 500 Amps peak.Article: 80640
On Wed, 09 Mar 2005 15:22:17 +0100, Sylvain Munaut wrote: > B. Joshua Rosen wrote: >> On Wed, 09 Mar 2005 15:25:45 +0700, Rudolf Usselmann wrote: >> >> >>>B. Joshua Rosen wrote: >>> >>>>They screwed up the installer on 7.1 and made it distribution dependent. >>>>Specifically the installer requires some out of date libraries. I wasn't >>>>able to install 7.1 on Fedora Core 3 or Mandrake 10.1 because of library >>>>issues. I ended up putting Whitebox Linux on one of my older machines >>>>(Whitebox is RHEL 3.0) and doing the install there. Once I'd done the >>>>install on the WB system I rsynced the directory over to my FC3 systems >>>>and it works fine. The tools themselves don't seem to have any >>>>distribution dependencies, the cock-up is limited to the installer. >>> >>> >>>I wonder if xilinx could provide an updated installer (only) >>>so that we all could install the tools on our favorite linux >>>distro. >>> >>>It should be just a recompile of xilsetup ... >>> >>>How about it ? >>> >>>I'll volunteer to beta test on 32 and 64 bit AMD platforms ... >>> >>>Best Regards, >>>rudi >>>============================================================= >>>Rudolf Usselmann, ASICS World Services, http://www.asics.ws >>>Your Partner for IP Cores, Design, Verification and Synthesis >> >> >> I've filed a webcase for Fedora Core 3. I've suggested that they >> statically link the installer so that it's not library dependent. It would >> probably be useful if other people would file cases for other >> distributions. There is no reason for there to be any distribution >> dependencies, the code can either be statically linked or the libraries >> included with the tools. In fact I think they have done the right thing >> when it comes to the tools themselves, I'm not having any trouble running >> them on Fedora Core 3. It is just the installer that has a problem. > > > Well, they also screwed up the WebPack installer apparently ;( > A don't have any RHEL 3.0 handy to install and copy, I'll have to find another > way. > > > Sylvain I used Whitebox, http://whiteboxlinux.org, to do the install, you could also download CentOS http://www.centos.org CentOS has just released 4.0 but you don't want that one, it's RHEL 4 which probably doesn't work, get 3.4.Article: 80641
Sylvain Munaut wrote: > B. Joshua Rosen wrote: >>... >> >> I've filed a webcase for Fedora Core 3. I've suggested that they >> statically link the installer so that it's not library dependent. It >> would probably be useful if other people would file cases for other >> distributions. There is no reason for there to be any distribution >> dependencies, the code can either be statically linked or the libraries >> included with the tools. In fact I think they have done the right thing >> when it comes to the tools themselves, I'm not having any trouble running >> them on Fedora Core 3. It is just the installer that has a problem. > > Well, they also screwed up the WebPack installer apparently ;( > A don't have any RHEL 3.0 handy to install and copy, I'll have to find > another way. > > Sylvain Same here - I too don't have a commercial Linux package "lying around". I am very glad to hear that the tools otherwise seem to work just fine with FC3. I am very disappointed to see that this Wind/U crap is still being used ... Is there anyway to escalate this within Xilinx ? Web-cases can take a while to resolve ... can somebody from xilinx provide a static version of the installer ? Perhaps in a restricted download area ? Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 80642
Giorgos P. wrote: > Hello, > > I am interested in opinions concerning advantages and disadvantages of the > hardware (FPGAs) and developing software (Quartus vs ISE) for high-end > (very demandidownload). > I was under the impression that xilinx was ahead but I've done some > readindesigns and StratixII seems to have made a step ahead in comparison > to Virtex4. The devices I am interested in are Stratix and StratixII from > one side and VirtexII pro, Virtex4 one the other. > > There is not one specific parameter that I need to investigate. Procesing > power, memory and I/O data rates are all significant. > > Of cource the role of the EDA tools is important so if someone could give > me his opinion one advantages and week points of each one I would be > grateful. > > Thanks You are asking for a holy war ! Both Altera and Xilinx make FPGAs. Som epeople like A, others like X. If you just go by marketing numbers, you will never be able to decide which one is better. When we had to make the choice, we downloaded the free tools, and tried a bunch of designs (you can download various sample designs from OpenCores.org if you need some). 1) Try both (free tools), look at the sample results 2) Look at the ease of use of tools 3) Look at support (do a search in this group for answers from X and A, perhaps thats not a fair comparison as there are alot more X users here than A users) 4) Make your own decission Shouldn't be that difficult. Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 80643
Xilinx offers a very nice UART core (+ 16 bytes fifo as an option) for free - it is includded in the PicoBlaze package. You can download it and use it - it has full documentation and it is working just fine. If you do not use Xilinx I'm sure that you can google for a UART core in the web. Regards, Moti.Article: 80644
Thanks for your reply Mike. Ideally I'd like to read any kind of memory configuration file into a design with Synplify - doesn't have to be Xilinx-specific formats. With XST, what I can do is read in a .mif file and then parse the data to create init values for my memory elements. Synplify does not appear to able to do the file read. Any more ideas? Andrew Mike Treseler wrote: > Andrew Whyte wrote: > >> Hi, >> >> I'm trying to read in data from a .mif file to initialise some memory >> elements in Synplify 7.6.1, but it fails when it encounters the line >> >> FILE initfile : TEXT; > > > A .mif file is specific to X devices. > > Synplify can synthesize variable or constant > arrays into ram or rom using only vhdl source code > for any fpga. > > Vendor-specific download widgets are handled with > vendor attributes in the code like this: > > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex11.html > > But consider maintaining vendor-independent code. > That's a common reason for using Synplify over XST > in the first place. > > -- Mike Treseler >Article: 80645
spacexxspace@yahoo.com wrote: > Hi All, > > Do you know what are the advantages and disadvantages / differences > between the FPGA development tools such as Actel Libero IDE, Xilinx > ISE and Altera MAX+PLUS II? > > Thanks. Don't know much about Libero or Quartus. ISE is good. I'm also impressed with Lattice's new ispLever. They have some unique fpgas and their tools cost less than the other guys.Article: 80646
> Well, they also screwed up the WebPack installer apparently ;( > A don't have any RHEL 3.0 handy to install and copy, I'll have to find > another > way. Apparently just installing openmotif did the trick ( missing libXm.so.3 was the problem ) I'm on gentoo btw SylvainArticle: 80647
Does anyone have experience with Lattice's XP (flash + sram) fpga? This technology looks great, instant on, reconfigurable & total security. I've been impressed with the progress of their sw, althogh it is not up to ISE, it seem more than adequate.Article: 80648
> 1) Try both (free tools), look at the sample results Just a quick note -- be sure to use real-world designs and push the tools on performance. Using "toy" designs (say, a 32-bit adder or a 4-bit multiply) often doesn't give you the full story. > 3) Look at support (do a search in this group for answers from > X and A, perhaps thats not a fair comparison as there are > alot more X users here than A users) If you plan to buy any volume, then this group will not be a good example of support. Both companies will fall overthemselves for your business if you are buying any quantity. There are distributor FAEs, factory FAEs, and others who will hold your hand and give you a back-rub if it helps you be successful with their product! If you are serious about buying high-end products, your best bet is to try out the tools and invite salespeople/FAEs from both companies in to compete for your business. Oh yeah -- pick Altera ;-) Regards, PaulArticle: 80649
Giorgos P. wrote:
> I am interested in opinions concerning advantages and disadvantages of the
> hardware (FPGAs) and developing software (Quartus vs ISE) for high-end (very
> demanding designs).
Consider deferring the vendor and part selection until after you
have prototyped and simulated a substantial portion
of your design in vendor-agnostic hdl. Use synthesis
to pick a device from each vendor and then get quotes.
-- Mike Treseler
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