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Andrew Whyte wrote:
> Hi,
>
> I'm trying to read in data from a .mif file to initialise some memory
> elements in Synplify 7.6.1, but it fails when it encounters the line
>
> FILE initfile : TEXT;
A .mif file is specific to X devices.
Synplify can synthesize variable or constant
arrays into ram or rom using only vhdl source code
for any fpga.
Vendor-specific download widgets are handled with
vendor attributes in the code like this:
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex11.html
But consider maintaining vendor-independent code.
That's a common reason for using Synplify over XST
in the first place.
-- Mike Treseler
Article: 80551Hello, I use a Virtex II Pro Development board (2VP7 - FG456 Rev 3) with XPS and ISE version 6.2.03. Since I use OCM memory instead of PLB or OPB memory , the malloc functions doesn't work anymore (the program write it on SDRAM memory instead of D-OCM). Also, I don't understand where are exactly the stack, heap and data zone ? (in spite of the LinkerScript file). Does someone have the same problem as me or know why? Best Regards PierreArticle: 80552
Hello guys, Can anyone please suggest guideline for routing the PCI signal from fpga to the connector. Thanks in advance, regards williamsArticle: 80553
Hello, I use a Virtex II Pro Development board (2VP7 - FG456 Rev 3) with XPS and ISE version 6.2.03. Since I use OCM memory instead of PLB or OPB memory , the malloc functions doesn't work anymore (the program write it on SDRAM memory instead of D-OCM). Also, I don't understand where are exactly the stack, heap and data zone ? (in spite of the LinkerScript file). Does someone have the same problem as me or know why? Best Regards PierreArticle: 80554
Hello, I'm going to create a RPM after PAR, for a Xilinx Virtex2. Following XAPP422 I have to launch floorplanner to create the ucf and ngc. Since I don't change the placement I hit only some menu items and and exit it. The ngc can be created via ngcbuild. Is there any command line tool for generating the ucf? Furthermore, what stands RPM for. XAPP422 says Relationally ... but XAPP416 Relatively ...:-) Bye TomArticle: 80555
Hello guys, I wanted to know far i can keep by USB PHY from USB core (inside the fpga)　so that i am within the USB standard????　how do i calculate the maximum trace length from fpga to Usb PHY. Thanks in advance Regards PraveenArticle: 80556
Can anybody recommend a good PC-based verilog simulator for substantially less than $4500? I am a new hire at a company which spent big bucks on ModelSim just two years ago. Unfortunately we purchased VHDL and I am a verilog designer. We have a tight schedule so I will stick with the familiar language. I would use the VHDL simulator but Xilinx tools won't put out a VHDL model from verilog source files. Mentor Graphics will not allow an inexpensive license switch from our present VHDL to the verilog (They charge full price and give us no credit for the previous full price purchase). I can't use the "Xilinx Edition ModelSim" becuase it won't support my target, the XC2VP20, as far as I know. Any suggestions would be appreciated.Article: 80557
Paul Taddonio <paul.taddonio@futureplus.com> wrote: > Can anybody recommend a good PC-based verilog simulator for substantially > less than $4500? > I am a new hire at a company which spent big bucks on ModelSim just ... First: put a line break at 60 charaters per line > Any suggestions would be appreciated. www.pragmatic-c.com www.icarus.com/eda/verilog -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 80558
its better to register at each level if your resource demand isnt too much.Article: 80559
williams wrote: > Hello guys, > Can anyone please suggest guideline for routing the PCI signal from > fpga to the connector. > > Thanks in advance, > regards > williams If you're building a daughtercard (as opposed to a motherboard) you should follow the maximum lengths per the PCI specification. Also note that the clock line is a length matching spec, not just a maximum. Briefly, the bulk of the 32-bit signals spec 1.5" max to the connector. Clock is 2.5" (matched length), and the 64-bit extension signals spec 2" maximum. Exceptions include interrupt lines and the reset signal. With any luck your FPGA pinout helps you meet these requirements.Article: 80560
just a guess, try checking out active HDL.Article: 80561
Great, thanks for the link. They're results are that the sync and async versions of the same processor have the same area, speed, and power consumption except that the async version apparently has less EMI. I was hoping the async design would have advantages in other areas, but I guess not. -- PeteArticle: 80562
<fpgavhdl@gmail.com> wrote in message news:1110232376.378197.253010@o13g2000cwo.googlegroups.com... > By scoping the sync stripper (EL 4511) H sync seems to be jitter free. > This Hysnc is given to the PLL which generates a 27 Mhz clock that is > locked to the Hsync. I have not had time to read the MK2069 datasheet in detail but it seems a strange one for locking to H. The block diagram seems to show that you MUST divide horizontal by two before you get to the first phase comp. Genarally speaking, you want to have the highest possible comparison frequency. Assuming you have the PV dividers set to "2", then you should be able to lock your scope to RCLK (fh/2) and observe the relative jitter on ICLK (fh). The jitter is actually on RCLK, but it's easier to measure if you sync to the lower frequency input. > This clock is fed into the FPGA which does the > Subcarrier locking. The 27 MHz coming into the FPGA is upscaled to 54 > MHz.. It might be better to allow the 2069 to do the frequency multiplication in its second PLL. The 2069 is designed to deal with any jitter on the primary VCO, but FPGA clcok multiplers tend to not tolerate input jitter well. > during the rising edge of this 54 MHz clock the subarrier is > locked to the reference input signal (composite video). Do u think this > helps the subcarrier lock to the 54Mhz clock? I'm not sure what you're saying here. Does your A/D run at 27 MHz or 54 MHz? I assume 54 MHz. Are you then half-band filtering? You should be using all the samples from the central 50% of the burst width. However, there's no need to be extremely super-Nyquist, so doing the demodulation at 27 MHz, or even 13.5 MHz should give you a decent burst lock (as long as you have a reasonable pre-decimation filter). > The PLL chip I am using > is a MK2069. > BTW whats the technique to measure the jitter. Also the 27 MHz clock > input to the FPGA is not a proper square wave...and as far i know this > could be reason for jitter aswell. What do u have to say on this? That could be a problem. Check the clock against the FPGA vendor's specs. > The > input analog video composite signal is converted into a 12-bit digital > before giving to the FPGA (for locking the subcarrier). The output from > the FPGA is given to the DAC which gives the analog black burst. Do u > think since both these DAC and ADCs,which are operated with clock (not > exactly square waves) will have anything to do with the jitter? Unless they're so badly miss-clocked that they're munging samples It shouldn't be a problem. > > Thanx again...Really appreciate ur help > You're welcome. What's the background to this design? What's it going to do when it's finished? Is it a commercial device or a hobby project?Article: 80563
Neo wrote: > just a guess, try checking out active HDL. Last price list shows definitely more than 4,500 for Verilog-only Active-HDL PE. I don't know if they will separate the simulator from the development environment.Article: 80564
Gabor wrote: > Neo wrote: > >>just a guess, try checking out active HDL. > > > Last price list shows definitely more than 4,500 for Verilog-only > Active-HDL PE. I don't know if they will separate the simulator > from the development environment. > Maybe you should ask them for Riviera instead of Active-HDL? Regards, PRArticle: 80565
Ben, But the "fixed" version isn't available till the end of the month. All that is on the shelf today is the "broken" version. Austin Ben Twijnstra wrote: > Er, Peter, > > >>Well, I think there is a difference here. >>On the newsgroup we can say: >>"Altera Stratix-2 still has the infamous start-up current, even >2A on >>a 2S60, and we have measurements to prove it". >> >>But I am not too excited about honoring them with a Xilinx website, >>only to have Altera then come back and claim that they finally "have >>REALLY" fixed it. >> >>Gentlemen should have some constraint in washing each other's dirty >>laundry in public, or call each other "liar" in public, even when it >>would be justified, as it is in this case. > > > Ok. In the same vein, what are you going to do about that slow interconnect > in the V4 series then? > > Paul never called Austin a liar. He merely exposed a few unmentioned facts > in Austin's diatribe. > > The EP2S60ES silicon is/was a power hog (ha, you should have heard the > raspberries when the ES power requirements were first mentioned to the > FAEs), and Altera has been exceedingly candid about this to all customers. > > For the EP2S60, ES silicon is all you'll find at the moment, and it would > have been better for your future credibility if Austin had immediately > mentioned that your measurements had indeed been done on an EP2S60ES. > Altera would have simply responded with "Yep, that's what we said. Didn't > you believe us?". > > Then again, the world would have missed an interesting Usenet thread... > > Best regards, > > > > Ben >Article: 80566
Kolja, I can send the pictures to you (to post quickly), but it sounds like it isn't of any interest. OK, I quit. Austin Kolja Sulimma wrote: > Peter Alfke wrote: > >> But I am not too excited about honoring them with a Xilinx website, >> only to have Altera then come back and claim that they finally "have >> REALLY" fixed it. > > [...] > >> But the newsgroup is like a club, where we can be more outspoken and >> candid... > > > But Austin could post the images on a webpage and link to them in a > newsgroup message. > I think a good place for such images would be fpga-faq.com but I could > also place them on fpga.de > > Kolja SulimmaArticle: 80567
Paul, Are you done changing the worst case numbers? Austin Paul Leventis (at home) wrote: > Hi Austin, > > >>As for webinar, is the leakage going to be less for all future production >>parts? Sounds like the first ES lot was leakier because it was fast >>corner material. It is possible that it was outside the wafer acceptance >>critera, so I will grant you that one, too. > > > Most ES units while leakier than typical are still within (the now reduced) > production specs. Over time we gain better control over the process and > hence can provide a better upper bound on worst-case leakage for production > units. This was reflected in the last spec upgrade. > > >>'Typical' is not something you can design to in this case. > > > You don't need to convince me that looking at "typical" numbers for leakage > is incorrect for most designs. Altera has published worst-case Stratix II > leakage specs since day one. > > Paul Leventis > Altera Corp. > >Article: 80568
You can get a VHDL netlist post-synthesis (depending upon the synthesizer you are using), post-NGD build, post-map, or post-PAR. Debugging your RTL from a post-NGD build VHDL netlist might not be as easy as debugging a Verilog RTL sim, but it may be your best option and requires no more cash. See the help for the Xilinx executable 'netgen' for details on creating VHDL netlists from NGD or NCD files. -Kevin Paul Taddonio wrote: > Can anybody recommend a good PC-based verilog simulator for substantially less than $4500? > > I am a new hire at a company which spent big bucks on ModelSim just two years ago. Unfortunately we purchased VHDL and I am a verilog designer. We have a tight schedule so I will stick with the familiar language. I would use the VHDL simulator but Xilinx tools won't put out a VHDL model from verilog source files. Mentor Graphics will not allow an inexpensive license switch from our present VHDL to the verilog (They charge full price and give us no credit for the previous full price purchase). I can't use the "Xilinx Edition ModelSim" becuase it won't support my target, the XC2VP20, as far as I know. > > Any suggestions would be appreciated.Article: 80569
Hello, I am interested in opinions concerning advantages and disadvantages of the hardware (FPGAs) and developing software (Quartus vs ISE) for high-end (very demanding designs). I was under the impression that xilinx was ahead but I've done some reading lately and StratixII seems to have made a step ahead in comparison to Virtex4. The devices I am interested in are Stratix and StratixII from one side and VirtexII pro, Virtex4 one the other. There is not one specific parameter that I need to investigate. Procesing power, memory and I/O data rates are all significant. Of cource the role of the EDA tools is important so if someone could give me his opinion one advantages and week points of each one I would be grateful. ThanksArticle: 80570
Hi everyone, Is it just me, or can you only request the windows version of the ISE Foundation/BaseX 7.1i evaluation? I would really like to know whether the software runs on Gentoo or it only accepts the Redhat-installation! Thanks Preben HolmArticle: 80571
On Tue, 08 Mar 2005 17:59:34 +0100, Preben Holm wrote: > Hi everyone, > > > Is it just me, or can you only request the windows version of the ISE > Foundation/BaseX 7.1i evaluation? > I would really like to know whether the software runs on Gentoo or it > only accepts the Redhat-installation! > > > Thanks > Preben Holm They screwed up the installer on 7.1 and made it distribution dependent. Specifically the installer requires some out of date libraries. I wasn't able to install 7.1 on Fedora Core 3 or Mandrake 10.1 because of library issues. I ended up putting Whitebox Linux on one of my older machines (Whitebox is RHEL 3.0) and doing the install there. Once I'd done the install on the WB system I rsynced the directory over to my FC3 systems and it works fine. The tools themselves don't seem to have any distribution dependencies, the cock-up is limited to the installer.Article: 80572
Try GPL Cver, it's 1394 compliant and it's free. http://www.pragmatic-c.com/gpl-cver/Article: 80573
I wonder how you can so easily speak about adding regisers somewhere in the circuit. Wouldn't it change the functionality of the circuit (missing cycles)? Consider a MUX(S, A, B): you cannot just FF the outputs as this will break the contract inferring a cycle delay. I beleive, this issue must be elaborated in the "good design methodologies" literature. The non-experienced users like me would try both options in practice by a conditional, generic-controlled regstration.Article: 80574
> But the "fixed" version isn't available till the end of the month. > All that is on the shelf today is the "broken" version. Just to clarify, all members except the 2S60ES have had no surge current since their introduction. And "broken" is too strong a word -- how hard is it to put a 2A supply on the board? Regards, Paul
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z