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I'm looking to implement four, 150 tap FIR filters in an Actel MX series FPGA. The filters I'm designing are 16 data bit input, 16 bit coeffienencs and 1khz sample rate. FPGA will be clocked with a 10MHz clock and will have a state machine to retrieve the samples from the A2D following a 1khz HW interrupt. How do I estimate the resource requirements to implement the filter section? Any special hurdles in implelenting FIR filters in a Actel MX series FPGA? MX series is a fixed quantity and cannot be changed. thanksArticle: 80751
First the co-efficients, if they are not same then you'll have 600 of them and you need to decide on their precision. that along with your inputs and outputs will determine your memory reqd. Next the adders and multipliers depend on how much parallelism you put into your filtering. that also gives your io requirements. I dont know the logic resource of this particular device but looking at your low sampling rate, you may be fine with pipelined serial implementation.Article: 80752
The coefficients of three of the four filters will be identical (just on diferent signals). I'm looking at a direct from FIR filter. Input will be sampled from a quad input 16 bit A2D at 1kHz intervals. The four sample will be pushed into the filter queue at a rate of 1kHz. I'm new to FPGA design so I have no idea how much parallelism is required. I do not need speed for this application since the sampel rate is so slow but it saves me some HW if i can fit it in an FPGA that has plenty of room left on the board. thanks "Neo" <zingafriend@yahoo.com> wrote in message news:1110515936.987823.261130@g14g2000cwa.googlegroups.com... > First the co-efficients, if they are not same then you'll have 600 of > them and you need to decide on their precision. that along with your > inputs and outputs will determine your memory reqd. Next the adders and > multipliers depend on how much parallelism you put into your filtering. > that also gives your io requirements. > I dont know the logic resource of this particular device but looking at > your low sampling rate, you may be fine with pipelined serial > implementation. >Article: 80753
handleC is proprietary and you have to use celoxica's tools with them. SystemC well, you can use as its open source and about to become the ieee std but that apart not only latest versions of some tools like modelsim,VCS and NCsim support it with some restrictions. mentors catapult C does synthesis from native C++ with some guidance. I am not aware how good that is. Forte also has a c-synthesizer but that again is proprietary. But I wonder if you knew VHDL why go for c -based sythesis as the eda tool market is yet to mature on that line and still it wouldnt beat VHDL, since VHDL was developed purposefully for hardware development.Article: 80754
yes, like a dead log no way about it. a port is akin to a pin for a circuit and you simply cant make its presence to be dynamically determined.Article: 80755
Thomas Reinemann wrote: > Hello, > > I'm going to create a RPM after PAR, for a Xilinx Virtex2. Following XAPP422 > I have to launch floorplanner to create the ucf and ngc. Since I don't > change the placement I hit only some menu items and and exit it. The ngc > can be created via ngcbuild. Is there any command line tool for generating > the ucf? > > > Furthermore, what stands RPM for. XAPP422 says Relationally ... but XAPP416 > Relatively ...:-) > > > Bye Tom Floorplanenr will create the UCF file when you save it's ".FNF" file. Be sure to include the UCF file which floorplanner creates in your project. This step is not automatic. Actually, you can apply RLOC constraints to your logic in the HDL itself, but for this to be effective, they must be applied either to instantiated primitives or instantiated components which are composed of primitives. Many designers create libraries of commonly used components such as registers, adders, etc which have RLOCs embedded in the HDL. RPM: I vote for relationally (heard that being used more often)Article: 80756
ezpcb.com wrote: > Hi all > I want to design a 1024 poles FIR filter on FPGA. But I had no > experiences on large scale FPGA programming. Can anybody tell me which > chip should I use? > > mike > > Both Altera and Xilinx sell FPGAs which are in some sense designed for DSP applications. How large an FPGA you need depends on other parameters which you have not specified, such as how many bits per sample, and how many clocks are available per sample. Altera and Xilinx offer development tools which have a variety of automated tools to help you do FPGA-based DSP, of course, none are as good as hand-coding. For many applications, though, they are enough. Regarding cost, generally the older chips (2 or more generations old) will cost more per CLB than new chips. Then again, there are more development boards and tools available to support the older chips.Article: 80757
Mook Johnson wrote: > The coefficients of three of the four filters will be identical (just on > diferent signals). > > I'm looking at a direct from FIR filter. Input will be sampled from a quad > input 16 bit A2D at 1kHz intervals. The four sample will be pushed into the > filter queue at a rate of 1kHz. > > > I'm new to FPGA design so I have no idea how much parallelism is required. > > I do not need speed for this application since the sampel rate is so slow > but it saves me some HW if i can fit it in an FPGA that has plenty of room > left on the board. > > thanks > > > "Neo" <zingafriend@yahoo.com> wrote in message > news:1110515936.987823.261130@g14g2000cwa.googlegroups.com... > >>First the co-efficients, if they are not same then you'll have 600 of >>them and you need to decide on their precision. that along with your >>inputs and outputs will determine your memory reqd. Next the adders and >>multipliers depend on how much parallelism you put into your filtering. >>that also gives your io requirements. >>I dont know the logic resource of this particular device but looking at >>your low sampling rate, you may be fine with pipelined serial >>implementation. >> > > Given you're using an Actel chip, you may not have looked on xilinx.com, which has an appnote (I forget which one) which describes transposed FIR filters, which can be modified easily to reduce device utilization by exploiting filter symmetry (if any). But anyway, since you have a 10 MHz clock and a 1 kHz data rate, you could get away with using a single multiplier and 4 accumulators. In this case, the resource utilization will be dominated by the multiplier. A more efficient use of resources would be a distributed-arithmetic filter, but resource utilization is not as straightforward to compute.Article: 80758
Hi all, Is there a Xilinx PQ208 package available anywhere for Eagle (I have a registered 4.09r2) that works with the autorouter ? Whenever I place even any of the library components in the cadsoft-supplied xilinx.lbr, I get an unroutable component (try 2 of the XC4000-type components, and click autoroute). I tried setting the routing grid low (1 mil) and the ripup options high (10x defaults) but still no joy - all I see at the end of the autoroute is maybe 1 or 2 lines routed and the rest is still a ratsnest... If I have to, I'll make a library component, but I'm not too experienced with the subtleties of autorouting on mixed mm/in grids (the PQ208 is in mm, most other components are in inches) and whether the component needs any special treatment because of that. Pre-built would give me a warmer feeling inside [grin]. Cheers, SimonArticle: 80759
Mike Treseler <mike_treseler@comcast.net> wrote in message news:<aIqdnXrlBO9Tua3fRVn-vg@comcast.com>... > Johnson Lee wrote: > > > I am writing a character controller using Altera MAXII device. > > This controller will monitor the input signals from lpt port. I make > > a simulation and download to real chip to verify function, but > > unfortunately it won't work as I designed. > > It won't work as you *expected*. > > > The simulation show that the state translate signals was initiated > > abnormal.. > > If the simulation doesn't work, there is a design error. > Debug it. > > -- Mike Treseler Well, My simulation is ok! But the result is not as what I planned to have. I abstracted some codes and attached in below for your reference: --------------------------------------------------------------------- PROCESS( RST, FLAG2, TP41, TP11, TP51, TP31) BEGIN IF RST='1' THEN BIOS1_ck <= '0'; BIOS2_ck <= '0'; BIOS5_ck <= '0'; BIOS7_ck <= '0'; ELSE IF ( TP11='1' ) THEN -- IF (FLAG2='1' AND TP41='1') THEN BIOS1_ck <='1' ; -- ELSE -- BIOS1_ck <= '0'; -- NULL; END IF; IF ( TP41='1' ) THEN BIOS2_ck <='1'; -- ELSE -- BIOS2_ck <= '0'; -- NULL; END IF; -- IF (CUR=BIOS5 AND TP51='1' ) THEN IF( TP51='1') THEN BIOS5_ck <='1'; -- ELSE -- BIOS5_ck <= '0'; -- NULL; END IF; IF (TP31='1') THEN BIOS7_ck <= '1'; -- ELSE -- BIOS7_ck <= '0'; -- NULL; END IF; END IF; END PROCESS; ----------------------------------------------------------- --- ----------------------------------------------------------- STATE_TRANS: PROCESS( RST, CUR, BIOS_ok, FLAG1, FLAG2, BIOS1_ck, BIOS2_ck, BIOS5_ck, BIOS7_ck, OS_RDY) BEGIN IF RST='1' THEN NEX <= POWER_ON; STATE <= '0'; BIOS1_sel <='0'; BIOS3_sel <='0'; SW_sel <= '0'; FAIL_sel <= '0'; OS_SEL <= '0'; B1 <= '0'; B2 <= '0'; B5 <= '0'; B7 <= '0'; ELSE CASE (CUR) IS WHEN POWER_ON => IF (FLAG2='1') THEN NEX <= BIOS0; STATE <= '1'; BIOS1_sel <= '1'; ELSE NEX <= POWER_ON; STATE <= '0'; BIOS1_sel <='0'; BIOS3_sel <='0'; SW_sel <= '0'; FAIL_sel <= '0'; OS_SEL <= '0'; B1 <= '0'; B2 <= '0'; B5 <= '0'; B7 <= '0'; END IF; WHEN BIOS0 => -- IF FLAG1='1' THEN -- NEX <= FAIL; -- STATE <= '1'; -- ELSIF (BIOS_ok ='1') THEN IF (BIOS_ok='1') THEN NEX <= BIOS1; STATE <= '1'; BIOS1_sel <= '0'; BIOS3_sel <= '0'; OS_SEL <= '0'; ELSE NEX <= BIOS0; STATE <= '0'; BIOS1_sel <='1'; BIOS3_sel <= '0'; END IF; WHEN BIOS1 => IF FLAG1='1' THEN NEX <= FAIL; STATE <= '1'; -- ELSIF ( BIOS1_ck='1' ) THEN ELSIF ( FLAG2='1') THEN NEX <= BIOS2; STATE <='1'; BIOS1_sel <= '0'; BIOS3_sel <= '0'; -- B1 <= '0'; ELSE B1 <= '1'; NEX <= BIOS1; STATE <= '0'; BIOS1_sel <= '0'; BIOS3_sel <= '0'; END IF; WHEN BIOS2 => IF FLAG1='1' THEN NEX <= FAIL; STATE <= '1'; ELSIF (BIOS2_ck='1') THEN NEX <= BIOS3; STATE <= '1'; BIOS3_sel <= '1'; BIOS1_sel <='0'; -- B2 <='0'; ELSE NEX <= BIOS2; STATE <= '0'; BIOS1_sel <= '0'; BIOS3_sel <= '0'; B2 <='1'; END IF; WHEN BIOS3 => -- IF FLAG1='1' THEN -- NEX <= FAIL; -- STATE <= '1'; -- ELSIF (BIOS_ok ='1') THEN IF (BIOS_ok='1') THEN NEX <= BIOS4; STATE <= '1'; BIOS3_sel <='0'; ELSE NEX <= BIOS3; STATE <= '0'; BIOS3_sel <= '1'; END IF; WHEN BIOS4 => -- IF FLAG1='1' THEN -- NEX <= FAIL; -- STATE <= '1'; -- ELSIF (FLAG2='1') THEN IF (FLAG2='1') THEN NEX <= BIOS5; STATE <= '1'; BIOS1_sel <='0'; BIOS3_sel <= '0'; ELSE NEX <= BIOS4; STATE <= '0'; BIOS1_sel <='0'; BIOS3_sel <= '0'; END IF; WHEN BIOS5 => IF FLAG1='1' THEN NEX <= FAIL; STATE <= '1'; ELSIF (BIOS5_ck='1') THEN NEX <= BIOS6; STATE <= '1'; OS_SEL <='1'; BIOS1_sel <='0'; BIOS3_sel <= '0'; ELSE NEX <= BIOS5; STATE <= '0'; BIOS1_sel <='0'; BIOS3_sel <= '0'; OS_SEL <= '0'; B5 <= '1'; END IF; WHEN BIOS6 => -- IF (FLAG1='1') THEN -- NEX <= FAIL; -- STATE <= '1'; -- ELSIF (OS_RDY='1') THEN IF (OS_RDY='1') THEN NEX <= BIOS7; STATE <= '1'; OS_SEL <= '0'; ELSE NEX <= BIOS6; STATE <= '0'; BIOS1_sel <='0'; BIOS3_sel <= '0'; OS_SEL <= '1'; END IF; WHEN BIOS7 => IF (FLAG1='1') THEN NEX <= FAIL; STATE <= '1'; ELSIF (BIOS7_ck='1') THEN NEX <= OS; STATE <= '1'; OS_SEL <= '0'; ELSE NEX <= BIOS7; STATE <= '0'; B7 <='1'; END IF; WHEN OS => SW_sel <='1'; NEX <= OS; STATE <='1'; BIOS1_sel <='0'; BIOS3_sel <= '0'; WHEN FAIL => FAIL_sel <= '1'; NEX <= FAIL; STATE <= '1'; BIOS1_sel <='0'; BIOS3_sel <= '0'; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; -------------------------------------------------------------- --- -------------------------------------------------------------- TP1 <= B1; TP2 <= B2; TP3 <= B5; TP4 <= B7; TP5 <= BIOS1_ck; TP6 <= TP11; TP7 <= TP21; TP8 <= TP31; TP9 <= TP41; TP10 <= TP51; TP16 <= BIOS1_ck; TP12 <= BIOS2_ck; TP13 <= BIOS5_ck; TP14 <= OS_RDY; TP15 <= BIOS7_ck; RS_O <= RS_01; RW_O <= RW_01; ENA_O <= ENA_01; DB_I1 <= DB_I; DB_I <= DB_O1 WHEN OE1='1' ELSE "ZZZZZZZZ"; DB_I2 <= DB_O; DB_O <= DB_O2 WHEN OE2='1' ELSE "ZZZZZZZZ"; RST_I <= ERR ; ----------------------------------------------------------- --- ----------------------------------------------------------- -- PROCESS( RST, CLK_10M ) PROCESS( RST, DB_I1, FLAG2, B1, BIOS7_ck, B7, B2, B5) BEGIN IF RST='1' THEN TP11 <= '0'; TP21 <= '0'; TP31 <= '0'; TP41 <= '0'; TP51 <= '0'; -- ELSIF( CLK_10M'EVENT AND CLK_10M='1') THEN ELSE -- IF (CUR=BIOS1 AND DB_I1="11111111") THEN IF ( FLAG2='1' AND B1='1' AND DB_I1 ="11111111") THEN -- IF (FLAG2='1' AND DB_I1="11111111") THEN TP11 <= '1'; ELSE TP11 <= '0'; -- NULL; END IF; IF (BIOS7_ck='1') THEN TP21 <= '1'; -- ELSE -- TP21 <= '0'; -- NULL; END IF; -- IF ( B7='1' AND DB_I1="01001100" ) THEN IF ( DB_I1 = "01001100") THEN TP31 <= '1'; ELSE TP31 <= '0'; -- NULL; END IF; -- IF (CUR=BIOS2 AND DB_I1="00000000") THEN -- IF (B2='1' AND DB_I1 = "00000000") THEN --CAN'T ADD THIS SIGNAL FOR USE?? IF ( DB_I1="00000000") THEN TP41 <= '1'; ELSE TP41<= '0'; -- NULL; END IF; IF ( DB_I1="10100101") THEN -- IF (B5='1' AND DB_I1="10100101") THEN TP51 <= '1'; ELSE TP51 <= '0'; -- NULL; END IF; END IF; END PROCESS; ---------------------------------------------------------- --- ---------------------------------------------------------- END A; In the functional simulation result, whiere the DB_I1 is set at "FF", TP8 is always keeps at low level while TP15 was pulled up at 380ns. In my design, TP15 is used to monitor the status of BIOS7_ck which was pulled up when TP8 is set to high. BR, JohnsonArticle: 80760
"Marc Randolph" <mrand@my-deja.com> schrieb im Newsbeitrag news:1110508806.681990.180250@f14g2000cwb.googlegroups.com... > > Austin Lesea wrote: > > And: > > > > MGTs, Power PC's, EMAC's, APU's. > > > > Lots of things that synthesis does poorly, or not at all. > > > > Oh, but Altera doesn't have any of these .... so they would not want to > > direct your attention to items that they are completely missing (in > > their product offering). > > Howdy Austin, > > What is this? > http://www.altera.com/products/devices/stratixgx/features/sgx-transceiver.html its only in VERY expensive StratixGX devices and no newer family seem to have the MGT similar high speed things any more, I wonder if a new Press release from altera could be expected about Stratix-III GX ?? would be nice and would not surprise me, but well lets see > True is isn't a full PPC, but they have processors too: > http://www.altera.com/products/devices/stratixgx/features/sgx-stratixgx_nios.html Nios is softcore so not countable, but Excalibur? has ARM stripe, again those devices are soon to move to mature list ? And new Altera Devices dont have hardcore processor any more, and no support for ARM - well here we have a new player coming in Actel just announced first time ever agreement from ARM to license ARM as softcore on FPGAs > I suppose APU is an arithmetic processing unit, i.e. a DSP block - you > know, the one that had an accumulator long before Xilinx: > http://www.altera.com/products/devices/stratixgx/features/sgx-dsp.html you suppose incorrectly, APU is auxiliary processing unit to PPC and Altera doesnt have that, both A and X have DSP blocks what are partially supported by synthesis tools, > Have fun, > > Marc > In generic almost all the comparison from Austin where valid, ok he forgot to mention the StratixGX and ARM stripe, but if only looking at latest products in comparison then Altera does not MGTs and hardcore processors in last families AnttiArticle: 80761
Make the filter a state machine that acts like a small computer. It fetches the data from a RAM delay line and the coefficient from a ROM and then multiplies them and adds the result to an accumulator, and then goes on like that. That way you reuse the multiplier. "Mook Johnson" <mook@mook.net> skrev i meddelandet news:GW8Yd.62440$SE2.53093@fe2.texas.rr.com... > I'm looking to implement four, 150 tap FIR filters in an Actel MX series > FPGA. The filters I'm designing are 16 data bit input, 16 bit coeffienencs > and > 1khz sample rate. FPGA will be clocked with a 10MHz clock and will have a > state machine to retrieve the samples from the A2D following a 1khz > HW interrupt. > > How do I estimate the resource requirements to implement the filter section? > Any > special hurdles in implelenting FIR filters in a Actel MX series FPGA? > > MX series is a fixed quantity and cannot be changed. > > thanks > >Article: 80762
Lukasz- An alpha release of the Linux API and drivers (they rely on libusb) has been released for Fedora Core 3 and SuSE 9.2, though they should work on distributions with similar gcc / library setups. The release includes the C++, Python, and Java APIs. Cheers, Jake Janovetz Opal Kelly IncorporatedArticle: 80763
is it possible to have a sequences of bursts in the user logic instead of using the DMA?Article: 80764
Thank you for your answers, although I have searched for the topic "reset + release" I am still confused. If Mr Randolph says that there in only one global reset path so does it make any sense to release the reset signals for the different clock domains separately that is to synchronize the reset with the corresponding clock and distribute different reset signals? Best regards AndrésArticle: 80765
xman wrote: > you can find it here: http://www.plsgoogleit.com/ > > > "Nicolas Schwarzentrub" <schwn@hta-bi.bfh.ch> wrote in message > news:d0pg8u$nco$1@news.hispeed.ch... > >>Hi everybody, >> >>we're two students looking for a low cost developer board for our diploma >>work. we intend to plug a camera to the pci board via 1394 and process the >>images throug the fpga and get the processed images from fpga via pci. The >>camera we will use, uses DCAM /IICD >>Now we have several problems: >>-we don't have a high budget, so it should be a low cost solution. >> >>-we have not jet found a board that fits our need, does anybody know >>something cheep that could fit our needs? >> >>-there would be several possibility to solve the connectivity problems: >> >>* best would be to find a board that fits our need, means have at least >>pci, fpga and 1394 on it? any suggestions ont htat? >> >>* if the above point can't be reached we could probably solder our 1394 >>interface ourself on a board. What would then be best for our purpose? We >>could probably use a TSB12LV32 chip from ti if we don't find a board with >>firewire. (http://focus.ti.com/docs/prod/folders/print/tsb12lv32.html)? >>does anybody know this? would it then be possible to implement the dcam in >>the fpga? >> >>Thanks to everbody > > > funny man! you may visit our page (www.cephalo.ch.vu) to see that we allready googled. Next time better don't answer if you don't have any help to a serious question. Maybe you didn't got the point. The point is not the header, the point is the 1394 problem! Boards with 1394 are available but we can't afford more than say $500, so we must find a cheap board and as far as we see ther doesn't exists one with 1394 for that price, it may exist but does' not have pci.. got it? So what we want to know is if anybody has already soldered himeself a 1394 chip on a fpga board and if so has implemented the DCAM IIDC on a fpga? $ serious answers very welcome kindest regards Nicolas SchwarzentrubArticle: 80766
Hello @ VHDL people out there, I have the following problem. Maybe someone of you has experienced the same: The signal "input_data" comes from a 12MHz clock domain. Now I want to sample that signal that way that I generate one sample-enable which is close to the center position of the bits. One possibility to do so is to use a over-sampling clock, let us assume 48MHz. When stepping to the signal processing of my design I see that the sampled signal which is in the 48MHz clock domain now has to be synchronized into a 90MHz clock domain. So my idea was to sample the "input_data" with a sample-enable directly in the 90MHz clock domain. The problem: 90 is not a multiple of 12. Is there a possibility to sample the 12MHz signal right in the center ? When using 48MHz sample clock I use a simple counter with which I can define the position of the sampling point. Any suggestions are appriciated. Rgds AndreArticle: 80767
Jim George wrote: > Thomas Reinemann wrote: >> Hello, >> >> I'm going to create a RPM after PAR, for a Xilinx Virtex2. Following >> XAPP422 I have to launch floorplanner to create the ucf and ngc. Since I >> don't change the placement I hit only some menu items and and exit it. >> The ngc can be created via ngcbuild. Is there any command line tool for >> generating the ucf? >> >> >> Furthermore, what stands RPM for. XAPP422 says Relationally ... but >> XAPP416 Relatively ...:-) >> >> >> Bye Tom > > Floorplanenr will create the UCF file when you save it's ".FNF" file. Be > sure to include the UCF file which floorplanner creates in your project. > This step is not automatic. I know how I have to create a RPM. But since the logic is placed during PAR floorplanner is only used to extract the RLOC constraints from the ncd. Just now I'm looking for a command line tool to avoid to click around in floorplanner. Similar to ngcbuild which I can use to create the ngc. Bye TomArticle: 80768
FPGAworld'2005 Stockholm, Sweden, September 8th, 2005 URL: http://www.fpgaworld.com/conference Dear Colleague I would like to invite you to attend the second FPGAworld Conference. The FPGAworld Conference addresses all aspects of digital and hardware/software system engineering on FPGA technology. It is a discussion and network forum for researchers and engineers working on industrial and research projects, state-of-the-art investigations, development, and applications. David Kallberg FPGAworldArticle: 80769
Neo Thank you a lot for your replay. I'm in nned to go to c- synthesis because I want to implement DSP algorithms on FPGA and I think it is better to write and test the algorithm in C/C++ then convert it to hardware may be more easy than using VHDl. Best regardsArticle: 80770
>Whenever I place even any of the library components in the >cadsoft-supplied xilinx.lbr, I get an unroutable component (try 2 of the >XC4000-type components, and click autoroute). I tried setting the >routing grid low (1 mil) and the ripup options high (10x defaults) but >still no joy - all I see at the end of the autoroute is maybe 1 or 2 >lines routed and the rest is still a ratsnest... Check your design rules. If you have the pad-wire clearence set too high, the router can't get a wire into a pad because the adjacent pads are too close. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 80771
Hello, I am interested in opinions concerning advantages and disadvantages of the hardware (FPGAs) and developing software (Quartus vs ISE) for high-end (very demanding designs). I was under the impression that xilinx was ahead but I've done some reading lately and StratixII seems to have made a step ahead in comparison to Virtex4. The devices I am interested in are Stratix and StratixII from one side and VirtexII pro, Virtex4 on the other. There is not one specific parameter that I need to investigate. Procesing power, memory and I/O data rates are all significant. Of cource the role of the EDA tools is important so if someone could give me his opinion one advantages and week points of each one I would be grateful. email: gpouikli@ee.duth.gr ThanksArticle: 80772
I can't answer your question, sorry. I post here just to tell that I would be interested to get an eagle libray with XC9536-in vq44 package and XC9572 in vq100 package. Anyone got it? (I'm not able to use .scr files for xilinx parts available on eagle website) Thanks "Hal Murray" <hmurray@suespammers.org> a écrit dans le message de news: gfidnSW9JvJV8KzfRVn-jg@megapath.net... > >Whenever I place even any of the library components in the >>cadsoft-supplied xilinx.lbr, I get an unroutable component (try 2 of the >>XC4000-type components, and click autoroute). I tried setting the >>routing grid low (1 mil) and the ripup options high (10x defaults) but >>still no joy - all I see at the end of the autoroute is maybe 1 or 2 >>lines routed and the rest is still a ratsnest... > > Check your design rules. If you have the pad-wire clearence > set too high, the router can't get a wire into a pad because > the adjacent pads are too close. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or > unsolicited > commercial e-mail to my suespammers.org address or any of my other > addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 80773
Hallo, I have devolped a small LCD controller for my grhaphic display, OPB compliant. When I create an embedded system with edk, I can choose STDIN and STDOUT, but my peripheral isn't between those I can choose. There is RS232, ecc. of my Spartan 3 Starter Kit. I would make it a stdout. What should I do?Article: 80774
"Marco" <marcotoschi@email.it> schrieb im Newsbeitrag news:ee8c9aa.-1@webx.sUN8CHnE... > Hallo, I have devolped a small LCD controller for my grhaphic display, OPB compliant. > > When I create an embedded system with edk, I can choose STDIN and STDOUT, but my peripheral isn't between those I can choose. There is RS232, ecc. of my Spartan 3 Starter Kit. > > I would make it a stdout. What should I do? 1) you 'mimic' the UARTlite registers 2) you write outb() that writes to the LCD that will redirect stdout from C program to your peripheral Antti
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