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The opb_emc controller can not handle any Flash devices correctly if the total width of flash is not 32 bits so if you have a 16 bit flash connected and bus widht matching enabled you need small glued logic to FIX the opb_emc this may or may not be your problem antti "PH" <p_hogan76@yahoo.co.uk> schrieb im Newsbeitrag news:1108035036.583034.235520@c13g2000cwb.googlegroups.com... > Hi, > > I'm trying to do reads/writes to a flash device on our board using the > Microblaze processor. The part itself is the same as featured on the > Insight board for the XC2V1000 eval board. > > When I simply try and read back the manufacturer and id codes, I get > the value 0x00AA00AA instead - incorrect value. Any erase or write > operations also fail. > > I'm using EDK 6.3 and an opb_emc peripheral - I used to use an > opb_memcon (I think) on previous versions of the EDK and this worked ok > with the same board. > > It's a combined SRAM/Flash device and the SRAM works ok. I've no clue > why it now fails. > > Cheers, > > Pete. >Article: 78926
Hello All I want to learn more about Bus Functional Models Please advice me about that. Like What a BFM contains...? code for BFM written in which all languages ...? Any documents or sites anyone can suggest to read about how to make a BFM KedarArticle: 78927
> > Antti, > Thanks for the reply. > > This information applies to a V2Pro UltraController product and not to a > V4. > > I make a special test case where I stripped pretty much everything in the > deisng except the opb_sysace, and some gpio to toggle some led's and some > uart support for stdout. > > I got some code to fit entirely within the brams and loaded it into the > compact flash without any elf file stuff. When I boot via the CF, the > status led goes green with no lit error led. After it returns from the > XSysAce_IdentifyCF routine, the Signature field is 848A which appears > correct, but the NumCylinders is also 848A. > > The registers before rouitne is called are > cf dword 0 = 00000001 > cf dword 1 = 00150392 > cf dword 2 = 00000000 > cf dword 3 = 00000CED > cf dword 4 = 00000000 > cf dword 5 = 100C0200 > cf dword 6 = 00000802 > cf dword 7 = 000000B3 > The registers after XSysAce_IdentifyCF called > cf dword 0 = 00000001 > cf dword 1 = 003502B2 > cf dword 2 = 00000000 > cf dword 3 = 00000CED > cf dword 4 = 00000000 > cf dword 5 = 100C0200 > cf dword 6 = 00000802 > cf dword 7 = 000000B3 > > It looks like the reads of the buffer are not incrementing the FIFO that > would cause the IdentifyMemCard command to end. What bothers me is that > I appear to be able to read the other registers OK. > > I guess I might have to open a web case, wait for EDK6.3i to arrive, buy > Chipscope or borrow a scope, or apply a blow torch to the Memec SysAce > card:,) Usually Memec has pretty good reference designs, but this one did > not have an MPU interface one for the standalone sysace module. Of course > their baseline reference had a bunch of deprecated cores I ended up > converting to EDK6.2 sp3. Do you think sysace is going away to be > replaced by the platform flash stuff? I'm wondering if I should be > researching a more valuable target. > > -Thanks again, > > -Newman Just to achieve closure on this part of the thread, I found that OEN from the FPGA to the SysAce board was specified to the wrong location in the UCF. Arrgh. -NewmanArticle: 78928
"newman5382" <newman5382@yahoo.com> schrieb im Newsbeitrag news:68IOd.10408$pc5.2593@tornado.tampabay.rr.com... > > > > > Antti, > > Thanks for the reply. [snip] > > -Thanks again, > > > > -Newman > > Just to achieve closure on this part of the thread, I found that OEN from > the FPGA to the SysAce board was specified to the wrong location in the UCF. > Arrgh. > > -Newman Ahh! Good for you! With the V4LX25-ES the SystemACE doesnt seem to work! Be the reason whatever, at most 10 succesfully secotor reads with correct contents there comes an error that lock ups further communication with systemace So you are lucky I am not... I wonder that no-one from Xilinx has bothered to comment the issue SystemACE is working on ML401 and there is also LX25 on board so if there is an issue then Xilinx DOES know, or if there isnt a issue then I would be thankful if someone could confirm that systemace works ok with V4LX25-ES without using any special tricks. AnttiArticle: 78929
Do you have a link to those run time comparisons ? I would like to see what the relationship between different chips / os is? Thanx, nachumArticle: 78930
Hi Creative lazyness and sometimes simple waiting (or sleeping) is possible the most effective way to work! Ok, only sometimes: I did write FPGA bootloader for MMC Card (in MMC not SPI mode), I was about to write the SD Card version also, but that wasnt challenging at that time and I had no real urgent need. Some time ago I uploaded my IP Core to opencores, and now, guess what I dont have to work on the SD Card FPGA configuration core as it done already, possible at the time while I was a sleep. 39 hours ago a spiboot project was added to opencores, supporting FPGA config from both MMC or SD cards in SPI mode. My MMC card was 21 PLD macrocells, my estimate for MMC-SD card core was 50..55 PLD cells (in non SPI mode) and I was sure the MMC-SD card combined core in SPI mode would fit 36 Macrocells, - the spiboot from opencores (MMC+SD in SPI) - my synthesis gives 24 PLD cells so it defenetly fits XC9536 :) - please note that I have not verified the opencores spiboot with any hardware, it may not be working out of box, as it is the first release. (I know my core does work, it sits on SystemACE slot on VP20 and does work) Antti has a smile on the face todayArticle: 78931
hum, do you meen that you can use an MMC card connected to a CPLD to configure a FPGA? Is the MMC card formatted to any file system? What is the procedure? You copy the config file with a normal card read connected to your computer then connect this card to your app and that's it? "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:cufkhe$mt7$03$1@news.t-online.com... > Hi > > Creative lazyness and sometimes simple waiting (or sleeping) is possible > the > most effective way to work! > Ok, only sometimes: > > I did write FPGA bootloader for MMC Card (in MMC not SPI mode), I was > about > to write the SD Card version also, but that wasnt challenging at that time > and I had no real urgent need. Some time ago I uploaded my IP Core to > opencores, and now, guess what I dont have to work on the SD Card FPGA > configuration core as it done already, possible at the time while I was a > sleep. 39 hours ago a spiboot project was added to opencores, supporting > FPGA config from both MMC or SD cards in SPI mode. > > My MMC card was 21 PLD macrocells, my estimate for MMC-SD card core was > 50..55 PLD cells (in non SPI mode) and I was sure the MMC-SD card combined > core in SPI mode would fit 36 Macrocells, - the spiboot from opencores > (MMC+SD in SPI) - my synthesis gives 24 PLD cells so it defenetly fits > XC9536 :) - please note that I have not verified the opencores spiboot > with > any hardware, it may not be working out of box, as it is the first > release. > (I know my core does work, it sits on SystemACE slot on VP20 and does > work) > > Antti has a smile on the face today > >Article: 78932
"Mouarf" <mouarf@chezmoi.fr> schrieb im Newsbeitrag news:420b57fd$0$8202$636a15ce@news.free.fr... > hum, do you meen that you can use an MMC card connected to a CPLD to > configure a FPGA? > Is the MMC card formatted to any file system? > What is the procedure? You copy the config file with a normal card read > connected to your computer then connect this card to your app and that's it? yes! basically there are 2 options 1) you reformat the mmc-sd card with reserved sectors and copy the bitstream there 2) you can also just copy normal xilinx bitstream as generated by xilinx tools as first file to formatted mmc card this will also work, you overwrite the file later its ok too, as long as the bitstream file is located in sequential sectors. the above applies for xilinx, for altera it maybe require todo bitswap additionally a similar IP core is offered commercially by El Camino, they provide a windows utility also. (their price is 1900 EUR for source code license) AnttiArticle: 78933
fine, but now I get an error on that web site Warning: mysql_connect(): Can't connect to local MySQL server through socket '/var/run/mysqld/mysqld.sock' (2) in /var/www/fpga.de/tiki/lib/adodb/drivers/adodb-mysql.inc.php on line 318 Unable to login to the MySQL database 'fpgatiki' on 'localhost' as user 'fpgatiki' Go here to begin the installation process, if you haven't done so already. Can't connect to local MySQL server through socket '/var/run/mysqld/mysqld.sock' (2) Joerg > Joerg Ritter <ritter@informatik.uni-halle.de> writes: > > >>the compilation of the kernel module windrv6.ko under kernel 2.6.x >>using the distribution SuSE 9.2 fails. >>Here are my steps to get it work: [...] >>Maybe you should add this to the description of Hein Roehrig. > > > Thanks, I updated > <http://www.fpga.de/tiki/tiki-index.php?page=XilinxSoftwareLinux> > > -HeinArticle: 78934
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:cufldf$rj5$01$1@news.t-online.com... > 2) you can also just copy normal xilinx bitstream as generated by xilinx > tools as first file to formatted mmc card this will also work, you > overwrite > the file later its ok too, as long as the bitstream file is located in > sequential sectors. >Article: 78935
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:cufldf$rj5$01$1@news.t-online.com... > 2) you can also just copy normal xilinx bitstream as generated by xilinx > tools as first file to formatted mmc card this will also work, you > overwrite > the file later its ok too, as long as the bitstream file is located in > sequential sectors. > I did not checked into the code but how do you recognize the correct bitstream file in the card with the second method? To you look for the first time you meet a special set of bytes?Article: 78936
"Mouarf" <mouarf@chezmoi.fr> schrieb im Newsbeitrag news:420b5ae8$0$8186$636a15ce@news.free.fr... > > "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag > news:cufldf$rj5$01$1@news.t-online.com... > > > 2) you can also just copy normal xilinx bitstream as generated by xilinx > > tools as first file to formatted mmc card this will also work, you > > overwrite > > the file later its ok too, as long as the bitstream file is located in > > sequential sectors. > > > > > I did not checked into the code but how do you recognize the correct > bitstream file in the card with the second method? To you look for the first > time you meet a special set of bytes? For xilinx FPGAs it isnt necessary :) just dump all the mmc card from sector 0! FPGA will sync itself when the bitstream begins :) That is tested with my bootx core, my IP core also includes minimal emulation ip core that emulates the FPGA configuration internals (not complete) so I tested with MMC card connected to FPGA and did configure my "config emulator" later test where done with real XC9536 connected to VP20 AnttiArticle: 78937
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:cufm2s$sn6$01$1@news.t-online.com... > "Mouarf" <mouarf@chezmoi.fr> schrieb im Newsbeitrag > news:420b5ae8$0$8186$636a15ce@news.free.fr... > For xilinx FPGAs it isnt necessary :) just dump all the mmc card from > sector > 0! > FPGA will sync itself when the bitstream begins :) > with a card reader, are you sure that the first file will be at sector 0 in a just formatted MMC?Article: 78938
"Mouarf" <mouarf@chezmoi.fr> schrieb im Newsbeitrag news:420b5d65$0$8212$636a15ce@news.free.fr... > > "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag > news:cufm2s$sn6$01$1@news.t-online.com... > > "Mouarf" <mouarf@chezmoi.fr> schrieb im Newsbeitrag > > news:420b5ae8$0$8186$636a15ce@news.free.fr... > > > For xilinx FPGAs it isnt necessary :) just dump all the mmc card from > > sector > > 0! > > FPGA will sync itself when the bitstream begins :) > > > > with a card reader, are you sure that the first file will be at sector 0 in > a just formatted MMC? > No, it want be, but that doesnt matter :) the all content before the actual bitstream is dumped to FPGA as well it is discarded by FPGA config logic, as it is looking for sync word AnttiArticle: 78939
it sounds like : Does anyone can do it for me?? "Marco" <marcotoschi@email.it> a écrit dans le message de news: cuf9og$6da$1@news.ngi.it... > Hallo to everyone, > I should develop a microcontroller based on microblaze with keypad and > 320x240 graphic LCD for an university exam. > > I should also make a printer interface to print datas displayed on LCD. > > There is someone who could help me? > > Many Thanks in advance > Marco > >Article: 78940
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:cufmna$rnu$03$1@news.t-online.com... > No, it want be, but that doesnt matter :) > the all content before the actual bitstream is dumped to FPGA as well > it is discarded by FPGA config logic, as it is looking for sync word ok, I understand now, nice behaviour from the FPGA!Article: 78941
Hi Antti, Nearly 30-40% of the on chip real estate is spent on peripherals, which are hetrogenous in nature and have almost been neglected from a research perspective. my fun is I need to set up harware such that high speed i/o ports like USB, Firewire, gigabyte ethernet etc connected and put some load (eg : video file transfer) make all ports busy like video camera connected to firewire port, through usb port I need to connect one hard disk and store it, and through ethernet transfer this video file to clients. so in such scenario I want to profile or estimate on chip processor and peripherals interaction...for example i want to observe the usb port alone....during single file transer how many instrucions are executed by processor.. so for this above fun if I use pci slots for firewire and gigabyte ethernet ..it would be difficult to profile the i/o ports as all o f them were connected to pci bus-bridge watever..when I profile at on-chip i which load is from which port. so for the above task I need to connect an external board which has USB, gigabyte ethernet and firewire ports(PHY) to ML310 board through its expansion slots such that they have an direct interaction to main core. I dont want to the ports on ml310 as they are connected through PCI bus. hope now you got an better idea... thanks...Article: 78942
Hi, in one the last posts Christos recommended me to use Virtual Pins if I want the Fitter not to optimize registered unused signals away. I have a module "sie.vhd" instantiated in my top level schematic design file "top_d.vhd". The module "sie.vhd" has a port "Eop_not_recog" of type std_logic. It is a registered signal which is not used at all. (I use Altera QuartusII v 4.2). In the Assignment Editor under LOGIC OPTIONS --> ADVANCED I define a Virtual Pin by going to the NODE FINDER and selecting the signal "Eop_not_recog" of the entity "sie.vhd" with the filter "Register : pre-synthesis". Then I select ASSIGNMENT NAME=Virtual Pin, VALUE=On, ENABLED=Yes After compilation I go into the NODE FINDER again to see if "Eop_not_recog" is still listed with the filter "Registers : post-fitting", but it is not. I conclude from this that the fitter optimized the node away although I defined the node as a Virtual pin. Can someone explain to me what went wrong? Thank you for your help. RgdsArticle: 78943
Hi it seems USB device function core is available on opencores.com but not USB host controller core...does any one have an idea where to get host controller core for USB.... hmmm.....thanksArticle: 78944
Dear Helper,
I am currently a student at The Nottingham Trent University and
carrying out a project using an Actel 1280XL FPGA and Mentor Graphics
tools.
I have created a VHDL model purely using a behavioural architecture
using MGC Design Architect.
I then applied this model to Actel's ACTMap which is used to convert
the VHDL model into a netlist, a *.edn file and *.aml file is
successfully created.
I then apply this netlist to Actel Designer. In Designer I can compile
the netlist, place the pins using the PinEdit, after this I can then go
on to layout the design. Once the layout has been completed I can then
use the 'Extract' button to create a *.sdf file from which a timing
file is created.
The problem occurs when I apply back annotation and try to simulate the
design with the *.sdf file. I apply the .sdf to QuickHDL by using the
following in the command prompt: -
qhsim <design> -sdf<delays> <SDF file>
This will load up QuickHDL and then errors will occur, The errors are
as shown below:
ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'INBUF_7'
ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'MX_3'
ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'MX_3'
ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'INBUF_1'
ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'OUTBUF_10'
WARNING: home/biggc/fat.sdf: this file is probably applied to thw wrong
instance.
Ignoring subsequent missing instances from this file.
Failed to find any of the 8 instances from this file.
The file is probably intended for a lower-level instance, not the
top-level.
When the VHDL model has been applied to Actel Designer, the code is
converted into a circuit, i.e. I/O pad buffers are created etc. this is
what the errors seem to be referring to as I assume its trying to
simulate the VHDL code which doesnt contain these instances. Do I need
to simulate the .edn file (the netlist file) as well as the .sdf file?
and if so how do I achieve this?
The version of design manager I am using is Design Manager V8.6_2.1.
I hope I have explained the problem clearly so that you can understand
what is going on?
Thankyou for your help. Please feel free to contact me at any of the
following: -
CA204080@ntu.ac.uk
gavbiggs@yahoo.co.uk
Kind regards
Gavin Biggs
CA204080 (Uni Username)
BEng (Hons) Electronics & Computing
The Nottingham Trent University
Article: 78945"rickman" <spamgoeshere4@yahoo.com> wrote in message news:Wrqdneo8FpgSkpbfRVn-jw@adelphia.com... > Dave Colson wrote: > > Hi, > > > > Just wondering if anyone has used, or tried to use > > this device yet. I have a design I did for the ProAsic+ > > that I converted to use the PA3 as a test. Went fairly well. Only > > real issue I had was that when I set the option for Designer or move > > flip flops to the IO cells, it did not implement them correctly. > > Specifically the async resets where the wrong sense. Since The device I > > am targeting is not in production yet so I can only simulate the back > > annotated > > design. This is where I discovered the problem so I do not know if the > > problem > > is with the simulation model or with designer. > > > > I had a couple of problems with the Plus and notice some changes to the PA3 > > data sheet; primarily concerned with the JTAG TRST pin. Under the pin > > description > > section, They "recommend" the following: > > > > "TRST Boundary Scan Reset Pin > > > > The TRST pin functions as an active low input to > > asynchronously initialize (or reset) the boundary scan > > circuitry. There is an internal weak pull-up resistor on the > > TRST pin. In the operating mode, a 100 ? external pulldown > > resistor should be placed between TRST and GND > > to ensure that the chip does not switch into a different > > mode." > > > > I had a power-up problem on some of the Plus device and found out > > that if I ground the TRST pin , the device would start working. I > > report this to Actel and had them evaluate the parts that exhibited the > > problem. > > There recommendation: "ground the TRST pin". Sounds to me like there is a > > problem with the TAP port on both the Plus and PA3 devices and the > > 100 ? resistor is the "patch" to fix it. I am curious if anyone else has had > > problems with the TRST pin. > > > > The other problem I have had is a high programming failure rate > > while using the FlashPro programmer, mostly exit 11 errors. > > Actel was not able to helps us solve this problem. We did > > not press them on this since eventually we would be getting the > > devices programmed by our supplier and it would become > > a non-issue after that. The curious thing is that if a device successfully > > programmed the first time, it would more then likely always program > > successfully. I have reprogram a single device 50 to 60 times > > with no problem. I suspect a marginal problem with the device itself or > > a problem with the programming algorithm and not with my programming > > fixture. > > > > It bothers me that Actel will not admit problems with their devices. Xilinx > > has no problem with admitting problems with devices and then publishing > > a work around to the problem until a permanent fix to the silicon is > > implemented. > > Why is Actel reluctant to do this. Maybe this problem with the TRST was > > already > > know to them, and if they had published an errata on this then maybe I would > > not have > > spent over a week debugging this problem. > > > > Why do I use Actel if I am unhappy with there devices? the truth is it is > > the only > > reprogrammable FPGA that fit the application. > > > > Would like to hear about any experiences that other people have had with the > > Actel > > Flash parts. > > I am meeting with a sales rep and FAE on these products tomorrow, opps, > today. My main concern is that they are not slated to be out until Q4 > although I was told possibly Q3 (meaning end of Sept). I also want to > hear some real pricing instead of the "as low as xxx in quantity". > > I was told that the larger parts would be out first. So if you want a > $1.50 part you will need to wait until '06, I expect. > > The data sheet talks about being 5 volt tolerant, but they aren't. They > just do the same game of using resistors like the Virtex, etc. parts. > > I don't see the pulldown on the TRST as being much of a bug myself. My > experience has been that every part handles the JTAG signals in > different, often incompatible ways. But if you use the spec'd pull ups > or downs and use their cable the JTAG should work just like TI DSPs and > Xilinx FPGAs. > > I'll let you know what I find out from the FAE. I seem to remember that the JTAG spec requires(recommends) that TRST is optional. That is it is not require to perform any of the JTAG operations, including powering up. As far as a bug. We had 2 unexplained catastrophic field failures (parts actually were fried) of the Plus device before I was able to figure out the problem in the lab. Some of the parts that fail to power up correct started to go into thermally run away. Eventually they would overhead and destroy themselves. It is one think if it powers up brain dead but another when it destroy itself and half of the other components on the board. My main issue is the fact that they do not notify customer of problems with the device. I always felt like I was the only one having problems with the device, but I am not so sure now.Article: 78946
On 9 Feb 2005 06:20:28 -0800, andyesquire@hotmail.com wrote: >Hi, > >I'm working on a design that will require external memory, and I'm >trying to find some learning resources for Xilinx DDR SDRAM memory >The memory controller performance/specification isn't important to me >right now, but without being able to simulate a controller I can't >proceed further with my circuit design. I'm using ISE and ModelSim. > >Do I need to go down the Denali route and purchase a memory model then >lean on their technical support? Or should I just give up and get a >consultant to help? You may need a simulation model of the DDR SDRAM, this will let you simulate the controller core's interactions with the memory. Micron.com are pretty good about supplying useful VHDL simulation models for their memory devices. - BrianArticle: 78947
Ben Popoola escreveu: > Rick Fox wrote: > >> Hello, <snip> >> >> Rick Fox >> (Belmont Special School) >> Manchester, UK. > > > > Hi Rick, > > Unfortunately, the 'S' in the EPM7128SLC84 part indicates that this part > cannot be programmed with a byteblaster cable. The new part that can be > programmed is probably an 'A' part i.e EPM7128Axxx. > > It might be worth contacting an Altera FAE to see whether they are > willing to program these parts for you. > > Regards > Ben The S says it can be programmed with the BB cable, although the Jtag pins can be programmed as IO, disabling the Jtag interface with no way os bringing it back AFAIK without a master programmer. RicardoArticle: 78948
ALuPin wrote: > Hi, > > in one the last posts Christos recommended me to use Virtual Pins > if I want the Fitter not to optimize registered unused signals away. > > I have a module "sie.vhd" instantiated in my top level schematic design file > "top_d.vhd". > > The module "sie.vhd" has a port "Eop_not_recog" of type std_logic. > It is a registered signal which is not used at all. > > (I use Altera QuartusII v 4.2). > > In the Assignment Editor > under LOGIC OPTIONS --> ADVANCED I define a Virtual Pin by > going to the NODE FINDER and selecting the signal "Eop_not_recog" of the entity > "sie.vhd" with the filter "Register : pre-synthesis". > Then I select ASSIGNMENT NAME=Virtual Pin, VALUE=On, ENABLED=Yes > > After compilation I go into the NODE FINDER again to see if "Eop_not_recog" > is still listed with the filter "Registers : post-fitting", > but it is not. I conclude from this > that the fitter optimized the node away although I defined the node > as a Virtual pin. > > Can someone explain to me what went wrong? > > Thank you for your help. > > Rgds Somethin additional: Christos said: >One thing that might work is to drive them to outputs and then define >those >outputs as virtual pins with the assignment editor. >They will not be synthesised away. In the QuartusII Help it is said: >This option should be specified only for I/O elements that become nodes >when imported to the top-level design. So do I have to route the signal in the top level file to a FPGA pin and define it as VIRTUAL then or do I have to define the Port of the component "sie_rec.vhd" as virtual ? It is not explained very clear. Thank you. Rgds AndréArticle: 78949
gavbiggs@yahoo.co.uk wrote:
> I have created a VHDL model purely using a behavioural architecture
> using MGC Design Architect.
Consider running a vhdl simulation on
your model. Once this is working
as you expect, run a trial synthesis
and static timing analysis.
-- Mike Treseler
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