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Hello When I run the synthese with the XST, everything works fine until the optimization of one of my units. Optimizing unit <add> ... Optimizing unit <sub> ... Optimizing unit <crt> ... Optimizing unit <cub> ... FATAL_ERROR:MDT:Portability/export/Port_Main.h:127:1.53 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com Did anyone have the same error message? Is it possible that XST does not optimise my cub.vhd entity? Any other suggestions? Thanks a lot PhilippArticle: 78376
Falk Brunner wrote: > 2nd) you have Saprtan-3 which has DCI, Digital Controlled Impedance, so no > need for external termination, this can be done inside the FPGA. From what I read on this newsgroup LVDS_25_DCI essentially does not work if you have many inputs. At least it is not worth the hassle. (Webpower estimates 740mA supply current for 16 LVDS_25_SCI inputs at 480 Mbps). All the other DCI modes seem to be OK. Kolja SulimmaArticle: 78377
Symon wrote: > The data rate is somewhat unimportant. Well, it gives you an upper bound on the rise time. What's the rise time of the signals > into your spartan3? They are programmable from 150ps to 400ps. >Can you tell us what the driving part is? ADS5270 > Also, you should be aware that the trace length on the PCB is only part of > the signal path. There's also the leadframe/BGA package to consider. A rule > of thumb from that Howard Johnson chap, if the total signal path is less > than a sixth of the rise time, you're OK! Electric goes at about 160ps/inch. > Cheers, Syms. Thanks. I am pretty sure that I can disregard transmission line effects at these very short signal lengths. What I am concerned about is the current mode driver characteristic as described by Gabor. KoljaArticle: 78378
Jedi escreveu: > Ulf Samuelsson wrote: > <snip> > ps: And still no answer given regarding Atmel making EPCS chips > for Altera (o; > From other posts to this newsgroup, EPCS devices are EPCS1- ST's M25P10 and EPCS4 - M25P40. I still haven't tried, but some others here have and said it worked without problems. RicardoArticle: 78379
On Mon, 31 Jan 2005, Thomas Stanka wrote: > Hi, > > Wojciech Zabolotny wrote: > > I'm developing a system which will work in the irradiated area. > > One of the components is the triple redundant register with asynchronous > > loading from the control bus. Additionally the register's should be > > refreshed > > with the system clock. The control bus is asynchronous. > > Why not using a RT54SX (Of course its a big difference in price)? > It has the FF already TMR, and you got also a protected reset and clock > path. > When using the A54SX you will have trouble protecting Reset and Clock. Yes I know. The price of RT54SX was unacceptable for us :-(. There will be above 200 boards with that chip, and above 1000 boards with Xilinx'es... > > If you need a specific element, why not instanciating it by hand? > Well, I just couldn't discover how to instantiate the FF by hand in the Actel platform... -- Thanks, WojtekArticle: 78380
Ricardo wrote: > Jedi escreveu: > >> Ulf Samuelsson wrote: >> > <snip> > >> ps: And still no answer given regarding Atmel making EPCS chips >> for Altera (o; >> > From other posts to this newsgroup, EPCS devices are EPCS1- ST's M25P10 > and EPCS4 - M25P40. I still haven't tried, but some others here have and > said it worked without problems. > > Ricardo I know that..also tested it...see http://www.fpga.ch/forum/viewtopic.php?t=4 (o; Mostly every SPI serial flash using read byte command 0x02 can be used for Altera Cyclone chips...though not all are directly supported under Quartus programmer due to different device ID and different byte/page programming commands. But still no one can confirm what Lattice is saying (o; rickArticle: 78381
Anybody received LFEC20 samples from Lattice and using them? rickArticle: 78382
Hi, There is a hand-shaking protocol, between PROM and FPGA, which varies for different FPGA vendors. Specific to Xilinx FPGAs, the steps involved in configuration of FPGA are 1.Once the power supply voltage to PROM reaches above a pre-definced threshold, it asserts a signal, to reset all config. memory on FPGA. 2.Once all config. memory is reset, FPGA acknowldges PROM, and starts giving out clock to PROM. 3.When PROM receives clock and ack, it starts sending out the config,bits serially or parrallely( as per config. mode selected) through the data bits. 4.When final config. byte is received by FPGA and doing config, FPGA asserts DONE signal, which drives PROM to power save mode. FPGA stops sending clock also. I hope this will give an idea on how the configuration is done. For more details, you can refer to any PROM datasheet, which in detail describe with all the waveforms. sowjanyanarla@yahoo.com wrote: > Hi , > > I have general question regarding the Master Serial Programming > mode . In the Master Serial Programming mode , FPGA drives the clock . > But ,how will the FPGA know that there is relevant and complete data > present on the PROM . Is there any mechanism to tell the FPGA that the > configurable data is present on the PROM and FPGA to initiate the > clock. > > Thanks in Advance , > SowjanyaArticle: 78383
Probably your simprim library path is not correct. you can add your simprim library to Modelsim project. Or if you are intiating Modelsim from ISE diretctly, you can change the library locations in ISE itself.Article: 78384
Kolja Sulimma wrote: > Symon wrote: > > > The data rate is somewhat unimportant. > Well, it gives you an upper bound on the rise time. > > What's the rise time of the signals > > into your spartan3? > They are programmable from 150ps to 400ps. > > >Can you tell us what the driving part is? > ADS5270 > > > Also, you should be aware that the trace length on the PCB is only part of > > the signal path. There's also the leadframe/BGA package to consider. A rule > > of thumb from that Howard Johnson chap, if the total signal path is less > > than a sixth of the rise time, you're OK! Electric goes at about 160ps/inch. > > Cheers, Syms. > Thanks. I am pretty sure that I can disregard transmission line effects > at these very short signal lengths. What I am concerned about is the > current mode driver characteristic as described by Gabor. The parts I was referring to are DS90C031 quad drivers, which are sort of jelly-bean parts in a package pin-compatible with the venerable AM26LS31. These are much slower than the ADS5270 but do have current source outputs and will drive near the rails with no terminating resistor. What bothers me about leaving out terminators, especially in your case where you're not running 8b/10b or some other code with guaranteed AC content, is what happens when the output has been in one state long enough to generate a wide voltage spread. By the way, LVDS drivers in FPGA's are not current mode and wouldn't have this problem. It may be worth experimenting with the ADS5270 if you have a chance to hook one up without a load (maybe on an evaluation module) to see what the outputs do without termination. It would also be interesting to see how the TI evaluation module handles termination. The appnotes for the reference design from the Xilinx site don't mention the PC board issues. > > KoljaArticle: 78385
Wojciech Zabolotny wrote: > Hi All, > [snip] > The synthesis tool (FPGA Advantage) correctly recognizes the flip/flops, > however it implements them using the C-cells, so finally the device > utilization is ca. 170% ;-). > I don't know why it is impossible to implement my redundant FF using > the R-cell, similarly to the Xilinx LPM implementation above... > According to the diagram: http://www.actel.com/documents/A54SXADS.pdf > figure 1-2, the FF's in SXA architecture features independent Preset > and Clear inputs. So why the synthesis is not able to make use of them? > Maybe I should use a special LPM-like blocks to obtain it? > Are you saying that the synthesis uses only C-cells, or C-cells in addition to R-cells. Your fclr and fset inputs require gates, so an R-Cell could not implement the logic by itself. I think in Xilinx you would use a LUT as well as the adjacent flip-flop to implement each bit. > -- > Any help is appreciated, > best regards, > Wojtek Zabolotny > wzab@ise.pw.edu.plArticle: 78386
Kolja Sulimma wrote: > > From what I read on this newsgroup LVDS_25_DCI essentially does not > work if you have many inputs. At least it is not worth the hassle. > If you can live with the power hit and other quirks, it works. On S3, with the new DCIUpdateMode=Quiet setting, the bank-bank offset problem should go away. ( although with differential inputs, that only offsets the common mode of the differential input buffer, which might(?) have minimal effects on the prop. delay ) Watch the FPGA Cin reflections if you need to get that forwarded clock to both a local clock input and a global clock input- offhand, I'd do a flyby of the local clock pins (delay matched to the data lines) with isolation resistors feeding the local clock input, on to the global clock pins with provision for a differential attenuator ahead of the global inputs to damp out the reflection there. > > (Webpower estimates 740mA supply current for 16 LVDS_25_SCI > inputs at 480 Mbps). > Watch those mA and mW :) When I checked just now, Webpower still gives a hopelessly low static VCCO power estimate of 74 mW per bank overhead and 31 mW per input pair for S3. For V2, I found 200 mW per bank and 100 mW per pair far more realistic estimates of static LVDS_25_DCI power overhead (50 ohm VRP/VRN). > > All the other DCI modes seem to be OK. > No, all the parallel split termination modes have high power by their nature. On a short run, you could try increasing the value of VRP/VRN to maybe 75-100 ohms and see how things look in simulation. Another possibility to eliminate the per-bank overhead would be to try disconnecting the VRP/VRN resistors with a timed analog switch after configuration once the DCI updates have stopped. BrianArticle: 78387
Thank you, Eric, for quick answer. I have bought some pcs of XC4013E-PQ240-3C on eBay :) for my unprofit use in my hobby only. But I donīt understand what is role of PCI LogiCore, when CoreGen of older Foundations isnīt usable (... if I understand correctly). To generate correct pci.vhd for appropriate core only? But why arenīt downloadable pci.vhd-s for this purpose directly (e.g. on xilinxīs ftp)??Article: 78388
Hi, I experience problems with some "normal" IO's(not dual purpose IO's) on a Xilinx Virtex2p50ff1517. I observe that these IO change value during configuration and after configuration these IO are not high impedance as intended, but either high or low. These IO's are part of a processor interface where the other IO on this bus is high impedance. I have checked in FPGA Editor and find that there the "strange" IO's are implemented exactly as the "normal" IO's (the same signal is driving the output buffer). Do any of you have any suggestion to what have gone wrong. Is the chip damaged or is there something wrong with the configuration procedure. I tried both slave-serial and JTAG programming but the behaviour is the same. John -- Sendt med M2 - Operas revolusjonerende e-postprogram: http://www.opera.com/m2/Article: 78389
Hi,
I've been getting some strange behaviour compiling hierarchical
vhdl files in quartus. The code is a vhdl reworking of the pong.v & vga
files from fpga4fun.
When written as separate files with a top level .bdf or with a top level
.vhd instantiating the other files as components or any other variation of
multple files fails to synthesise correctly.
Regardless of which variation of the above is tried, it always synthesises
the same component.
When written as a single .vhd file with a .bdf for the pin connections
it synthesises correctly.
the initial structure of the files was
top-level.bdf-|
|
pong.vhd------|
|
hysnc.vhd-+
hsync was a dependency of pong.vhd and was the only code that
would actually be synthesised when the compiler focus was set to the
top-level .bdf in spite of the synthesis tool reporting 'found 2 design
units in pong.vhd' etc,etc.
compiling/sysnthesising pong.vhd on its own results in no errors.
Having googled without finding a solution, does anyone have any
suggestions. ( other than sticking with verilog :) as it's for a student
exercise)
--
Nigel Gunton Phone : +44/0 117 32 83167 /"\
Senior Lecturer, School of Electrical & Computer Engineering, \ /
CEMS, University of the West of England, Bristol. X
ASCII Ribbon Campaign against HTML email & microsoft attachments / \
Article: 78390I wrote: > > When I checked just now, Webpower still gives a hopelessly low > static VCCO power estimate of 74 mW per bank overhead and 31 mW per > input pair for S3. > Oops, that should have read "31 mw per input pin" not "per input pair"; i.e., they still seem to be using the 62.5 mW per pair DCI overhead number in the WebPower estimator tools. BrianArticle: 78391
Hello, how can I list unrouted nets in Xilinx' FPGAEditor via the command line? Is there a user's guide for the command line language? Bye TomArticle: 78392
Hello! I am using an Virtex-II Pro Development Board. I have written my own OPB-Slave-IPIF and included it into a design created by the EDK. As long as the IPIF was very simple everything worked without problems, but now the READ-Operations (direction: from IPIF to PPC) don't work any longer, because the PPC doesn't recognize my xferAck-Signal. In Software on the PPC I use the XIo_In32 and XIo_Out32 functions, in Hardware (IPIF) I use the signals OPB_Clk, OPB_RNW, OPB_Select, OPB_Adr, OPB_DBus, Slv_DBus and Slv_xferAck. Does somebody know, how I can solve this problem? Thanx, NorbertArticle: 78393
> how can I list unrouted nets in Xilinx' FPGAEditor via the command line? The closest command I can think of is "drc -all net". > > Is there a user's guide for the command line language? $XILINX\doc\usenglish\help\fpga_editor\fpga_editor.htm HTH, Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chipsArticle: 78394
Hi All, I have several BRAMs in my design each needs its own set of constants. So far I have used the ucf file to store my BRAM values. But it has become error prone and tedious. I would like to have a command for the ucf such that I can "link" a generated file in to the ucf and its format. Something like: MyBRAM => file:MyBramFile.dat where MyBramFile contains " 0000002800000028000000280000002800000028000000280000002800000028 0000002800000028000000280000002800000028000000280000002800000028 "...etc is this possible in some way? Regards, R.N.Article: 78395
In article <3668t9F4u7e1rU1@individual.net>, Symon <symon_brewer@hotmail.com> wrote: >I think Nick Weaver recently suggested the best method. Sue anyone who >steals your stuff. It's illegal. >Cheers, Syms. The original poster asked a different question. The question is maintaining confidentiality/security of the design process, not of the resulting (sold) product. This is often very annoying and very difficult. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 78396
Norbert Abel wrote: > Hello! > > I am using an Virtex-II Pro Development Board. > I have written my own OPB-Slave-IPIF and included it into a design > created by the EDK. As long as the IPIF was very simple everything > worked without problems, but now the READ-Operations (direction: from > IPIF to PPC) don't work any longer, because the PPC doesn't recognize > my xferAck-Signal. > In Software on the PPC I use the XIo_In32 and XIo_Out32 functions, in > Hardware (IPIF) I use the signals OPB_Clk, OPB_RNW, OPB_Select, > OPB_Adr, OPB_DBus, Slv_DBus and Slv_xferAck. > > Does somebody know, how I can solve this problem? Have you created a testbench and simulated the design? If not, then that is the way to solve the problem. -- My real email is akamail.com@dclark (or something like that).Article: 78397
OK, two different questions, but what I meant was that both have the same answer. Cheers, Syms. "Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message news:ctlpas$2cqe$1@agate.berkeley.edu... > In article <3668t9F4u7e1rU1@individual.net>, > Symon <symon_brewer@hotmail.com> wrote: > >I think Nick Weaver recently suggested the best method. Sue anyone who > >steals your stuff. It's illegal. > >Cheers, Syms. > > The original poster asked a different question. The question is > maintaining confidentiality/security of the design process, not of the > resulting (sold) product. This is often very annoying and very > difficult. >Article: 78398
In article <36783tF4tc4pbU1@individual.net>, Symon <symon_brewer@hotmail.com> wrote: >OK, two different questions, but what I meant was that both have the same >answer. >Cheers, Syms. Actually, tehy often have VASTLY different answers. Physical/corporate security is a PITA, depending on one's level of paranoia. for the properly paranoid, working at home is definatly NOT allowed. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 78399
Rick, Have you considered using a tool called Data2MEM? To find out more about it check out" http://tinyurl.com/6xlsu Shalin- Rick North wrote: > Hi All, > > I have several BRAMs in my design each needs its own set of constants. > So far I have used the ucf file to store my BRAM values. But it has > become error prone and tedious. I would like to have a command for the > ucf such that I can "link" a generated file in to the ucf and its > format. > > Something like: > MyBRAM => file:MyBramFile.dat > where MyBramFile contains > " > 0000002800000028000000280000002800000028000000280000002800000028 > 0000002800000028000000280000002800000028000000280000002800000028 > "...etc > > is this possible in some way? > > Regards, > R.N.
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