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Thanks a lot Thomas. I'm glad you've answered this so fast. I apologise for not posting an answer fast. That's because I was very busy these days with other things to do. Thomas Stanka (usenet_10@stanka-web.de) wrote: > ... > What to you mean with "user gates"? 2input-NAND? 4 input LUT > When an RH1020 is to small you need an RT54SX32S. But be aware, > there's currently a relability problem when using the RT54SX-S > devices. > I mean 2 input-NAND. Does anyone knows if Actel still manufactures obsolete and legacy rad-hard (or rad-tolerant) parts like RT1460A or RT54SX16 ? I think these parts would suit or needs. I will ask Actel about this. What reliability problem is this related to the RT54SX-S devices? Does this reliability problem affects RTSX-SU devices? Actel told me that RT54SX-X and RTSX-SU are based in the same design. The difference is that RT54SX-X parts are manufactured by MEC and RT54SX-SU are produced at UMC. > > ... availability of a similar or > > equivalent, in System Programmable (ISP), part would be a plus. > > When using the 5V IO, you will have trouble finding a reprogrammable > equivalent. > 3.3V FPGA would be fine. > > P.S: ASICs (Field Gate Arrays) would be OK, provided it cost less than > > US$10,000.00 and takes less than a month or two to be fabricated. In > > case we opt for an ASIC, only around 3-5 units would be produced. > > I know no alternative when spending 30-50k$ for that number. AFAIK > there are Actel fpgas above 10k$ per device. It seems that an ASIC is indeed very expensive. Anyone has a value for the cheapest rad-tolerant ASICs (around 1k 2input NAND-gates) ? Best Regards, Marcio.Article: 76401
Does anyone out there have any IP and documents on how to use SD cards ? Victor http://www.zertec.co.zaArticle: 76402
Just to fix what I think is a typo by Ray, the gain is actually |M*R|^N So, the bit growth is N*log2(RM). Pedantically, Syms. "Ray Andraka" <ray@andraka.com> wrote in message news:41AD1C9E.A4DEE522@andraka.com... > Check to make sure the integrator widths are correct (the gain is |N*R|^M). The > integrators need to be wide enough to accommodate the gain. I suspect your > widths are OK since you get the same result as the coregen macro, but check > anyway. Check the input signal to make sure the glitches are not being > introduced there. Make sure the input is 2's complement, not thermometer code. > > pete dudley wrote: > > > We planned on using the Xilinx Coregen core for the Cascade Integrator Comb > > CIC filter but I am finding peculiar glitches in its output. The parameters > > for the filter are R=decimation=10, N=stages=4, M=difference delay=1, > > Bin=input width=15. > >Article: 76403
http://groups.google.com/groups?q=flops+trust+synchronizer+setup/hold
-- Mike Treseler
Article: 76404
> > When you find out the answer please post a reply to the group. I
> >am facing the same problem. I am trying to configure the digilent
> >spartan-3 board using slave serial mode using a USB controller. The
> >same setup works for a spartan-II
> >but not for spartan-3. I already tried adding extra clocks. That did
> >not help.
>
OK I found the problem in my case. The USB controller pin which
connects to CCLK of FPGA, also connects to a user I/O pin of the FPGA.
I had this so that the USB controller could talk to the FPGA after
configuration and it was working for spartan-II becasue I guess that
user I/O pins are floating till the configuration completes. But in
case of spartan-3, the logic on these pins during configuration is
controlled by the HSWP_EN pin of the FPGA. The digilent board ties
this pin to GND thus making the user I/O pins to be pulled up to VCCO.
This was hurting cclk and the configuration. I rewired the connections
a little bit differently and its now working.
Sumit
Article: 76405Mike Treseler <mike_treseler@comcast.net> wrote in message news:<Mp6dnXq2T7b2dTDcRVn-uA@comcast.com>... > Patrick Kulle wrote: > > > Now I face the following problem. If I do the steps described above for > > a Spartan 2 I get results that show a difference of some percents which > > seem to be realistic. If I do the steps above for a Virtex 2 I get the > > _identical_ power consumption for all different types of encoding. > > Maybe the difference in power due to state encoding > is less than the uncertainty in the XPower measurement. > I expect that zero is closer to the right answer > than a few percent. I agree. For example if you implement a counter, the binary encoding and the one hot encoding toggle two bits per cycle on avarage, whereas the gray encoding toggles one bit per cycle. This means that in this case independently of the size of the counter the implementations differ only in one toggling flip-flop per cycle. For more irregular state machines of course the difference is larger, but I expect it still to be pretty small compared to the clock tree power. Kolja SulimmaArticle: 76406
Hello, I am about to develop a compact flash gps receiver for PDA (TDS Recon or PocketPC or others), and the power consumption is very critical. A senior CF developer suggested me to use low power microcontroller such as a simple PIC or an AVR (8 to 16 bits) for this type of application, other than FPGA/CPLD, because he thought FPGA is very expensive and very bad for critical consumption applications. I think he is right if I only want to do a simple interface between the GPS OEM and the PDA. However, I am thinking about to provide more functionalities and flexibilities, like to support "Sleep" mode of the GPS OEM to save power further and the customer can modify the sleep time from an utility software at PDA side. Moreover, I want to support all three modes of CF (Memory, I/O, and true IDE), (not sure how important they are). Could anybody please let me know which design is better for these functionalities, low-cost FPGA/CPLD, or low-cost DSP, or low power microcontroller? Thanks in advance. JohnsonArticle: 76407
Hi, This may sound like an odd thing to want to do, but is there anyway to take an EDIF file, have it mapped and placed and then turn it back into an EDIF file? Specifically I want to be able to do this targeting a Virtex FPGA. The reason I want to do this, is that I'm developing a design in JHDL, which seems to provide a nice interface for placing blocks of logic. For example, I can write 'place(blockA, RIGHT_OF, logicB)'. The catch seems to be, that for this to work blockA and blockB have to already have all their internal wires and logic placed. While technically I could do this manually, it is infeasible for the project I'm working on. So I'm hoping there might be some way I can take advantage of another feature of JHDL, which is the ability to parse and translate EDIF into a JHDL representation. Then perhaps there is some way I can have the EDIF placed for me by external tools. Is it the case that I'm simply asking for the impossible, wanting to place blocks logic relative to other logic blocks in a reasonably high-level and abstract way when targeting an FPGA? Thanks, JakeArticle: 76408
Austin Lesea wrote: > > Rick, > > Frankly, the Spartan team is not all that concerned about the (partial) > reconfiguration feature. I understand your situation, and I can > sympathize, but the "low cost" FPGA is diverging from the "high feature" > FPGA. I guess I don't understand how this is an issue. The current parts support partial reconfiguration in hardware. Even if it is not supported in hardware, a bitstream can be "modular" which would suffice to meet my needs. But it has to be supported in software. That is the issue for the Spartan 3 parts, not the hardware. > I would ask your contact at the factory about their plans in their new > family. They may decide to support it, or not. I did, but just like a year ago, I got an answer that says it is in the plan, but no dates are given. Frankly I don't see why this is an issue for the Virtex but not the Spartan devices. Using the modular reconfiguration capability of an FPGA can provide temendous compression of bitstream data if the design is truely modular. One of the big marketing/selling points of FPGAs is that the same hardware can be used to do different tasks at different times by reconfiguring them. The idea of modular configuration is just an extension of that to allow greater saving in hardware costs. If Sirius wanted to use an FPGA as an SDR with modular reconfiguration, do you think they would want to pay $50 for a Virtex or <$20 for a Spartan part? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76409
>Actually, I don't recall ever seeing a formula with the "a" >coefficient. I have always just worked with a variable F to account for >differences in the number of transitions. There is another factor of 2 to consider. If the clock is running at F, a FF can only toggle at F/2. Is your F the clock frequency or the frequency of a FF toggling on each clock tick? (bottom bit of a counter) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76410
Hi Terrence, SysGen currently only supports single processor designs. The work around is to create one half of a design in SysGen, and to export that to the EDK. From the EDK add in the required number of MicroBlazes and connect them up via the EDK-SysGen export. For example, have one Microblaze connect up to your SysGen logic, connect the ports that would otherwise link up to your second MicroBlaze to SysGen gateway blocks. When you export this design, the gateway ports will become toplevel ports in the exported pcore. You can than go into EDK and link the 'dangling' pcore ports to another MicroBlaze. Hope this helps. Cheers, shay Terrence Mak wrote: > Hi, > > Matlab SysGen provide a microblaze module that we can have the design of > microblaze processor together with other FPGA logic solely defined in the > SysGen design environment. But when I try to place more than one microblaze > module, says two microblaze communication through some FPGA logics, SysGen > fails to compile such a case. Are there any solutions to achieve > multi-microblaze in one chip? > > Many thanks, > Terrence > >Article: 76411
"Marcio A. A. Fialho" wrote: > > Does anyone knows if Actel still manufactures obsolete and > legacy rad-hard (or rad-tolerant) parts like RT1460A or > RT54SX16 ? I think these parts would suit or needs. > I will ask Actel about this. I know of an engineer at NASA who works with rad-hard parts. He has posted here in the past, but I have not heard from him lately. From an old post his email address is rk <stellare@NOSPAMPLEASE.erols.com> Obviously remove the NOSPAMPLEASE His name is Rick Katz, IIRC. I was going to do a little work for him once, but our schedules did not work out. He seems like a very nice guy and I am sure he would be happy to adivse you or point you to some sources. If he is swamped when you contact him, don't let that put you off. Just try again in a couple of weeks or so. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76412
Nicolas Matringe wrote: > > Hello > The question is in the subject: is there such a thing? > How to make an Altera post-p&r simulation work when a setup violation > occurs on an input register? How about synching the testbench data output to the chip input clock? I don't think there is any value to allowing the setup time to be violated in a simulation since there is no simulation equivalent to metastability. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76413
I think you can use an http interface at www.deja.com to read, search and reply to all newsgroups. Deja keeps posts going way back too! "Johnson" <gpsabove@yahoo.com> wrote in message news:b1ac2406.0411301627.2d01d19b@posting.google.com... > Thanks for the reply. > > I contacted our IT department, and they said that we do not have > access to NNTPserver, and NNTP access may leave your computer exposed > to viruses. In a word, they would not setup it for me. > > However, I still want to read it in my Outlook Newsreader. Does > anybody know a NNTP server for "public" so I can log on? I know > Microsoft provides "public" server for their own news groups, but I do > not know who can provide a NNTP server for comp.* groups. > > Thanks in advance. > > Johnson > > > > "John_H" <johnhandwork@mail.com> wrote in message news:<45Mqd.2$8%.765@news-west.eli.net>... > > "Johnson" <gpsabove@yahoo.com> wrote in message > > news:b1ac2406.0411291241.43e1f524@posting.google.com... > > > Hi there, > > > > > > I am a newbie and I do not know how to subscribe to the newsgroup > > > listed in the following website. Could anybody let me know what is the > > > server name for the newsgroup? I need it to fill the "Server > > > Information" of my "Microsoft Outlook Newsreader"? > > > > > > http://jupiter.sun.csd.unb.ca/usenet/comp.html > > > > > > Thanks. > > > > > > Johnson > > > > Your server information comes from your Internet Service Provider and is not > > a general internet value. If your ISP's webside doesn't contain a simple > > link to setting up the news server, call your tech support line. > > > > If you can't get the information or don't want to set up within Outlook's > > Newsreader, consider groups.google.com or - perhaps -groups.yahoo.com (you > > have a yahoo email account but I can't reach groups.yahoo.com from work).Article: 76414
Hi Rick, > Actually, I don't recall ever seeing a formula with the "a" > coefficient. I have always just worked with a variable F to account for > differences in the number of transitions. I guess the 'a' is just a suitable modifer for F so that readily available numbers can just be plugged in (i.e. fmax for FPGA). One example of many I have found that define 'a' is at: http://www.lowpower.de/charter/introduction.php (see section 3.2) Also, "Minimizing Power Consumption in Digital CMOS Circuits" by Chandrakasan seems be often referenced and defines such a term (alpha, on page 2, right-hand column). > The energy required to move charge onto a capacitor is Q*V. As you move > more charge onto the capacitor the voltage rises linearly with the > amount of charge so that V = Q/C. The total amount of energy stored on > the capacitor at any voltage is the integral of the V vs. Q curve which > is Int(V dQ) = Int(C*V dV) = 0.5 * C * V^2. If the capacitor is charged > fully from a constant voltage source via a resistor, the curve to > integrate is just a constant Vcc vs. Q which gives you an integral of C > * Vcc^2. If you want a power level you must multiply by F, the rate of > charging the cap (not discharging since that consumes no extra power, it > just dissapates the power stored in the cap). That gives you P = > F*C*V^2. So the whole "where did the 0.5 come from" question has no > answer. There is *no* 0.5 inherent in the equation. If someone wants > to change it by counting *both* the positive and negative transitions, > then you will have to multiply by 0.5 to compensate. Ok, in that case, my 1st option holds? 'a' is the transition density (0 to 1 and 1 to 0) at the node F is the clock freq C is the node capacitance V is supply voltage then P = 0.5aCV^2F where the 0.5 is modifying 'a' since 'a' is counting all transitions (0 to 1 and 1 to 0) instead of just the power consuming ones (0 to 1)? Cheers, KenArticle: 76415
Hi Hal, (snip) > There is another factor of 2 to consider. If the clock is running > at F, a FF can only toggle at F/2. > > Is your F the clock frequency or the frequency of a FF toggling > on each clock tick? (bottom bit of a counter) I think that this must be taken care of in the 'a' term so that the clock freq can just be plugged in to F. In http://bwrc.eecs.berkeley.edu/Classes/Icbook/SLIDES/slides4a.pdf they actually modify the C term with transition probability and call it "effective capacitance"! One example they give for the probability of a 0 to 1 transition for a 2 input NOR gates comes out to 3/16 which is multiplied with C but is effectively the 'a' term we have been discussing I believe. KenArticle: 76416
Jacob Bower wrote: > > Hi, > > This may sound like an odd thing to want to do, but is there anyway to take > an EDIF file, have it mapped and placed and then turn it back into an EDIF > file? Specifically I want to be able to do this targeting a Virtex FPGA. > > The reason I want to do this, is that I'm developing a design in JHDL, which > seems to provide a nice interface for placing blocks of logic. For example, > I can write 'place(blockA, RIGHT_OF, logicB)'. The catch seems to be, that > for this to work blockA and blockB have to already have all their internal > wires and logic placed. While technically I could do this manually, it is > infeasible for the project I'm working on. > > So I'm hoping there might be some way I can take advantage of another > feature of JHDL, which is the ability to parse and translate EDIF into a > JHDL representation. Then perhaps there is some way I can have the EDIF > placed for me by external tools. > > Is it the case that I'm simply asking for the impossible, wanting to place > blocks logic relative to other logic blocks in a reasonably high-level and > abstract way when targeting an FPGA? Since you are targeting Virtex parts, you can use the Xilinx RLOC attributes to place your logic in a relative way. I know this can be done from VHDL and Verilog, but I know nothing about JHDL. Can JHDL provide attributes in a way that the Xilinx software can understand? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76417
Thanks, Dave, that's the sort of strategy I was looking for.Article: 76418
Rickman, > Since you are targeting Virtex parts, you can use the Xilinx RLOC > attributes to place your logic in a relative way. I know this can be > done from VHDL and Verilog, but I know nothing about JHDL. Can JHDL > provide attributes in a way that the Xilinx software can understand? Ultimately, the place functions in JHDL map down to RLOC properties in the EDIF output. I could also explicitly annotate things with EDIF properties if I wanted. The problem with using RLOCs directly, firstly is that (as far as I understand them anyway) they only let me place individual logic elements like flip-flops for example. They won't let me place a macro-block which contains two multipliers and an adder for example. Not at least without first manually placing all the sub-elements of the multipliers and adder anyway, which brings me back to my original problem. The second problem is that RLOCs require relative co-ordinates specified in rows, columns and slice. This is useless if I want to say "put large logic A right of large logic B" or even perhaps "put small logic A and the bottom left hand corner of large logic B". In theory this should be possible in JHDL. At least this is my understanding, please correct me if I am wrong. - JakeArticle: 76419
Kolja Sulimma wrote: > Mike Treseler <mike_treseler@comcast.net> wrote in message > news:<Mp6dnXq2T7b2dTDcRVn-uA@comcast.com>... >> Patrick Kulle wrote: >> >>> Now I face the following problem. If I do the steps described above >>> for a Spartan 2 I get results that show a difference of some >>> percents which seem to be realistic. If I do the steps above for a >>> Virtex 2 I get the _identical_ power consumption for all different >>> types of encoding. >> >> Maybe the difference in power due to state encoding >> is less than the uncertainty in the XPower measurement. >> I expect that zero is closer to the right answer >> than a few percent. > > I agree. For example if you implement a counter, the binary encoding > and the one hot encoding toggle two bits per cycle on avarage, whereas > the gray encoding toggles one bit per cycle. > This means that in this case independently of the size of the counter > the implementations differ only in one toggling flip-flop per cycle. > > For more irregular state machines of course the difference is larger, > but I expect it still to be pretty small compared to the clock tree > power. > > Kolja Sulimma Hello Mike, Hello Kolja, thank you for your posts. Before I had a look at the power consumption using XPower I simulated the FSM absolutely technology independent and only observed the switching activity. The difference between the best and the worst encoding is up to 40 percent of the switching activity. The results for the Spartan 2 match with the results I got when I only observed the switching activity of the state-bits. Even if they are not so good. The results for the Virtex 2 are equal for each encoding, there is not even a difference between two encodings of more than 1 mW. If I try the same experiment using a CoolRunner 2 I get different results for different encodings again. I'm just wondering If there is anything else that could cause this behavior of the results? Thanks Patrick PS: Currently I'm not trying to optimise a specific circuit to a specific target but trying to check where power can be saved.Article: 76420
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message news:coikr1$11p9$1@agate.berkeley.edu... > I'm doing a pretty complex state machine, which is perfect for in > memory (blockRAM based) encoding. > > Before I go through and build my own state machine compiler out of > python hack-scripts or Excel macros, does someone already have such a > compiler available? picoblaze might be a good fit. HTH, Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chipsArticle: 76421
Rick, I will forward this thread to my buddy in Spartan land. I'm on your side here. But the XC4VLX15 is not going to be a $50 part, and at 13,824 logic cells, 864 Kb of BRAM, 32 DSP48's, and four DCM's, that might be just the right choice for a SDR design. I think that a Spartan part that could do the same thing would be much larger, and probably more costly just due to the lack of the hard IP? But, you are right: whatever solves the problem is going to win, and if Spartan could have had the socket if they had made some other decisions, maybe that would be a good thing. I'll let you know what kind of response I get. Austin rickman wrote: > Austin Lesea wrote: > >>Rick, >> >>Frankly, the Spartan team is not all that concerned about the (partial) >>reconfiguration feature. I understand your situation, and I can >>sympathize, but the "low cost" FPGA is diverging from the "high feature" >>FPGA. > > > I guess I don't understand how this is an issue. The current parts > support partial reconfiguration in hardware. Even if it is not > supported in hardware, a bitstream can be "modular" which would suffice > to meet my needs. But it has to be supported in software. That is the > issue for the Spartan 3 parts, not the hardware. > > > >>I would ask your contact at the factory about their plans in their new >>family. They may decide to support it, or not. > > > I did, but just like a year ago, I got an answer that says it is in the > plan, but no dates are given. > > Frankly I don't see why this is an issue for the Virtex but not the > Spartan devices. Using the modular reconfiguration capability of an > FPGA can provide temendous compression of bitstream data if the design > is truely modular. One of the big marketing/selling points of FPGAs is > that the same hardware can be used to do different tasks at different > times by reconfiguring them. The idea of modular configuration is just > an extension of that to allow greater saving in hardware costs. > > If Sirius wanted to use an FPGA as an SDR with modular reconfiguration, > do you think they would want to pay $50 for a Virtex or <$20 for a > Spartan part? >Article: 76422
Thanks, When I clicked the link you provided, it led me to http://groups.google.com/ Yes, I can read and reply from here. However, it will take me more than 4 hours to see my new posts. I think it is too slow. John "pete dudley" <padudle@sandia.gov> wrote in message news:<41ae216b$1_1@news3.es.net>... > I think you can use an http interface at www.deja.com to read, search and > reply to all newsgroups. Deja keeps posts going way back too! > >Article: 76423
Yep, you are correct. I've designated N as the delay and M as the order as
long
as I can remember. I didn't notice that you have them the other way around
until
you corrected me.
Symon wrote:
> Just to fix what I think is a typo by Ray, the gain is actually
> |M*R|^N
> So, the bit growth is N*log2(RM).
> Pedantically, Syms.
> > > for the filter are R=decimation=10, N=stages=4, M=difference delay=1,
> > > Bin=input width=15.
> > >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 76424
John,
There is something you can do about it: use a local copy of the control
signal and put a keep buffer on it. The snippet below is a simple VHDL
example:
signal lcl_ce std_logic;
attribute syn_keep boolean;
attribute syn_keep of lcl_ce:signal is true;
begin
lcl_ce<= ce;
process(clk)
begin
if rising_edge(clk) then
if lcl_ce='1' then
q<=d;
end if;
The keep buffer causes the local signal to be named differently so that
the local signal doesn't exceed the fan out limit. That keeps all the local
destinations for the control signal on the same named net, which in turn
keeps them able to be mapped with the desired placement. The keep
buffer itself is removed during PAR. Use a separate local copy for each
register.
For the LUTs, if you keep the logic to a single level between FFs, the
mapper does a pretty decent job at keeping the LUT with the FF.
Unfortunately, it doesn't do so well keeping a LUT near a second LUT
when there is no FF between, and as you mention, the combinatorial
names are not always consistent from run to run, especially with tool
version changes in the mix. You can do a little better with the names
by using the syn_keep on the intermediate signal to force a particular
partitioning of the logic between LUTs, and it will usually keep the name
of the forced signal on the first LUT (but not always; depends on the tool).
Hope that helps!
john jakson wrote:
> This brings up 1 little gripe with XST mapper.
> When a ck en has large fanout and drives many different regs of
> different widths, the FF driving the enables will be split into clones
> (good part) but often the branches will enable groups of FFs that is
> less optimal and cuts across a slice pair.
>
> In my cpu project, with some 20 regular 16b regs on 1 enable I get
> told to remove 1 FF from the middle of a few of these regs because of
> this odd splitting which is tiresome. Its too early to manually split
> such enables.
>
> Are there any switches to force grouping of replicated FF signals to
> stay within pairs? Timing driven placement seemed to help, as well as
> not placing the ck enable FFs.
>
> My other gripe about floorplanning is the LUT structures/names are
> liable to change on me even if the logic that created it doesn't so I
> try not to place those since they tend to get placed/pulled near the
> connected FFs that I did place. Still lots to learn:-)
>
> regards
> johnjakson_usa_com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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