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Adarsh Kumar Jain wrote: > > Should we ever get to that ? > I know typically A and X bother recommend 80-85% resource usage and so do a > lot of others > But besides having no provision for expansion of design and probably > extremely long p&r times, what are the other dangers of such a high resource > utilisation, if our clock is only 40 MHz. > Also what if we are using all 8 Rocket IOs in a device ? Most of the area of an FPGA is routing. Maybe you should try to maximize the useage of that. Sounds like you could gain more efficiency there than in the LUT usage. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76326
>Do I have to add some CCLK cycles after I have sent the last data? I >recognized there are a bunch of new settings in the ISE6.3 in comparison >to the 4.1 which I used for the Spartan XL. Try it. Faster than waiting for answers from a newsgroup. There have been (many?) problems in that area. A few extra clocks won't cost much. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76327
In article <41ACB09D.75F34B34@yahoo.com>, rickman <john@bluepal.net> wrote: >Most of the area of an FPGA is routing. Maybe you should try to >maximize the useage of that. Sounds like you could gain more efficiency >there than in the LUT usage. Except that because of marketing and perception reasons (tehre's no good way to say "routing utilization" that users currently understand), the routing is significantly overprovisioned for most designs to allow high chip utilization. Running at high utilization is a LOT easier if a large amount of the logic is floorplanned/placed, it makes both placement easier and routing easier. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 76328
Ken, A commont confusion is what dissipates power? When you charge a node, you waste power in the resistance of the charging transistor. When you discharge a node, you then waste power in the resistance of the discharging transistors (both generate heat). If both edges generate heat, then you have to count them both. The energy stored in a capacitor is 1/2 CV^2, but don't let that confuse you: you have to put it in, and then take it out! The devices that do the work dissipate the power. Austin Ken wrote: > Hello folks, > > I often see the following equation to define the dynamic power consumption > of a node in a CMOS circuit: > > P = aCV^2F > > where: > > > P = dynamic power > > a = ** average number of times in a clock cycle a node with capacitance C > will make a power consuming transition ** > > V= supply voltage > > F = clock rate > > > My question is related to the definition of 'a'. In a CMOS related paper I > have seen 'a' defined as the average number of "0 to 1" transitions in a > clock cycle since that is when power is drawn from the supply (half being > stored in the cap and half being dissipated in the node). The 1 to 0 > transition does not draw power from the supply, only the power previously > stored in the cap on the 0 to 1 transition is dissipated. > > However, in some FPGA related papers, I see 'a' being defined as the > probability of a 0 to 1 or a 1 to 0 transition during a clock cycle. > > Hence my confusion... > > Can anyone shed any light on why this might be (or are the FPGA papers I've > seen just wrong)? > > Many thanks for your time, > > Ken > > >Article: 76329
>> Hello, >> >> I am new with CPLD and Verilog. I have made some code and posted >> on comp.lang.verilog but nobody responded. >> >> I need help. I don't know if this code works. I don't know how >> to make a test module. (I am using ISE Webpack 4.2 and MXE). > > We have a simple VGA circuit that we implemented on XC9572 CPLDs and > XC4000 FPGAs described at http://www.xess.com/appnotes/vga.pdf. > > We also have a newer VGA design for Spartan2/3 described at > http://www.xess.com/appnotes/an-101204-vgagen.pdf. This one uses a FIFO > made from a BlockRAM as an input buffer, but you can strip that out and > use the VGA generator at its core. > > The timing values for your horizontal and vertical sync look correct. > But your logic seems to increment both the Xcounter and Ycounter on each > clock edge. (I'm not very conversant in Verilog, so I could be wrong.) > You need to increment the Ycounter only when the Xcounter is reset to > zero at the end of each scanline. A clock enable is the best way to do > this. > > Your state machine looks like it does the horizontal timing and then > tries to do the vertical timing after that. These are not sequential > processes. The horizontal and vertical timing proceed in parallel > together. Your code looks like it outputs a single horizontal scanline > and then it waits for the Ycounter to increment and overflow to start a > new frame. Probably not what you want. > > Also, you need to set RGB to 1 (indicating active video, I guess) when > Xcounter is less than 800 and Ycounter is less than 600. This is the > active video portion of the frame. You don't want active video during > the vertical or horizontal retrace and it looks like you only test for > the horizontal. > > As for testing, you only have two inputs: clock and reset. Just give it > a clock in your simulator and see what the horizontal and vertical syncs > look like. That will tell you immediately if you have a problem. If you > need to test actual hardware, there are several boards that have VGA > ports you can use to drive a monitor. We even have a few at > www.xess.com. Thank you for your comments. I am now trying to make a test module. I will post the results here in the group. Regards.Article: 76330
"John_H" <johnhandwork@mail.com> wrote in message news:3y1rd.8$8%.1119@news-west.eli.net... > "Adarsh Kumar Jain" <adarsh.jain@cern.ch> wrote in message > news:coi7rq$nce$1@sunnews.cern.ch... >> Should we ever get to that ? >> I know typically A and X bother recommend 80-85% resource usage and so do > a >> lot of others >> But besides having no provision for expansion of design and probably >> extremely long p&r times, what are the other dangers of such a high > resource >> utilisation, if our clock is only 40 MHz. >> Also what if we are using all 8 Rocket IOs in a device ? > > You're worried because you have 99% slice utilization? Don't! Check your > LUT and register usage and you'll find you're probably *well* under the > 99% > mark. The P&R software tends to spread things around in the fabric, one > element per slice until the slices are each occupied with something, then > begin to backfill the extra slice resources to get the design in the part. > It seems inefficient, but it's what we have to deal with. > > I look forward to the day when the slice components are be freely > rearranged > by the P&R software; why have two registers locked together at the map > phase > when P&R needs to make the tough decisions? > > Reference Xcell journal Issue 50 Fall 2004 Introduced in September 2003, ISE 6 adds a new timing driven map option that helps get better design utilization for your FPGA devices, particularly if the device is already 90% utilized. Timing driven map is a next generation enhancement to ISE physical synthesis placement with logic slice packing for Virtex-II, Virtex-II Pro and Spartan-3 devices to improve placement quality for unrelated logic. I think I tried using this with ISE 6.2i with Spartan-3. Looked to me like it was a keeper. -NewmanArticle: 76331
Hi there, We have a bunch of Virtex-II Pro AFX boards we're using to build a single larger system. Currently we have a Parallel Cable IV programmer, and thus have to program each board individually. What we'd like to do is be able to program all the boards at the same time. The AFX boards all have upstream and downstream System ACE ports, and this seems to be a suitable interface to use, but I'm a bit confused as to what programmer and cabling I need to take advantage of this interface. Looking at the programmer on the Xilinx web site, the one that would appear to fit is the MultiPRO Desktop Tool: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&key=HW-MULTIPRO This lists System ACE support in the data sheet, but doesn't explain how to actually do that. The 20 pin port on the side of the MiltiPRO device would appear to be similar to the System ACE interface pin out on the AFX board, but the descriptions don't match perfectly. Is it possible to use this device with a set of suitable ribbon cables to hook up a set of AFX boards and program all the V2P devices at once? Any information greatly appreciated! Cheers, -- Michael Dales University of Cambridge Computer Laboratory http://www.cl.cam.ac.uk/~mwd24/Article: 76332
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message news:coibq8$up9$1@agate.berkeley.edu... > Running at high utilization is a LOT easier if a large amount of the > logic is floorplanned/placed, it makes both placement easier and > routing easier. Spot on, Nicholas. One further point; often the time you spend on Floorplanning is more than recovered in P&R times, certainly for repeatedly used RPMs. Cheers, Syms.Article: 76333
In article <313t6uF37n91nU1@uni-berlin.de>, Symon <symon_brewer@hotmail.com> wrote: >"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message >news:coibq8$up9$1@agate.berkeley.edu... >> Running at high utilization is a LOT easier if a large amount of the >> logic is floorplanned/placed, it makes both placement easier and >> routing easier. >Spot on, Nicholas. One further point; often the time you spend on >Floorplanning is more than recovered in P&R times, certainly for repeatedly >used RPMs. And don't forget the performance win. I have a deliberately dinky 3 pipeline stage encryption core: placing just PART of the core allows the 125 MHz timing to be met easily, with a vast fraction of the tool time. RLOC is your friend. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 76334
Austin Lesea wrote: > All, > > The question is: what to do with Vbatt if not used? > > If it is not used, then it really is a 'don't care'. You could float > it, connect it to ground, or connect it to a Vcco. > > But if you let it float, it is a very low leakage pin (obviously, as you > do not want to let the battery die from leakage). > > A very low leakage pin is also a very sensitive pin to ESD damage. > > So when we tested it for ESD, we decided to change the documentation to > say to ground it if not used. > > If it gets zapped by an ESD discharge, it will have bad leakage. It is > most unlikely to cause any other problems, but why take the risk? > > So, you are correct, in that we are correcting a problem. It is a very > small, and very unlikely problem (customer removes part where Vbatt was > left floating, Vbatt was zapped with an ESD discharge, and then uses it > in an application where Vbatt is used, and the battery ends up running > down in less than 25 years). .. and field replacement of a battery, where the Vbatt is much more physically exposed, is OK, or is High Risk ? - ie just what is the ESD rating of the Vbatt pin ? -jgArticle: 76335
Ken wrote: > Hello folks, > > I often see the following equation to define the dynamic power consumption > of a node in a CMOS circuit: > > P = aCV^2F > > where: > > > P = dynamic power > > a = ** average number of times in a clock cycle a node with capacitance C > will make a power consuming transition ** > > V= supply voltage > > F = clock rate > > > My question is related to the definition of 'a'. In a CMOS related paper I > have seen 'a' defined as the average number of "0 to 1" transitions in a > clock cycle since that is when power is drawn from the supply (half being > stored in the cap and half being dissipated in the node). The 1 to 0 > transition does not draw power from the supply, only the power previously > stored in the cap on the 0 to 1 transition is dissipated. > > However, in some FPGA related papers, I see 'a' being defined as the > probability of a 0 to 1 or a 1 to 0 transition during a clock cycle. > > Hence my confusion... > > Can anyone shed any light on why this might be (or are the FPGA papers I've > seen just wrong)? Where logic devices quote a Power Dissapation capacitance ( most glue logic does ), they adjust the 'C' so you plug in F ( ie that's two edges ) The C is thus more a modeling value, to get the Power/Freq to Fit. Nailing F is also not simple, as decode glitches and runt pulses can cost power, and real power is a combinaton of Clock Tree, and D-Q loadings. Measure of a real operating device is always a good idea :) -jgArticle: 76336
I've made a board with CS8900 for proto of NIOS Development kit board. It works very strange, I read internal registers and sometimes they was read correctly but in generaly incorrectly. Writing is correctly as seem to me. I'm using core of SOPC. Maybe someone gives me some advise. Thx.Article: 76337
Hi folks, I'm working on developing an embedded system with a xilinx v2pro fpga. I have all my code for the ppc (including 2 block rams, one on the plb and the other on the opb) done in xps, and exported it to the project navigator. I am trying to add an additional block rom, but I don't want to add it in the EDK, I just want it to communicate directly with fpga fabric. So, I used the core generator, and created a bram instance that is 70 bits wide, and 8k deep. The core generator doesn't create a .bmm or .mem file to accompany this. So how do I go about adding the proper lines to the current bmm file? I haven't found much for documentation on this. If I don't add any information for the new ram to the bmm file created by xps, then when I import the projnav files back into xps, and regenerate the bitstream, data2mem errors out on me. Currently, my bmm file looks like this: ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xffffc000:0xffffffff] BUS_BLOCK top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 [63:56] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_1 [55:48] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_2 [47:40] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 [39:32] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_4 [31:24] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_5 [23:16] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_6 [15:8] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; ADDRESS_BLOCK opb_bram_if_cntlr_1_bram RAMB16 [0x00000000:0x00003fff] BUS_BLOCK top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0 [31:28] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_1 [27:24] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_2 [23:20] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_3 [19:16] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_4 [15:12] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_5 [11:8] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_6 [7:4] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_7 [3:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; I'm not entirely sure how the rom needs to get assigned in the fpga. I was thinking of adding a line such as: ADDRESS BLOCK pattern_rom RAMB16 [0x00040000:0x00042000] END_ADDRESS_BLOCK; (where "pattern_rom" is my rom I added in the fpga from the coregen) But, I'm not sure how to complete the BUS_BLOCK section. Any help would be appreciated! Thanks, -- Matt maplante@iol.unh.eduArticle: 76338
Erik Walthinsen wrote:
(snip)
> always @(posedge clk) begin
> if (prev_lrclk != lrclk)
> int_strobe = 1'b1;
> else
> int_strobe = 1'b0;
> prev_lrclk = lrclk;
> end
A FF to latch the previous value, an XOR gate to indicate
that the current value is different, and another FF to
latch the output of the XOR gate.
I might have written it:
int_strobe = prev_lrclk ^ lrclk;
prev_lrclk = lrclk;
but otherwise...
-- glen
Article: 76339What is the motivation for exporting it back to XPS? What is the nature of the data2mem errors? Maybe I had a similar but different problem that you have. I had code located in external flash. I modified the bmm file and added some stuff similar to Xilinx answer record 16577. I added the modified bmm file to the ISE project, but did NOT include the elf file. I let the tool crank out a bit file, then I manually invoked data2bram using the tag option, which IIRC indicates to data2ram, which block to load up. If I did not do this, it would try to load up the external reference and "error out". -Newman -------------------------------------------------------------------------------------- "Matthew Plante" <maplante@iol.unh.edu> wrote in message news:coih22$k99$1@tabloid.unh.edu... > Hi folks, > > I'm working on developing an embedded system with a xilinx v2pro fpga. I > have all my code for the ppc (including 2 block rams, one on the plb and > the other on the opb) done in xps, and exported it to the project > navigator. I am trying to add an additional block rom, but I don't want > to add it in the EDK, I just want it to communicate directly with fpga > fabric. So, I used the core generator, and created a bram instance that > is 70 bits wide, and 8k deep. The core generator doesn't create a .bmm or > .mem file to accompany this. So how do I go about adding the proper lines > to the current bmm file? I haven't found much for documentation on this. > If I don't add any information for the new ram to the bmm file created by > xps, then when I import the projnav files back into xps, and regenerate > the bitstream, data2mem errors out on me. > Currently, my bmm file looks like this: > ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xffffc000:0xffffffff] > BUS_BLOCK > top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 > [63:56] ; > top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_1 > [55:48] ; > top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_2 > [47:40] ; > top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 > [39:32] ; > top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_4 > [31:24] ; > top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_5 > [23:16] ; > top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_6 > [15:8] ; > top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_7 [7:0] > ; > END_BUS_BLOCK; > END_ADDRESS_BLOCK; > ADDRESS_BLOCK opb_bram_if_cntlr_1_bram RAMB16 [0x00000000:0x00003fff] > BUS_BLOCK > top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0 > [31:28] ; > top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_1 > [27:24] ; > top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_2 > [23:20] ; > top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_3 > [19:16] ; > top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_4 > [15:12] ; > top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_5 > [11:8] ; > top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_6 [7:4] > ; > top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_7 [3:0] > ; > END_BUS_BLOCK; > END_ADDRESS_BLOCK; > > I'm not entirely sure how the rom needs to get assigned in the fpga. I > was thinking of adding a line such as: > ADDRESS BLOCK pattern_rom RAMB16 [0x00040000:0x00042000] > END_ADDRESS_BLOCK; > (where "pattern_rom" is my rom I added in the fpga from the coregen) > But, I'm not sure how to complete the BUS_BLOCK section. > > Any help would be appreciated! > > Thanks, > > -- Matt > maplante@iol.unh.edu >Article: 76340
"newman5382" <newman5382@yahoo.com> wrote in message news:fo4rd.107164$6w6.1499@tornado.tampabay.rr.com... > What is the motivation for exporting it back to XPS? What is the nature > of the data2mem errors? > > Maybe I had a similar but different problem that you have. I had code > located in external flash. I modified the bmm file and added some stuff > similar to Xilinx answer record 16577. I added the modified bmm file to > the ISE project, but did NOT include the elf file. I let the tool crank > out a bit file, then I manually invoked data2bram using the tag option, > which IIRC indicates to data2ram, which block to load up. If I did not do > this, it would try to load up the external reference and "error out". > > -Newman > Oops, I included the original bmm file from xps into project_nav, and manually invoked data2bram using the tag option. I created a new bmm file with the external flash reference to get a mem file which I had to modify, to load into Modelsim. - Newman > -------------------------------------------------------------------------------------- > "Matthew Plante" <maplante@iol.unh.edu> wrote in message > news:coih22$k99$1@tabloid.unh.edu... >> Hi folks, >> >> I'm working on developing an embedded system with a xilinx v2pro fpga. >> I have all my code for the ppc (including 2 block rams, one on the plb >> and the other on the opb) done in xps, and exported it to the project >> navigator. I am trying to add an additional block rom, but I don't want >> to add it in the EDK, I just want it to communicate directly with fpga >> fabric. So, I used the core generator, and created a bram instance that >> is 70 bits wide, and 8k deep. The core generator doesn't create a .bmm >> or .mem file to accompany this. So how do I go about adding the proper >> lines to the current bmm file? I haven't found much for documentation on >> this. If I don't add any information for the new ram to the bmm file >> created by xps, then when I import the projnav files back into xps, and >> regenerate the bitstream, data2mem errors out on me. >> Currently, my bmm file looks like this: >> ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xffffc000:0xffffffff] >> BUS_BLOCK >> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 >> [63:56] ; >> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_1 >> [55:48] ; >> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_2 >> [47:40] ; >> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 >> [39:32] ; >> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_4 >> [31:24] ; >> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_5 >> [23:16] ; >> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_6 >> [15:8] ; >> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_7 >> [7:0] ; >> END_BUS_BLOCK; >> END_ADDRESS_BLOCK; >> ADDRESS_BLOCK opb_bram_if_cntlr_1_bram RAMB16 [0x00000000:0x00003fff] >> BUS_BLOCK >> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0 >> [31:28] ; >> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_1 >> [27:24] ; >> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_2 >> [23:20] ; >> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_3 >> [19:16] ; >> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_4 >> [15:12] ; >> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_5 >> [11:8] ; >> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_6 >> [7:4] ; >> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_7 >> [3:0] ; >> END_BUS_BLOCK; >> END_ADDRESS_BLOCK; >> >> I'm not entirely sure how the rom needs to get assigned in the fpga. I >> was thinking of adding a line such as: >> ADDRESS BLOCK pattern_rom RAMB16 [0x00040000:0x00042000] >> END_ADDRESS_BLOCK; >> (where "pattern_rom" is my rom I added in the fpga from the coregen) >> But, I'm not sure how to complete the BUS_BLOCK section. >> >> Any help would be appreciated! >> >> Thanks, >> >> -- Matt >> maplante@iol.unh.edu >> > >Article: 76341
I'm doing a pretty complex state machine, which is perfect for in memory (blockRAM based) encoding. Before I go through and build my own state machine compiler out of python hack-scripts or Excel macros, does someone already have such a compiler available? -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 76342
"newman5382" <newman5382@yahoo.com> wrote in message news:gA4rd.85069$8G4.64560@tornado.tampabay.rr.com... > > "newman5382" <newman5382@yahoo.com> wrote in message > news:fo4rd.107164$6w6.1499@tornado.tampabay.rr.com... >> What is the motivation for exporting it back to XPS? What is the nature >> of the data2mem errors? >> >> Maybe I had a similar but different problem that you have. I had code >> located in external flash. I modified the bmm file and added some stuff >> similar to Xilinx answer record 16577. I added the modified bmm file to >> the ISE project, but did NOT include the elf file. I let the tool crank >> out a bit file, then I manually invoked data2bram using the tag option, >> which IIRC indicates to data2ram, which block to load up. If I did not do >> this, it would try to load up the external reference and "error out". >> >> -Newman >> > > Oops, I included the original bmm file from xps into project_nav, and > manually invoked data2bram using the tag option. I created a new bmm file > with the external flash reference to get a mem file which I had to modify, > to load into Modelsim. > > - Newman Answer record 16577 seems to be a little old. I also referenced dev.pdf, which contains more information concerning data2mem. It is located under the Xilinx install directory. - Newman > >> -------------------------------------------------------------------------------------- >> "Matthew Plante" <maplante@iol.unh.edu> wrote in message >> news:coih22$k99$1@tabloid.unh.edu... >>> Hi folks, >>> >>> I'm working on developing an embedded system with a xilinx v2pro fpga. >>> I have all my code for the ppc (including 2 block rams, one on the plb >>> and the other on the opb) done in xps, and exported it to the project >>> navigator. I am trying to add an additional block rom, but I don't want >>> to add it in the EDK, I just want it to communicate directly with fpga >>> fabric. So, I used the core generator, and created a bram instance that >>> is 70 bits wide, and 8k deep. The core generator doesn't create a .bmm >>> or .mem file to accompany this. So how do I go about adding the proper >>> lines to the current bmm file? I haven't found much for documentation on >>> this. If I don't add any information for the new ram to the bmm file >>> created by xps, then when I import the projnav files back into xps, and >>> regenerate the bitstream, data2mem errors out on me. >>> Currently, my bmm file looks like this: >>> ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xffffc000:0xffffffff] >>> BUS_BLOCK >>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 >>> [63:56] ; >>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_1 >>> [55:48] ; >>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_2 >>> [47:40] ; >>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 >>> [39:32] ; >>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_4 >>> [31:24] ; >>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_5 >>> [23:16] ; >>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_6 >>> [15:8] ; >>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_7 >>> [7:0] ; >>> END_BUS_BLOCK; >>> END_ADDRESS_BLOCK; >>> ADDRESS_BLOCK opb_bram_if_cntlr_1_bram RAMB16 [0x00000000:0x00003fff] >>> BUS_BLOCK >>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0 >>> [31:28] ; >>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_1 >>> [27:24] ; >>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_2 >>> [23:20] ; >>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_3 >>> [19:16] ; >>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_4 >>> [15:12] ; >>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_5 >>> [11:8] ; >>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_6 >>> [7:4] ; >>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_7 >>> [3:0] ; >>> END_BUS_BLOCK; >>> END_ADDRESS_BLOCK; >>> >>> I'm not entirely sure how the rom needs to get assigned in the fpga. I >>> was thinking of adding a line such as: >>> ADDRESS BLOCK pattern_rom RAMB16 [0x00040000:0x00042000] >>> END_ADDRESS_BLOCK; >>> (where "pattern_rom" is my rom I added in the fpga from the coregen) >>> But, I'm not sure how to complete the BUS_BLOCK section. >>> >>> Any help would be appreciated! >>> >>> Thanks, >>> >>> -- Matt >>> maplante@iol.unh.edu >>> >> >> > >Article: 76343
Austin Lesea wrote: > > Ken, > > A commont confusion is what dissipates power? > > When you charge a node, you waste power in the resistance of the > charging transistor. > > When you discharge a node, you then waste power in the resistance of the > discharging transistors (both generate heat). > > If both edges generate heat, then you have to count them both. > > The energy stored in a capacitor is 1/2 CV^2, but don't let that confuse > you: you have to put it in, and then take it out! The devices that do > the work dissipate the power. This is a bit misleading and irrelevant. The fact that power is only dissipated in the resistance has nothing to do with the total amount of energy expended in charging and discharging a capacitor. Regardless of what value resistance, even if it is not constant, the energy drawn from the supply is the same as long as the capacitor is charged to the same voltage. The energy may be dissipated in the transistor or in the poly track or a metal track or the bond wire or the external pin or even in the wire from the power supply to the board. But add them all up and you will get the same value each time you charge a capacitor to a given voltage. So the amount of power consumed is related to the frequency of transitions and the size of the capacitance. Whether you calculate it from the rate of the rising edges or both edges is not relevant, that just changes the constant that you use by a factor of 2. As the OP said, when you charge the cap from 0 volts to Vcc, half goes into the cap and half is wasted. But the total always comes from the PSU and is always the same amount. You can't have a 0 to 1 transition without a 1 to 0 transition, so why is this even an issue? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76344
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag news:coikr1$11p9$1@agate.berkeley.edu... > I'm doing a pretty complex state machine, which is perfect for in > memory (blockRAM based) encoding. > > Before I go through and build my own state machine compiler out of > python hack-scripts or Excel macros, does someone already have such a > compiler available? XST offers an option to put logic into BRAMS. But I dont know if it is smart enough to put the FSM into the BRAM. Regards FalkArticle: 76345
rickman wrote: (snip of (1/2) C V**2 discussion) > This is a bit misleading and irrelevant. The fact that power is only > dissipated in the resistance has nothing to do with the total amount of > energy expended in charging and discharging a capacitor. Regardless of > what value resistance, even if it is not constant, the energy drawn from > the supply is the same as long as the capacitor is charged to the same > voltage. The energy may be dissipated in the transistor or in the poly > track or a metal track or the bond wire or the external pin or even in > the wire from the power supply to the board. But add them all up and > you will get the same value each time you charge a capacitor to a given > voltage. > So the amount of power consumed is related to the frequency of > transitions and the size of the capacitance. Whether you calculate it > from the rate of the rising edges or both edges is not relevant, that > just changes the constant that you use by a factor of 2. As the OP > said, when you charge the cap from 0 volts to Vcc, half goes into the > cap and half is wasted. But the total always comes from the PSU and is > always the same amount. > You can't have a 0 to 1 transition without a 1 to 0 transition, so why > is this even an issue? The issue is where the factor of two goes. As previously said, when charging half is dissipated, and half goes into the capacitor. When discharging the rest is dissipated. For some designs it is easier to count total transitions than to count rising or falling transitions. Otherwise, yes, it doesn't matter as long as the 2 and 1/2 are in the right place. -- glenArticle: 76346
> It depends on your timing budget. There is a thing called a DLL that phase > locks the clock input to the destination synchronous clock input. It can > also double the frequency. It has the ability to adjust the phase of the > clock to null out the estimated first order delay of the IOB (note use of > FDDRCPE) and PCB transport delay. I have used the DLL's but the FDDRCPE is not something I know anything about? > If more precision is needed for temperature / voltage compensation, then maybe the feedback approach is > better. How do I make the feedback approach out of the IC? Do I just send out the clock to the IO-pin and then back to some other IO-pin after having been "around" the A/D? Or any special pins for this purpose? >>>>Rise-time/fall-time problems when attaching an A/D-converter to the same >>>>clock? >>> >>> >>>I like point to point routing where possible. You may be able to use a >>>clock >>>forwarding scheme (via an FDDRCPE instance) to achieve this. There are >>>also board deskewing schemes via feedback that may be suitable. I think >>>the feedback scheme necessitates a 'T' in the board routing. >> >>I'm stupid (or maybe I just haven't learned all this stuff yet) so please >>explain all these terms like "point to point routing", "clock forwarding >>scheme" and what do you mean by a "board deskewing schemes via feedback" >>and what is a 'T'? > > > I think my explanation was inadequate. What I meant by point to point is > that there are only two component connection involved in routing the trace > on the PCB (There may also be a series source termination resistor in the > path). I believe that the feedback scheme wants a minimum of three > component connections. One from the FPGA output pin to the destination, > and an equal length path from the FPGA output pin to the FPGA feedback pin. Which means that I should add a "clock-line" on the PCB from the output-pin to the A/D. And from the same output just "draw" a line exactly as long as the line to the A/D, but know to a pin on the FPGA (feedback)? How should the clock be terminated on the board-layout (I must say - i never made a PCB design - this will be my first - sounds silly, but we are educated using already made development boards) I somehow don't see how these attempts make sure that the outside clock is different from the same signal just inside the IC. I guess that somehow you will need two clock-lines (one to the internal and one for the external). If you have time for making a simple "point-to-point" example of the clock-net circuit (on the board that I should produce), please feel free to do so. I haven't got much time up to christmas and I'm very new to this High speed era of electronics, and somehow my bachelor starts tomorrow, so the PCB should be finished quite soon so I can start on my project. > I've never used the feedback method, but I suspect that I would research > "Source Termination of Multiple Clock Lines" section 11.5 "High-Speed > Digital Design A Handbook Of Black Magic" by Howard Johnson and Martin > Graham where there is a short segment from the output clock pin to two > series resistors (what I called the "T") to two lines of equal length and > the loads at each end are balanced. Thanks (but the money as a student is very small, so maybe the library can be used - i'll try so).. Thanks for all your help, and very sorry about my very bad english! / PrebenArticle: 76347
usmgn wrote: >>>I use xilinx shematic editor. >>>On a wire i trying to place two I/O markers (same name ?), but the editor >>>say : "Error : net 'xxx' is already a port with a polarity value 'output' >>> >>> >>" >> >> >>>I want do this for wiring facility on the uper level schema. >>> >>> >>>Any solution ? >>> >>> >>think! >>(sometimes helps) >> >>add a dummy buffer to split the wire before connecting to iopad/marker >> >> > > >I had thought of that but i was not on that would not have perverse effects >(i debute with FPGA). > > > It will have no effect. The synthesis just gets rid of anything that doesn't affect the final outputs of the logic. JonArticle: 76348
All valid points. 99% utilization is probably the slice usage, not the LUT
usage, so you may still have plenty of margin (you are really between 50% and
99% LUT utilization, check the map results for LUT and memory usage. At 40 MHz,
you will probably not have a problem if you were smart about your design (no
logic with layer upon layer of LUTs). As the device gets filled, you may find
that routing starts becoming an issue. That can be mostly alleviated by doing
some floorplanning. Many of our designs have LUT utilization above 80%. The
PAR times can get long, especially with less than optimal placement. At 40 MHz,
you may also be able to take advantage of a multiplied clock to reduce logic
should you get painted into a corner. I think you've got plenty of wiggle room
to get out of a tight spot if you get there in future design spins. You may
have to be smart about the design to fit a larger change in.
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 76349Hello All I'm doing a Digital DownConverter application with an overall sampling rate reduction of 640. We want to use a so called CIC or Hogenauer filter for the first decimate by 10 then follow with five decimate-by-2 halfband filters to get 640. We are using a Xilinx VirtexII XC2V6000 to implement the hardware. We planned on using the Xilinx Coregen core for the Cascade Integrator Comb CIC filter but I am finding peculiar glitches in its output. The parameters for the filter are R=decimation=10, N=stages=4, M=difference delay=1, Bin=input width=15. I wrote a simulation testbench that sweeps a linear FM chirp accross the entire input Nyquist range and records the output data to a file. Every 1500 output samples there is a notable glitch of magnitude -30dB with respect to the filter full scale output. I keep input amplitude less than half what the input port should be able to handle (+-8192 into 15 bit port) Thinking that the core was bad I wrote my own CIC filter from the Hogenauer filter and it has exactly the same characteristics. With my own filter I can look at the internal integrators and differentiators and the glitches occur where there are general direction changes in the stage registers but with all that accumulator overflow going on its hard to analyze. Has anyone else encountered this general glitching with CIC filters? Can you see a systematic way to analyze such a problem? If interested I can share my filter design and testbench. Regards, Pete Dudley
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