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"Antti Lukats" <antti@case2000.com> wrote in message news:cobu4e$m14$01$1@news.t-online.com... > there is only one catch: > JTAG is accessible and you can do boundary scan, > etc when PROG is low, but programming over JTAG will fail. > PROG needs a pull-up in order to allow DONE go high Thanks for the tip. This would suggest that PROG is being pulled low unintentionally. I have no connections to this pin, which has a 4k7 pull-up on the FPGA board. However, the symptoms are so similar that I think it is worth trying a stronger pull-up to see if that helps. <solders 2k2 resistor on protoboard between PROG pin and 3V3> The 2k2 resistor in parallel with the 4k7 gives just under 1k5 pull-up. <tries programming multiple times> Hurrah! Seems to be working now. Thanks again for your invaluable tip! :-) K.Article: 76201
>>>Being able to write to a common RAM from two processes is not
>>>supported in VHDL as far as I am aware.
Sorry. I didn't read this carefully.
That is correct. Multiple processes can read
a ram signal, but only one can drive it.
My examples had one read-only process
and one read/write.
See Jim Lewis's posting for the single
process version. I have not tested this,
but I will on Monday. In the single process
case, it should be possible to use a normal
variable for the RAM array.
Note that design using a dual clock, dual write enable
ram is not complete until 1.synchronization
and 2.arbitration of writes to the same
location is worked out. That is why I
prefer the synchronous fifo approach.
-- Mike Treseler
Article: 76202Ian, So it goes. Training on the tools and familiarity is a big cost, I know. To decide to switch to another tool flow is often very painful, and expensive. But, that should not be the reason to NOT consider another product. That is what having training courses (either on your site for larger audiences, or at 'Xilinx U') is all about. http://www.support.xilinx.com/support/services/education.htm We have trained entire departments of engineers to take advantage of our features. Have fun, Austin Ian & Hilda Dedic wrote: > Austin > > Obviously if one vendor has an overriding advantage for a particular > application then they'll be used -- so is somebody really needs an FPGA > with 10Gb/s I/O now or in the near future they've got a choice of Brand > X or Brand X...:-) > > But if they're already using Brand A and it suits them and their > engineers are familiar with the tools and so on, I don't want to have to > tell them to switch. > > If being the best always won we'd now be dumping Betamax video recorders > for DVD rather than VHS, I'd probably be writing this on a Mac not a PC, > and Bill Gates would be flipping burgers. If only... > > Ian > > austin wrote: > >> Ian, >> >> Most customers are not stupid: if they see their competition using >> Xilinx, and beating them, they are unlikely to remain so fixated on a >> particular vendor. >> >> I understand that there are Altera customers who are so committed, >> that they will not consider any other solution. >> >> The oppsoite is true, as well. >> >> I don't think we need to discuss it here. More intersting are folks >> who want the best features, performance, support, software, cores, and >> tools. And are willing to examine all vendors. >> >> Those are the ones I want to reach. >> >> By the way, there are customers who believe that in order to keep both >> vendors alive, they have to intentionally switch every so often. >> >> AustinArticle: 76203
Kryten, What chip? Austin Kryten wrote: > The presence of the CPU in my project seems to prevent DONE going high. > > Nothing else in or connected to JTAG chain. > > CPU is 7 mA and under 2 MHz, so nothing exotic. > > Are flapping I/O pins likely to be disruptive? > > Or do RAM-based FPGA chips still draw big ICC during programming? > > XP / Xilinx ISE 6.2.03i bug perhaps? > > >Article: 76204
Hi Austin, at least with VirtexE there is no PROG pullup! or at least if the prog pin is floating then JTAG programming will yield in done not high error. I just looked at S3 and S2 datasheets s3 says week pullup s2 schematic doesnt show pullup, but I would defenetly always design in and prog pin pullup as extra, correct me if I am wrong, maybe for some families it is ok to leave prog pin open Antti "austin" <austin@xilinx.com> wrote in message news:cod4in$m5g3@cliff.xsj.xilinx.com... > Kryten, > > What chip? > > Austin > > Kryten wrote: > > > The presence of the CPU in my project seems to prevent DONE going high. > > > > Nothing else in or connected to JTAG chain. > > > > CPU is 7 mA and under 2 MHz, so nothing exotic. > > > > Are flapping I/O pins likely to be disruptive? > > > > Or do RAM-based FPGA chips still draw big ICC during programming? > > > > XP / Xilinx ISE 6.2.03i bug perhaps? > > > > > >Article: 76205
Hi emrah, > Thanks for your clues, but the signal I need is optimized away. Let me > explain my problem in detail: We have a memory in our design and the > inputs of this memory are optimized away. And my job is to get the > exact delay of the memory! Sounds like there's a problem in your code. If the inputs are optimized away, the RAM disappears as well, and so will its outputs go as well etc etc. Any chance of you posting the code you're having trouble with? And, maybe, which version of the software you're using? Best regards, BenArticle: 76206
Hello,
I am new with CPLD and Verilog. I have made some code and posted
on comp.lang.verilog but nobody responded.
I need help. I don't know if this code works. I don't know how
to make a test module. (I am using ISE Webpack 4.2 and MXE).
Thanks.
---
http://www.terra.es/personal9/listaco/VGAsignal.html (Project)
Here goes:
======================================================================
/*
* VGA 800x600 @ 60 Hz Signal Generator using Verilog
* ==================================================
*
* Date: 25 November 2004
*
* Intended CPLD: Xilinx XC9536XL (or XC9572XL)
* Clock source: 40 Mhz (25 nanoseconds per pixel)
* Posted on comp.lang.verilog and es.ciencia.electronica
*
Timing diagrams:
================
(For more detailed information on timing, see:
http://www.epanorama.net/documents/pc/vga_timing.html)
A) Horizontal Line:
===================
A1 ---> 800 pixels (20 us) Horizontal active display
A2 ---> 40 pixels ( 1 us) Horizontal front porch
A3 ---> 128 pixels ( 3.2 us) Horizontal Sync.
A4 ---> 88 pixels ( 2.2 us) Horizontal back porch
==================================================
1056 pixels (26.4 us) Total Horizontal line (about 37.879 KHz)
B) Vertical timing:
===================
(A1+A2+A3+A4) * 600 lines --> (15840 us) Vertical active display
B (1 line) ----------------> ( 26.4 us) Vertical front porch
C (4 lines) ---------------> ( 105.6 us) Vertical Sync.
D (23 lines) ---------------> ( 607.2 us) Vertical back porch
=====================================
16579.2 us Total VGA Frame (about 60.31 Hz)
*/
module VGAsignal (clock, reset, RGB, Hsync, Vsync);
input clock;
input reset;
output RGB, Hsync, Vsync;
reg RGB, Hsync, Vsync;
reg [10:0] Xcounter; // 2^11 = 2048
reg [9:0] Ycounter; // 2^10 = 1024
parameter A1=0, A2=1, A3=2, A4=3, B=4, C=5, D=6;
reg [2:0] CurrentState, NextState;
always @(Xcounter or Ycounter or CurrentState) // Next state logic
begin
NextState = A1;
case (CurrentState)
A1 : begin
if (Xcounter == 800) NextState = A2;
else NextState = A1;
end
A2 : begin
if (Xcounter == 840) NextState = A3;
else NextState = A2;
end
A3 : begin
if (Xcounter == 968) NextState = A4;
else NextState = A3;
end
A4 : begin
if ((Xcounter == 1056) & (Ycounter == 600)) NextState = B;
else NextState = A4;
end
B : begin
if (Ycounter == 602) NextState = C;
else NextState = B;
end
C : begin
if (Ycounter == 606) NextState = D;
else NextState = C;
end
D : begin
if (Ycounter == 628) NextState = A1;
else NextState = D;
end
endcase
end
always @(posedge clock or posedge reset) // Current state logic
begin
if (reset)
begin
CurrentState = A1;
Xcounter = 0;
Xcounter = 0;
end
else
begin
CurrentState = NextState;
if (Xcounter == 1057) Xcounter = 0;
else Xcounter = Xcounter + 1;
if (Ycounter == 629) Ycounter = 0;
else Ycounter = Ycounter + 1;
end
end
always @(CurrentState) // Output logic
begin
case (CurrentState)
A1 : begin
RGB = 1; Hsync = 0; Vsync = 0; // Active RGB
end
A2 : begin
RGB = 0; Hsync = 0; Vsync = 0; // Horizontal Front Porch
end
A3 : begin
RGB = 0; Hsync = 1; Vsync = 0; // Horizontal Sync.
end
A4 : begin
RGB = 0; Hsync = 0; Vsync = 0; // Horizontal Back Porch
end
B : begin
RGB = 0; Hsync = 0; Vsync = 0; // Vertical Front Porch
end
C : begin
RGB = 0; Hsync = 0; Vsync = 1; // Vertical Sync.
end
D : begin
RGB = 0; Hsync = 0; Vsync = 0; // Vertical Back Porch
end
default: begin
RGB = 0; Hsync = 0; Vsync = 0; // Is this needed?
end
endcase
end
endmodule
Article: 76207
Hi Cristian,
Just a note that the dedicated multipliers in Cyclone-II, Stratix and
Stratix-II (i.e. Embedded multipliers or DSP blocks) can implement full
width 18x18 signed *and* unsigned multipliers. Unsigned multipliers are
supported explicitly, and are not just a special case of signed multipliers.
So for the sample code you gave, it will be implemented in one 18x18
dedicated multiplier.
Hope this helps.
Subroto Datta
Altera Corp.
"cristian" <cas7406@yahoo.com> wrote in message
news:9e825b8b.0411201308.3eb63985@posting.google.com...
>I am doing some test with the Spartan III multipliers. I have tried
> the following simple code:
>
> entity mac_ex is
> generic (width: integer := 18) ;
> port ( a,b : in std_logic_vector (width-1 downto 0);
> final_res: out std_logic_vector((width*2)-1 downto
> 0));
>
> end mac_ex;
>
> architecture behave of mac_ex is
> begin
>
> final_res <= a * b;
>
> end;
>
> The map report states that the above code will be implemented in 3
> (three) 18x18 multipliers when 'width' is equal to 18. Does any of you
> have an explanation for needing 3 18x18 multipliers?.
>
> Note: when 'width' is equal to 17, just one 18x18 multiplier is
> needed. I am using the WebPack 6.2.03 version
>
> thanks,
>
> cris
>
Article: 76208"austin" <austin@xilinx.com> wrote in message news:cod4in$m5g3@cliff.xsj.xilinx.com... > Kryten, > > What chip? It is a XC2S300E. Problem solved by decreasing pull-up resistor from 4k7 to 1k5. Mind you, I would have thought 4k7 a medium strength pull-up. I tend to use 10k weakest, 1k strongest.Article: 76209
I am a newbie of FPGA. Could anhybody please provide me some sample designs of FPGA, better for Compact Flash peripheral design. We will start a project by using FPGA for a Compact flash gps receiver. Thanks in advance. JohnsonArticle: 76210
RF <listacoESPAM@terra.es> wrote in news:43sqd.175936$r4.8918469@news-reader.eresmas.com: > > Hello, > > I am new with CPLD and Verilog. I have made some code and posted > on comp.lang.verilog but nobody responded. > > I need help. I don't know if this code works. I don't know how > to make a test module. (I am using ISE Webpack 4.2 and MXE). We have a simple VGA circuit that we implemented on XC9572 CPLDs and XC4000 FPGAs described at http://www.xess.com/appnotes/vga.pdf. We also have a newer VGA design for Spartan2/3 described at http://www.xess.com/appnotes/an-101204-vgagen.pdf. This one uses a FIFO made from a BlockRAM as an input buffer, but you can strip that out and use the VGA generator at its core. The timing values for your horizontal and vertical sync look correct. But your logic seems to increment both the Xcounter and Ycounter on each clock edge. (I'm not very conversant in Verilog, so I could be wrong.) You need to increment the Ycounter only when the Xcounter is reset to zero at the end of each scanline. A clock enable is the best way to do this. Your state machine looks like it does the horizontal timing and then tries to do the vertical timing after that. These are not sequential processes. The horizontal and vertical timing proceed in parallel together. Your code looks like it outputs a single horizontal scanline and then it waits for the Ycounter to increment and overflow to start a new frame. Probably not what you want. Also, you need to set RGB to 1 (indicating active video, I guess) when Xcounter is less than 800 and Ycounter is less than 600. This is the active video portion of the frame. You don't want active video during the vertical or horizontal retrace and it looks like you only test for the horizontal. As for testing, you only have two inputs: clock and reset. Just give it a clock in your simulator and see what the horizontal and vertical syncs look like. That will tell you immediately if you have a problem. If you need to test actual hardware, there are several boards that have VGA ports you can use to drive a monitor. We even have a few at www.xess.com. > > Thanks. > > --- > http://www.terra.es/personal9/listaco/VGAsignal.html (Project) > > > Here goes: > ====================================================================== > /* > * VGA 800x600 @ 60 Hz Signal Generator using Verilog > * ================================================== > * > * Date: 25 November 2004 > * > * Intended CPLD: Xilinx XC9536XL (or XC9572XL) > * Clock source: 40 Mhz (25 nanoseconds per pixel) > * Posted on comp.lang.verilog and es.ciencia.electronica > * > > Timing diagrams: > ================ > > (For more detailed information on timing, see: > > http://www.epanorama.net/documents/pc/vga_timing.html) > > A) Horizontal Line: > =================== > > A1 ---> 800 pixels (20 us) Horizontal active display > A2 ---> 40 pixels ( 1 us) Horizontal front porch > A3 ---> 128 pixels ( 3.2 us) Horizontal Sync. > A4 ---> 88 pixels ( 2.2 us) Horizontal back porch > ================================================== > 1056 pixels (26.4 us) Total Horizontal line (about 37.879 KHz) > > B) Vertical timing: > =================== > > (A1+A2+A3+A4) * 600 lines --> (15840 us) Vertical active display > B (1 line) ----------------> ( 26.4 us) Vertical front porch > C (4 lines) ---------------> ( 105.6 us) Vertical Sync. > D (23 lines) ---------------> ( 607.2 us) Vertical back porch > ===================================== > 16579.2 us Total VGA Frame (about > 60.31 Hz) > > */ > > > module VGAsignal (clock, reset, RGB, Hsync, Vsync); > > input clock; > input reset; > output RGB, Hsync, Vsync; > reg RGB, Hsync, Vsync; > > reg [10:0] Xcounter; // 2^11 = 2048 > reg [9:0] Ycounter; // 2^10 = 1024 > > parameter A1=0, A2=1, A3=2, A4=3, B=4, C=5, D=6; > > reg [2:0] CurrentState, NextState; > > > always @(Xcounter or Ycounter or CurrentState) // Next state logic > begin > NextState = A1; > case (CurrentState) > A1 : begin > if (Xcounter == 800) NextState = A2; > else NextState = A1; > end > A2 : begin > if (Xcounter == 840) NextState = A3; > else NextState = A2; > end > A3 : begin > if (Xcounter == 968) NextState = A4; > else NextState = A3; > end > A4 : begin > if ((Xcounter == 1056) & (Ycounter == 600)) > NextState = B; else NextState = A4; > end > B : begin > if (Ycounter == 602) NextState = C; > else NextState = B; > end > C : begin > if (Ycounter == 606) NextState = D; > else NextState = C; > end > D : begin > if (Ycounter == 628) NextState = A1; > else NextState = D; > end > endcase > end > > > always @(posedge clock or posedge reset) // Current state logic > begin > if (reset) > begin > CurrentState = A1; > Xcounter = 0; > Xcounter = 0; > end > else > begin > CurrentState = NextState; > if (Xcounter == 1057) Xcounter = 0; > else Xcounter = Xcounter + 1; > if (Ycounter == 629) Ycounter = 0; > else Ycounter = Ycounter + 1; > end > end > > > always @(CurrentState) // Output logic > begin > case (CurrentState) > A1 : begin > RGB = 1; Hsync = 0; Vsync = 0; // Active RGB > end > A2 : begin > RGB = 0; Hsync = 0; Vsync = 0; // Horizontal Front > Porch > end > A3 : begin > RGB = 0; Hsync = 1; Vsync = 0; // Horizontal Sync. > end > A4 : begin > RGB = 0; Hsync = 0; Vsync = 0; // Horizontal Back > Porch > end > B : begin > RGB = 0; Hsync = 0; Vsync = 0; // Vertical Front > Porch > end > C : begin > RGB = 0; Hsync = 0; Vsync = 1; // Vertical Sync. > end > D : begin > RGB = 0; Hsync = 0; Vsync = 0; // Vertical Back > Porch > end > default: begin > RGB = 0; Hsync = 0; Vsync = 0; // Is this needed? > end > endcase > end > > endmodule > -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 76211
gpsabove@yahoo.com (Johnson) wrote in news:b1ac2406.0411282101.2509ec30 @posting.google.com: > I am a newbie of FPGA. > > Could anhybody please provide me some sample designs of FPGA, better > for Compact Flash peripheral design. We will start a project by using > FPGA for a Compact flash gps receiver. > We have a Compact Flash / IDE disk interface described at http://www.xess.com/appnotes/an-041404-atacntl.pdf. This may serve as a starting point for your efforts. > Thanks in advance. > > Johnson -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 76212
Hi All: I have installed ISE6.3i and EDK 6.2i. When I run "platform studio" it show the following message: "$XILINX does not point to an ISE 6.2 installation" and does not work. I am wondering if there is any way to have EDK ruuning with ISE 6.3? Thank you in advance. MassoudArticle: 76213
Hello everybody, I want to connect a Xilinx CoolrunnerII (XC2c256) to the CAN-Bus. To make it easy I would like to use a ready to use CAN-bus driver chip (as much of the protocol implemented as possible). Any suggestions? How many of the CPLD resources does it take to initialize/communicate with the CAN-bus driver chip? Thanks for your help! Falk Salewski Embedded Software Laboratory RWTH Aachen University -----------------------------------------------------------------------Article: 76214
Dear All, I have a signal that enters to my MAX7000 Altera (nDS). This signal pass throught two D series flip-flops (synchronizer). I would like to assing a global routing signal for the output of the synchronizer. How to do that in QII and MAX7000, is it possible for the MAX7000S?. Any idea or recomendation? And also, the QII soft. recommends me to use a synchronizer also for the Reset Signal. If I use a syncronizer for the reset signal, should I connect the reset/presets of the D Flip-flops of the other synchronizers to the synchronized reset or to the not synchronized or not connect at all?. Thanks a lot and best regards, javiArticle: 76215
Falk Salewski <salewski@informatik.rwth-aachen.de> wrote: : Hello everybody, : I want to connect a Xilinx CoolrunnerII (XC2c256) to the CAN-Bus. To make : it easy I would like to use a ready to use CAN-bus driver chip (as much of : the : protocol implemented as possible). Any suggestions? How many of the CPLD : resources does it take to initialize/communicate with the CAN-bus driver : chip? There is a CAN Protocoll Controller at www.opencores.org Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 76216
Thank you very much for your reply. However what I am looking for is how difficult is it to connect a CPLD to a CAN-controller chip like the SJA1000 http://www-eu3.semiconductors.com/pip/SJA1000.html and how many of the CPLD resources it takes to initialize/communicate with this CAN-controller. bye Falk "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:coensd$mh6$1@lnx107.hrz.tu-darmstadt.de... > Falk Salewski <salewski@informatik.rwth-aachen.de> wrote: > : Hello everybody, > > : I want to connect a Xilinx CoolrunnerII (XC2c256) to the CAN-Bus. To > make > : it easy I would like to use a ready to use CAN-bus driver chip (as much > of > : the > : protocol implemented as possible). Any suggestions? How many of the CPLD > : resources does it take to initialize/communicate with the CAN-bus driver > : chip? > > There is a CAN Protocoll Controller at www.opencores.org > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 76217
Check the start-up clock is selected for JTAG(bitstream options) is something to check. Also if you have access check what the INIT line does during the configuration. May be some clues there. Also like everyone else I recommend checking the values of pullup resistors. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:Gx8qd.3023$FT3.1627@newsfe2-gui.ntli.net... > The presence of the CPU in my project seems to prevent DONE going high. > > Nothing else in or connected to JTAG chain. > > CPU is 7 mA and under 2 MHz, so nothing exotic. > > Are flapping I/O pins likely to be disruptive? > > Or do RAM-based FPGA chips still draw big ICC during programming? > > XP / Xilinx ISE 6.2.03i bug perhaps? > > >Article: 76218
woko wrote: > Hello! > > I want to revitalise a question at was asked in 2001, because I hope > something changed during the time. > > How can a AT49LV001 flash by programmed through a XC9536XL CPLD and > its JTAG-connector with really low cost? > > All address, data and control pins are connected to the CPLD, so ISP > via JTAG should be possible.I'm sure there are lots of tools available > at this time for programming, but still I don't want to pay >10k USD. > > Does anyone know if it's possible to program at flash with JAMPLAYER > sw from altera? How much effort would it be to implement flash > algorithms? > > regards, > > Wolfgang www.universalscan.com for boundary scan software www.amontec.com for jtag download cables and you are ready to go! LaurentArticle: 76219
For Virtex II: Vbatt - in some places in the datasheet and user manual it is advised to leave it open if not used, in other it is advised to connect it to Vaux or to ground. Maybe someone knows what is the right way to go? (in previous project I left it open, no problems noticed). DXN, DXP - can these pins be left open if not used? -- Regards RobertArticle: 76220
Falk Salewski wrote: > Thank you very much for your reply. > > However what I am looking for is how difficult is it to connect a CPLD to a > CAN-controller chip like the SJA1000 > http://www-eu3.semiconductors.com/pip/SJA1000.html > and how many of the CPLD resources it takes to initialize/communicate with > this CAN-controller. You'll need to setup the registers [either a rom in the CPLD, or a Serial EE holding the init values, to BUS], and then be able to poll messages, and manage TX packets (which come from where ?). All of these are not CPLD-centric tasks, so why not use a small uC instead - or even better, choose a uC with CAN on chip ? If you have the XC2C256 there already, needing > 128 MC for other tasks, then you could use a small portion, for SPI-SJA1000 bridge, and then use a small SPI uC for the CAN manager/init. Philips LPC9xx or Silicon Labs C8051F33x series would do this, in tiny 11-20pin packages. -jgArticle: 76221
Falk Salewski <salewski@informatik.rwth-aachen.de> wrote: : Thank you very much for your reply. : However what I am looking for is how difficult is it to connect a CPLD to a : CAN-controller chip like the SJA1000 : http://www-eu3.semiconductors.com/pip/SJA1000.html : and how many of the CPLD resources it takes to initialize/communicate : with this CAN-controller. : bye : Falk : "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im : Newsbeitrag news:coensd$mh6$1@lnx107.hrz.tu-darmstadt.de... : > Falk Salewski <salewski@informatik.rwth-aachen.de> wrote: ... Can communication needs some protocoll stack. Your question seems to be what implementing this stack in hardware needs with regards to hardware resources. My guess is that the 2c256 is too small for that task. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 76222
Jim Granville <no.spam@designtools.co.nz> wrote: : All of these are not CPLD-centric tasks, so why not use a small uC : instead - or even better, choose a uC with CAN on chip ? : If you have the XC2C256 there already, needing > 128 MC for other : tasks, then you could use a small portion, for SPI-SJA1000 bridge, and : then use a small SPI uC for the CAN manager/init. : Philips LPC9xx or Silicon Labs C8051F33x series would do this, in tiny : 11-20pin packages. Perhaps PicoBlaze for CoolRunner-II could be used too... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 76223
rickman <spamgoeshere4@yahoo.com> wrote in message news:<41A9EA9E.2B26BFB9@yahoo.com>... > Falk Brunner wrote: > > > > Hello everybody, > > > > Iam using ISE 6.2 with XST as synthesis tool. So far so good. But Now I have > > a design with plenty of timing margin (just 36 MHz ;-) and the goal is to > > fit it into a XC2S50E. > > At the end, it doesnt. > > So looking a little closer to the reports, I saw in the MAP report something > > like this. > > > > blabla > > 1000 LUTs used > > 300 LUTs used a s route-thru. > > > > How is this to understand? I understand it this way, that XST (and the other > > tools) use a LUT to feed data into a FF, but only 1 input is used, so the > > LUT has no real function, maybe only a inversion. Is this how it works? > > So how can I tell the software not to use LUTs as route thru, even if this > > will decrease timing performance? I mean it is tecnically possible to use th > > BY input to feed data into a FF. > > Are you sure this is the output from MAP? My understanding is that it > is the routing tool that will add route-thru LUTs, not the mapper. > There would be no point to the mapper adding them since it would have no > idea of where routing is a problem. http://groups.google.com/groups?selm=pan.2003.12.22.22.41.18.876240%40_NOSPAM_nc.rr.com MAP indeed documents the route-thru's, although I haven't been able to find any *detailed* information on how/when it decides to use route-thru or not (I assume it is routing congestion, but I was looking for a bit more detail than that). Nor did I find anything on how to influence their use. Anyone have ideas? > I am thinking that perhaps your synthesis tool is adding them because of > some mistaken option. I'd be real suprised if the synthesis tool did it, since you can syth a design using larger or smaller size targets than what you finally create a bit-stream for. > Or maybe your design won't fit anyway!!! I just > checked and the XC2S50 only has 864 LUTs ignoring the data sheet that > says 972. Does your design require 1000 *plus* 300 for routing or just > 700? This is what peaked my interest in wanting to know more about route-thru's. Regardless if he has 700+300 or 1000+300 (both of which easily exceed 864), the route-thru's are over 30% of his design - that strikes me as a huge percentage. Could this be caused by anything except a larger number of timing domains that are poorly placed? MarcArticle: 76224
Hi Kubik. You can also find boards in http://www.xess.com/ Good prices. Cheers, Hernán Sánchez "kubik" <jackgroups@interfree.it> escribió en el mensaje news:pan.2004.11.29.13.03.45.427048@interfree.it... > Forgive me for these stupid questions, but i'm a beginner in this field. > > I was searching on the web a Xilinx virtex2 board for doing my first > experience. > I' ve found many boards on the xilinx on line store ( the > HW-AFX family ) on the Avnet site ( ADS family ) and so on. But the prices > of these boards are all more then one thousand of dollars. > > Are these prices so high because with them is sold the design software too ? > > If so, and if i want to build a system in fpga i must buy many of these > boards, i don't need many copies of the design software. Are there others > expensive boards that need only to be programmed and cost much less? > > What shoud be the orientative value for the cost for piece that i must > sustain if i want to build a society that sells designs in FPGA? > > Thanks in advance >
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