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In article <34g7sqF49urriU1@individual.net>, Falk Brunner <Falk.Brunner@gmx.de> wrote: >> If you REALLY want to edit interconnect structure on a Xilinx FPGA, >> use one supported by JBits. But you really, REALLY don't want to. > >Is there a practical reason to do so?? >Cant think of such a reason. A researcher working on routing algorithms. A researcher looking to reroute designs to better handle partial configuration. A researcher looking at how to deal with a large board of flawed FPGAs (a'la the old HP system), especially with easypath parts testing the LUT fully but not fully testing the interconnect. >Regards >Falk > > > > > -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 77551
Kadir Solid Gold Suleyman wrote about California: > firearms have > essentially been de facto outlawed. Greg Lara wrote: > I don't understand this comment. All of my friends in San Jose and > surrounding communities own multiple firearms-long guns and hand guns > both. I can buy guns from at least 12 firearms emporiums less than 30 > minutes from my house. The state legislature hasn't actually completely banned them yet, but the Federal Ninth Circuit Court of Appeals ruled in Silveira v. Lockyer that the right to bear arms is not an individual right. Thus in the Ninth Circuit (including California) there is now no impediment to further and more draconian gun bans. On the other hand, the Justice Department recently published a report concluding that the right to bear arms *is* an individual right. It amazes me that otherwise rational people will maintain that the word "people" in the Second Amendment means something different than the same word when used in other Amendments such as the First Amendment. If the government required people to register and/or obtain a license before exercising their First Amendment rights, everyone would be outraged, but yet it seems that many think it is OK to require that for Second Amendment rights, or to disallow them entirely.Article: 77552
All, I saw this and thought of all those FPGAs out there on high speed busses. Quote:- "If you depend on ESD-protection diodes to clamp transients on a high-speed bus, you risk burning them out. Because a burned-out diode fails in the open state, obliterating its clamping effect, the next ESD blast that roars through your system will likely cause permanent damage." http://www.sigcon.com/Pubs/edn/ProtectionForYour.htm I wonder if the FPGA vendors have any figures to plug into the equation given in the above article? That way, those engineers who ignore SI issues could predict when their designs will fail and prepare to get another job! Paul? Austin? Cheers, Syms.Article: 77553
kubik wrote:
>I'm a beginner in this field so forgive me if what seems interesting
>for me can seem stupid for others.
>I'm approaching the fpga field cause i' ve read many times that the
>fpga can reduce the time to market and reduce the costs of the system
>for low volume applications.
>
>
Compared with an ASIC, an FPGA has a shorter time to market provided you
have a competent designer. This doesn't necessarily hold true when
comparing it for an application that can run on a microprocessor.
>Surfing on the web i can find easily PC-104 platform for more or less
>100$ that have a 300MHz cpu clock etc etc.
>If i search for an fpga board with the same price i will never reach
>comparable performance, or quantity of hardware.
>
>
The FPGA cost is relative. A single FPGA can often take the place of
multiple high end DSP chips, in which case it quickly becomes cost
competitive. An FPGA rarely makes sense in applications that can be
handled by a single microprocessor. In order for the FPGA to shine, you
need an application that requires too much processing horsepower for a
single microprocessor to handle.
>So i would like to know which are the markets or the applications where
>an fpga can represent a real gain or be necessary.?
>
>
Video, digital radio, mil-aero applications, lower volume high
complexity apps like cellular basestations.
>Are there useful only for that application where the performance is
>not a goal?
>
>
No, quite the contrary. FPGAs are best in applications where
performance rules out microprocessors and economics rules out ASICs
>Are there useful only for research and prototyping?
>
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 77554The referenced article does not mention diode burn-out, but rather the failure of metal traces leading to the diode. Rest assured that Xilinx outputs and their metal traces can conduct and withstand (ad infinitum!) currents up to at least 12 mA, probably considerably higher. Now, if you intend to zap the pin with repeated capacitive discharges of 10,000 V backed by several 100 pF, that may be a different story. But I have not seen anything like that in real life. ESD damage occurs usually on the bare device, before it is soldered to a pc board. Peter Alfke, Xilinx ApplicationsArticle: 77555
I am designing an encryption algorithm using VHDL & targetting it to Stratix EP1S10F780C6.The problem is that post P&R simulation results are not correct.however when i target to Stratix EP1S10F780C5, i get the correct encrypted/decrypted output.How does the speed grade affect the post P&R output.The device i m using is the same.only spped grade is diffeterent.I am using Quartus synthesis tools for synthesising the code...pls helpArticle: 77556
Hi vlsi_learner, > I am designing an encryption algorithm using VHDL & targetting it to > Stratix EP1S10F780C6.The problem is that post P&R simulation results > are not correct.however when i target to Stratix EP1S10F780C5, i get > the correct encrypted/decrypted output.How does the speed grade affect > the post P&R output.The device i m using is the same.only spped grade > is diffeterent.I am using Quartus synthesis tools for synthesising the > code...pls help Have you looked at the timing report to see if there were no red lines in any of the timing specs? Rgds, BenArticle: 77557
hi Ben i have compared the timing reports for both the cases ie with Stratix EP1S10F780C6 & Stratix EP1S10F780C5.The resources etc used are all same except that the critical path delay is different for EP1S10F780C6 : critical path delay is 10.647 ns total cell delay is 4.956 ns total interconnect delay is 5.691 ns for EP1S10F780C5 : critical path delay is 9.468 ns total cell delay is 4.420 ns total interconnect delay is 5.048 ns wat should i do??? the results are correct for EP1S10F780C5..how should i reduce the critical path delay for stratix EP1S10F780C6 Ben Twijnstra wrote: > Hi vlsi_learner, > > > I am designing an encryption algorithm using VHDL & targetting it to > > Stratix EP1S10F780C6.The problem is that post P&R simulation results > > are not correct.however when i target to Stratix EP1S10F780C5, i get > > the correct encrypted/decrypted output.How does the speed grade affect > > the post P&R output.The device i m using is the same.only spped grade > > is diffeterent.I am using Quartus synthesis tools for synthesising the > > code...pls help > > Have you looked at the timing report to see if there were no red lines in > any of the timing specs? > > Rgds, > > > BenArticle: 77558
I thought the ply about the experiance of being surrounded by talent was interesting I spent some time working in Cambridge in England which is the famous university town and prolly the cloest to sillicon valley we have in England and it does attract a lot of very talented people my experience of working with the 'talented' people that you find there is that I have never met a more highly fucked up sociopathic bunch of social misfits and boader line autistic personalities in my life. So I would say if you value your mental health,your integrity and your dignity then stay away from anywhere which attracts lots of talented programmers/designers in one place.Article: 77559
Hi I saw the post on this group for editing a spartan-2 bitstream. I was looking into a way of changing the frequency multiplier and divider values of a DCM while downloading the bitstream (to support variable sampling rate for my application). As I understand those values cannot be changed after loading the bit stream. Has anybody done something like that ? SumitArticle: 77560
Hi, all: Implementing a UART(asic core) into XILINX Virtex2 3000-5. Due to 99% slices is used (2 slices is unused), the skew of the gated clock in UART is a little large (2-3 ns). On debuging, the UART is work well on some boards, however, occur error on other boards. And when I add a skew constraint to limit the skew below 1ns, all boards is ok. I hope to know, does par tools do setup / hold check with skew analyse. My current mapping tools is ISE5.2.03. regards, seyiorArticle: 77561
Can I use JTAG pins as a user I/O on an Altera Stratix Device ? MatteoArticle: 77562
Hello
Currently I am implementing my own IP which I wanna add to the FSL of the
Microblaze soft processor. But unfortunately I have problems with the RAM I
programmed. Although it is fully synthesizeable it doesnt work the way I
want it to on the FPGA. In the simulation it looks good to me, so probably
there is some syntax I use which causes problems on the FPGA. Here is the
VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------
-- START: Memory
-------------------------------------------------------------------
entity memory is
generic (width : integer);
port (clk : in std_ulogic;
rst : in std_ulogic;
data_in : in std_ulogic_vector(31 downto 0);
wr_addr: in std_ulogic_vector(7 downto 0);
wr : in std_ulogic;
rd1_addr :in std_ulogic_vector(7 downto 0);
rd1 : in std_ulogic;
data1_out:out std_ulogic_vector(31 downto 0)
);
end memory;
architecture rtl of memory is
type reg_type is array (0 to 3) of std_ulogic_vector(31 downto 0);
signal reg_file : reg_type;
begin
write : process(clk,rst,data_in,wr_addr,wr)
variable x_int : integer;
begin
if rst = '1' then
reg_file(0) <= (others => '0');
reg_file(1) <= (others => '0');
reg_file(2) <= (others => '0');
reg_file(3) <= (others => '0');
x_int:=0;
else
if clk'event and clk = '1' then
x_int:=to_integer(unsigned(wr_addr));
if wr = '1' then
reg_file(x_int) <= data_in;
end if;
end if;
end if;
end process;
read1 : process(clk,rst,rd1_addr,rd1)
variable x_int : integer;
begin
if rst = '1' then
data1_out <= (others => '0');
else
if clk'event and clk = '1' then
x_int:=to_integer(unsigned(rd1_addr));
if rd1 = '1' then
data1_out <= reg_file(x_int);
end if;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------
-- END: Memory
-------------------------------------------------------------------
I use the Xilinx ML300 Board as FPGA, would be very thankful if somebody
could point out the problem!
Philipp
Article: 77563Hello, I am using a PCMCIA software core in a design of mine. But i am not sure if i need a transreciever for it. Thanks and regards PraveenArticle: 77564
Nicolas, Make the Fast Output Register assignment to lberr_b_out (the data output register) instead of lberr_b (the output IOC). I just tried this in Quartus version 4.2 on a sample design, and it worked fine. Making a Fast Output Register assignment to pad tells Quartus to pack both the data & OE registers feeding the IO into the IO cell. Making the assignment to the data output register instead says that's the register you want packed in the IO cell, which is useful in this case since Quartus can't pack both the OE & data registers in the IO cell for the FLEX 10K. Regards, Vaughn Altera [v b e t z (at) altera.com] Make a fast output register assignment to the "Nicolas Matringe" <matringe.nicolas@numeri-cable.fr> wrote in message news:1105000023.498384@teheran.magic.fr... > Vaughn Betz a écrit : > > Hi Nicolas, > > > > The FLEX 10K family only has one register in each IO cell. That means that > > with a bidirectional IO like you have, where both the dataout signal and the > > OE signal come from registers, only one register can be implemented in the > > IO cell itself. This won't affect functionality, but will increase your Tco > > for whatever signal doesn't go into the IO cell. > > Yes, I know all this (already got stung by this single IO register that > did not show in the datasheet 6 years ago) > What I don't understand is why Quartus refuses to put the output > register in the IO when I ask it to do so (and put the input & tristate > regs somewhere else) > > > > Stratix, Cyclone & beyond all have more registers in the IO cell, so you > > won't run into this issue with them. > > I'm stuck with a Flex10K on this project > > > -- > ____ _ __ ___ > | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - > | | | | | (_| |_| | Invalid return address: remove the - > |_| |_|_|\__|\___/Article: 77565
Hi Torsten, There is an explanation of how Quartus names registers in the Quartus II handbook chapter on Quartus Integrated Synthesis: http://www.altera.com/literature/hb/qts/qts_qii51008.pdf , starting on page 7-46. Quartus does not use the process block name in naming registers, since many registers may be inferred in a single process block. So the register you're creating won't be named REG_A. The 'keep' attribute is not needed to preserve register names. That attribute is used to make sure a combinational node you want to observe exists (isn't optimized away or folded into other logic) in the implemented design. The 'preserve' attribute is used to make sure registers that are duplicates, stuck at logic 1 or 0, or otherwise are unnecessary are kept in the design. However, you shouldn't need to use that attribute either, since presumably this register is not redundant. If you post a more complete code fragment, we can probably give you some more guidance as to what your register will be named. i~0 is probably a combinational node name, since those are more difficult to keep good names for than registes. Regards, Vaughn Altera [v b e t z (at) altera.com] "Torsten Alt" <talt@kip.uni-heidelberg.de> wrote in message news:crh6kk$acv$1@news.urz.uni-heidelberg.de... > Hei, > > using the Quartus SignalTap Node finder i encountered the following > problem. When i use a graphical designfile (*.bdf) and i name the > instance of a register, i.e. reg_A, then i can search for this name in > the SignalTab nodefinder. When i do the same with a VHDL file and i name > the register, i.e. REG_A : process(clk), then the nodefinder doesn't > find the name. Instead i see something like i~0 since the name was not > preserved during synthesis. So i tried to preserve the name by using the > "keep" attribute for the registered signal as it is described in an > older thread. But this generates an additional logic cell and changes my > design. > > Is there any way to keep the name of an instance/register in a vhdl file > without generating additional logic cells? > > Cheers, > TorstenArticle: 77566
I'm simulating a design where a number of external signals is asynchronous in respect to the main FPGA clock. The device targeted is Virtex2 and I'm using ISE and Modelsim XE. During timing simulation, asynchronous signals often cause setup/hold time violations when synchronized to the main clock. I know about ASYNC_REG constraint that makes that no 'X' propagates through the desing when timing violation happens. However the timing violations are still reported in Modelsim, and because there are many of them it is difficult to spot the messages that may be really important. Is there any way to switch off reporting setup/hold timing warnings for a particular flip/flop? Any other ideas? -- Regards RobertP.Article: 77567
Hi vlsi_learner,
Quartus II 4.1 and newer versions of Software has an application
called Timing Optimization Advisor under the Tools menu. First compile the
design and then click on Tools->Timing Optimization Advisor. On the left
panel of the advisor, you will find a list of recommendations that can be
used for optimizing timing, based on the type of timing requirements and
second based on the order in which you should try these recommendations.
If you go the top of the Timing Optimization Advisor Left panel and click on
the Timing Summary you should see a summary of your timing report. The
detailed Timing report is available in the compilation report window.
Hope this helps.
- Subroto Datta
Altera Corp.
"vlsi_learner" <bajajk@gmail.com> wrote in message
news:1105428506.583848.218950@f14g2000cwb.googlegroups.com...
> hi Ben
>
> i have compared the timing reports for both the cases ie with Stratix
> EP1S10F780C6 & Stratix EP1S10F780C5.The resources etc used are all same
> except that the critical path delay is different
>
> for EP1S10F780C6 : critical path delay is 10.647 ns
> total cell delay is 4.956 ns
> total interconnect delay is 5.691 ns
>
> for EP1S10F780C5 : critical path delay is 9.468 ns
> total cell delay is 4.420 ns
> total interconnect delay is 5.048 ns
>
> wat should i do??? the results are correct for EP1S10F780C5..how should
> i reduce the critical path delay for stratix EP1S10F780C6
> Ben Twijnstra wrote:
>> Hi vlsi_learner,
>>
......
>> Have you looked at the timing report to see if there were no red
> lines in
>> any of the timing specs?
>>
>> Rgds,
>>
>>
>> Ben
>
Article: 77568
RobertP wrote:
> I'm simulating a design where a number of external signals is
> asynchronous in respect to the main FPGA clock.
> Is there any way to switch off reporting setup/hold timing warnings for
> a particular flip/flop? Any other ideas?
Consider pre-synchronizing the testbench stimulus
for the purposes of a functional simulation.
-- Mike Treseler
Article: 77569Symon, We design for extreme electromigration, as we have no clue what our customers will do to (with) our parts. They are designed for in excess of 60 mA. Now that doesn't mean you can go and use the clamp at that level, but we do not see any EM failures in ten years of accelerated tested. On the other hand, ASIC IO cells (and 'hardened' logic versions) are as small (cheap), and fast as possible, and I have been told that they can (easily) be blown out by abuse. Austin Peter Alfke wrote: > The referenced article does not mention diode burn-out, but rather the > failure of metal traces leading to the diode. > Rest assured that Xilinx outputs and their metal traces can conduct and > withstand (ad infinitum!) currents up to at least 12 mA, probably > considerably higher. > Now, if you intend to zap the pin with repeated capacitive discharges > of 10,000 V backed by several 100 pF, that may be a different story. > But I have not seen anything like that in real life. > ESD damage occurs usually on the bare device, before it is soldered to > a pc board. > > Peter Alfke, Xilinx Applications >Article: 77570
Sumit, We do it all the time here in the lab(for testing). You have to find the M and D values (just do a diff on two bistreams where that is the only change), and then disable the CRC check (in bitgen). In V4 we have the dynamic reconfiguration port (DRP - an 8 bit uP like interface port to talk to the DCM config bits) for the DCM which allows changes while operating. RESET must be asserted in order to re-lock however. Austin do_not_reply_to_this_addr@yahoo.com wrote: > Hi > > I saw the post on this group for editing a spartan-2 bitstream. I was > looking into a way of changing the frequency multiplier and divider > values of a DCM while downloading the bitstream (to support variable > sampling rate for my application). As I understand those values cannot > be changed after loading the bit stream. > Has anybody done something like that ? > > Sumit >Article: 77571
I've run into an issue with the Bitgen software and Vref pins. In a design with a fairly high impedance Vref generator it is important that the Vref pins are floated in order to maintain the desired voltage. I had a design where a national LP2995 termination voltage regulator had its Vref output pulled down almost to ground after configuration. I also noticed that it was being pulled up near 2.5V during configuration until I removed the pulldown resistor from the HSWAP_EN pin. In this design, one bank had no input pins, so although the I/O for the bank was all SSTL_II_DCI, the Vref pins for that bank became "unused IOBs." Unused IOBs are pulled down by default in Bitgen. It was necessary to configure bitgen to float unused IOBs and handle any really unused pads by driving them explicitly in the design. Other banks in the design worked correctly because they all contained a mix of inputs and outputs.Article: 77572
Hi Peter, "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1105415410.455687.153430@c13g2000cwb.googlegroups.com... > The referenced article does not mention diode burn-out, but rather the > failure of metal traces leading to the diode. Yes. > Rest assured that Xilinx outputs and their metal traces can conduct and > withstand (ad infinitum!) currents up to at least 12 mA, probably > considerably higher. The point I think the author was trying to make was that if someone used the diodes (and by definition the metal connections) to clamp a badly terminated high speed bus, the repeated clamp current, albeit brief but in excess of (say) 12mA, could cause a failure in time. Even though the average clamp current was far below the 12mA you mention. > Now, if you intend to zap the pin with repeated capacitive discharges > of 10,000 V backed by several 100 pF, that may be a different story. > But I have not seen anything like that in real life. > ESD damage occurs usually on the bare device, before it is soldered to > a pc board. Indeed, as I said, ESD is something different, and well understood. I was just curious about designs where the diodes are relied on to repeatedly clamp over/under shoots. The article implies that the diode/metal connections are there *only* to protect against a few ESD zaps in a lifetime, not repeated stress caused by bad bus design. Which is something I didn't know! Cheers, Syms. > > Peter Alfke, Xilinx Applications >Article: 77573
"Austin Lesea" <austin@xilinx.com> wrote in message news:cs0t8f$ibt1@cliff.xsj.xilinx.com... > Symon, > > We design for extreme electromigration, as we have no clue what our > customers will do to (with) our parts. > I bet you see a few horror stories! > They are designed for in excess of 60 mA. Now that doesn't mean you can > go and use the clamp at that level, but we do not see any EM failures in > ten years of accelerated tested. > > On the other hand, ASIC IO cells (and 'hardened' logic versions) are as > small (cheap), and fast as possible, and I have been told that they can > (easily) be blown out by abuse. > > Austin OK, sounds as though it's not a big deal for Xilinx parts then. Thanks for the reply, Syms.Article: 77574
Robert, I have named asynchronous flip-flops with a unique prefix that helps identify it as a flop where timing violations are expected. One could filter out references to this from a timing report to get a more concise report. Another. perhaps more drastic option is to find the async instances in the sdf file and change the setup and hold to "0.0". One has to be careful not to shoot oneself in the foot when doing these things. Newman "RobertP" <r_p_u_d_l_i_k@poczta.onet.pl> wrote in message news:cs0s4s$b8s$1@news.onet.pl... > > I'm simulating a design where a number of external signals is asynchronous > in respect to the main FPGA clock. > The device targeted is Virtex2 and I'm using ISE and Modelsim XE. > During timing simulation, asynchronous signals often cause setup/hold time > violations when synchronized to the main clock. I know about ASYNC_REG > constraint that makes that no 'X' propagates through the desing when > timing violation happens. However the timing violations are still reported > in Modelsim, and because there are many of them it is difficult to spot > the messages that may be really important. > Is there any way to switch off reporting setup/hold timing warnings for a > particular flip/flop? Any other ideas? > > > -- > Regards > RobertP. > > > > >
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