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Hi Seyior, Are you trolling? ;-) A cursory search back through this newsgroup with Google will show that 'gated clocks' are anathema to everyone here. DON'T DO IT! Cheers, Syms. <seyior> wrote in message news:ee8b070.-1@webx.sUN8CHnE... > Hi, all: > > Implementing a UART(asic core) into XILINX Virtex2 3000-5. Due to 99% slices is used (2 slices is unused), the skew of the gated clock in UART is a little large (2-3 ns). > > On debuging, the UART is work well on some boards, however, occur error on other boards. And when I add a skew constraint to limit the skew below 1ns, all boards is ok. > > I hope to know, does par tools do setup / hold check with skew analyse. My current mapping tools is ISE5.2.03. > > regards, seyiorArticle: 77576
Gabor, Do not use a high impedance reference generator. Austin Gabor wrote: > I've run into an issue with the Bitgen software and > Vref pins. In a design with a fairly high impedance > Vref generator it is important that the Vref pins > are floated in order to maintain the desired voltage. > > I had a design where a national LP2995 termination > voltage regulator had its Vref output pulled down > almost to ground after configuration. I also noticed > that it was being pulled up near 2.5V during configuration > until I removed the pulldown resistor from the HSWAP_EN > pin. > > In this design, one bank had no input pins, so although > the I/O for the bank was all SSTL_II_DCI, the Vref > pins for that bank became "unused IOBs." Unused IOBs > are pulled down by default in Bitgen. It was necessary > to configure bitgen to float unused IOBs and handle > any really unused pads by driving them explicitly in > the design. > > Other banks in the design worked correctly because they all > contained a mix of inputs and outputs. >Article: 77577
On Tue, 11 Jan 2005 08:49:30 -0800, Austin Lesea <austin@xilinx.com> wrote: >Do not use a high impedance reference generator. I'm getting awful confused.... 1) I don't understand what a "high impedance reference generator" is. I can just about understand what a "reference generator with limited output current" is, but a reference generator with high impedance output sounds to me about as useful as a chocolate teapot. Do we, or do we not, want a fixed voltage? 2) With that doubt in mind, I looked up the cited LP2995. Its quoted maximum output current is no less than 1.5 *amps* (not a typo; amps, not milliamps) on its Vtt output pin. 3) The Vtt output is quoted as having a rather high output impedance of 5k ohms. On closer inspection, though, we find that this is its slope resistance over the rather narrow crossover region where its Vtt output current is only a few microamps. Outside this crossover region, the output slope resistance appears to be in the milliohm region. Its regulation of Vtt remains excellent. So, chaps, just what is going on? Is Gabor mistakenly trying to use the Vref output of his LP2995 (which is feeble, and can source/sink hardly any current at all)? Or is Austin hiding from us the unpleasant fact that the reference pins need over an amp to keep them happy? (Only joking - I hope!) Or have I missed some important piece of hidden folklore? Gabor, are you trying to use Vref instead of Vtt from the LP2995? And if you're using Vtt, did you remember to tie the Vsense input to the same place? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 77578
Jonathon, All we need is the leakage (less than 10uA + or -) per Vref pin. But I agree that a high impedance Vref generator is not very useful (or desirable). Austin Jonathan Bromley wrote: > On Tue, 11 Jan 2005 08:49:30 -0800, > Austin Lesea <austin@xilinx.com> wrote: > > >>Do not use a high impedance reference generator. > > > I'm getting awful confused.... > > 1) I don't understand what a "high impedance reference > generator" is. I can just about understand what > a "reference generator with limited output current" > is, but a reference generator with high impedance > output sounds to me about as useful as a chocolate > teapot. Do we, or do we not, want a fixed voltage? > 2) With that doubt in mind, I looked up the cited > LP2995. Its quoted maximum output current is > no less than 1.5 *amps* (not a typo; amps, > not milliamps) on its Vtt output pin. > 3) The Vtt output is quoted as having a rather high > output impedance of 5k ohms. On closer inspection, > though, we find that this is its slope resistance > over the rather narrow crossover region where > its Vtt output current is only a few microamps. > Outside this crossover region, the output slope > resistance appears to be in the milliohm region. > Its regulation of Vtt remains excellent. > > So, chaps, just what is going on? Is Gabor mistakenly > trying to use the Vref output of his LP2995 (which is > feeble, and can source/sink hardly any current at all)? > Or is Austin hiding from us the unpleasant fact that > the reference pins need over an amp to keep them happy? > (Only joking - I hope!) Or have I missed some important > piece of hidden folklore? > > Gabor, are you trying to use Vref instead of Vtt from > the LP2995? And if you're using Vtt, did you remember > to tie the Vsense input to the same place?Article: 77579
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag news:crv421$79c$1@agate.berkeley.edu... > >Is there a practical reason to do so?? > >Cant think of such a reason. > > A researcher working on routing algorithms. > > A researcher looking to reroute designs to better handle partial > configuration. > > A researcher looking at how to deal with a large board of flawed FPGAs > (a'la the old HP system), especially with easypath parts testing the > LUT fully but not fully testing the interconnect. But this all is stuff done only by the Xilinx folks or people working close to Xilinx to improve the design flow tools (map/ p&R). And those guy for sure have much more detailed information (and tools) about FPGA connectivity. No normal mortal, ahhh user, does this kind of stuff, not even advanced users. But I wont stop anyone. Regards FalkArticle: 77580
In article <34ike7F4a19aaU1@individual.net>, Falk Brunner <Falk.Brunner@gmx.de> wrote: >But this all is stuff done only by the Xilinx folks or people working close >to Xilinx to improve the design flow tools (map/ p&R). And those guy for >sure have much more detailed information (and tools) about FPGA >connectivity. No normal mortal, ahhh user, does this kind of stuff, not >even advanced users. >But I wont stop anyone. Uh, you'd be suprised what a researcher would want to do. EG, one research bit I did loaded Xilinx designs after placement but before routing, ripped up all the registers, duplicated them for C-slowing, retimed, reinserted all the new registers, and wrote back out the placement. I could EASILY see an interesting research project which "meer mortal researchers" could attempt which would be take a bunch of easypath parts, map the actual defects, and route around defets albeit at a performance penalty. It might be interesting to see if you colud use this to build a multi-teraflop vector supercomputer on a decent budget. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 77581
Patrick, See comp.lang.vhdl for a recent critique of a very similar design. --- Mike TreselerArticle: 77582
Call for Papers ******************************** We're looking for existing or newly authored technical papers to supplement the streaming media sessions related to our FPGA content at www.demosondemand.com <http://demosondemand.com/dod/>. We will pay $12 USD each time a user downloads the paper. To respond, visit paper submissions section at www.demosondemand.com or respond via email with the title and an abstract of your paper. Sheila Carey Demos on Demand sheilacarey@demosondemand.com ********************************Article: 77583
Austin Lesea wrote: > Jonathon, > > All we need is the leakage (less than 10uA + or -) per Vref pin. > > But I agree that a high impedance Vref generator is not very useful (or > desirable). > High impedance is always relative to something. In this case I am using the Vref pin of the LP2995, which was designed to create a more stable reference voltage than the Vtt (termination) output. The Vtt is used to source and sink current from a lot of 50 ohm resistors and has a good deal of noise on it. The point I was making in the post is that the tools make assumptions about the use of Vref pins based on the IOBs used in that bank, and free them up if there are no inputs in the bank which require Vref. The default action of Bitgen is then to add pull-downs to every pin, so in my case I had 6 "weak" pull-downs going against my reference generator. If I had instead used a resistor divider for Vref, I may not have seen such a dramatic change in the reference voltage, however there would be some sag and therefore the reference voltage would no longer be centered in the signal swing. Removing the default pull-down of unused IOB's fixes this problem. > Austin > > Jonathan Bromley wrote: > > On Tue, 11 Jan 2005 08:49:30 -0800, > > Austin Lesea <austin@xilinx.com> wrote: > > > > > >>Do not use a high impedance reference generator. > > > > > > I'm getting awful confused.... > > > > 1) I don't understand what a "high impedance reference > > generator" is. I can just about understand what > > a "reference generator with limited output current" > > is, but a reference generator with high impedance > > output sounds to me about as useful as a chocolate > > teapot. Do we, or do we not, want a fixed voltage? > > 2) With that doubt in mind, I looked up the cited > > LP2995. Its quoted maximum output current is > > no less than 1.5 *amps* (not a typo; amps, > > not milliamps) on its Vtt output pin. > > 3) The Vtt output is quoted as having a rather high > > output impedance of 5k ohms. On closer inspection, > > though, we find that this is its slope resistance > > over the rather narrow crossover region where > > its Vtt output current is only a few microamps. > > Outside this crossover region, the output slope > > resistance appears to be in the milliohm region. > > Its regulation of Vtt remains excellent. > > > > So, chaps, just what is going on? Is Gabor mistakenly > > trying to use the Vref output of his LP2995 (which is > > feeble, and can source/sink hardly any current at all)? > > Or is Austin hiding from us the unpleasant fact that > > the reference pins need over an amp to keep them happy? > > (Only joking - I hope!) Or have I missed some important > > piece of hidden folklore? > > > > Gabor, are you trying to use Vref instead of Vtt from > > the LP2995? And if you're using Vtt, did you remember > > to tie the Vsense input to the same place?Article: 77584
teo_80 wrote: > Can I use JTAG pins as a user I/O on an Altera Stratix Device ? > > Matteo Hi Matteo, The Stratix JTAG pins are dedicated inputs. They have no other function than JTAG, as shown in the pin tables. (The pin tables are at http://www.altera.com/literature/lit-dp.jsp?category=Stratix ) Hope this helps, Subroto Datta Altera Corp.Article: 77585
Nicholas Weaver wrote: >> I could EASILY see an interesting research project which "meer mortal > researchers" could attempt which would be take a bunch of easypath > parts, map the actual defects, and route around defets albeit at a > performance penalty. Nick, as you know, there is no "bunch of EasyPath parts". By the nature of the beast, each and every one part is different. That makes your suggestion a formidably inefficient job... Peter AlfkeArticle: 77586
Gabor, Ahhh. Now I understand, unused pins in banks get tied if there are no Vref standards in the bank. Got it. Good point. AustinArticle: 77587
Hi vlsi_learner, > hi Ben > > i have compared the timing reports for both the cases ie with Stratix > EP1S10F780C6 & Stratix EP1S10F780C5.The resources etc used are all same > except that the critical path delay is different > > for EP1S10F780C6 : critical path delay is 10.647 ns > total cell delay is 4.956 ns > total interconnect delay is 5.691 ns > > for EP1S10F780C5 : critical path delay is 9.468 ns > total cell delay is 4.420 ns > total interconnect delay is 5.048 ns > > wat should i do??? the results are correct for EP1S10F780C5..how should > i reduce the critical path delay for stratix EP1S10F780C6 If your clock frequency is 100MHz, your clock period in 10ns. Ergo, the C6 is too slow, and the C5 meets timing. From what I gather from your story, you don't seem to have put any information regarding clock frequency into your Quartus project. This means that Quartus will compile the circuit, do a few P&R iterations, and then finishes, telling what it thought up as a possible solution. Once Quartus knows about your minimum clock frequency and, probably, the Tsu and Tco constraints (I usually set them to about 2/3 of the clock period if there are no special demands) it will try to meet these constraints and will telly if it hasn't been able to find a P&R solution that met your requirements. If you have indeed not entered any clock frequency constraints in your project, you can do so by clicking "Assignments" on the menu bar and selecting "Timing Wizard". Just follow the instructions. Another solution I have seen, but definitely not one for production environments, is to apply a healthy dose of cold spray to the FPGA if the circuit doesn't violate timing constraints too badly. The lower temperature will make circuit timing faster. As stated, good for experimenting and testing your algorithm, but not for an end product, unless of course you want to ship your crypto processor with a lifetime supply of cold spray ;-) Best regards, BenArticle: 77588
Hi there. I've built a VGA controller, and want to interface it to a chunk of RAM now. Unfortunately, I'm a bit new at cpld and electronics in general, so yeah, I need some advice. The device I'm using doesn't have any on board ram. Searching about my house, I found some DRAM chips. Am I right in thinking that DRAM has to be refreshed every so often? Is this hard to do? How do I do it? Are there easier ways (sram?) that I may have chips to do lying around? And am I right in thinking that to access a bit, I put an 'x co-ord' on the address bus, take RAS low for a bit, return it to high, then do the same for CAS? Will it just spit data back at me there? Sorry bout all the questions...*grins* Thanks. -AlanArticle: 77589
Alan Randomdude wrote: > I've built a VGA controller, and want to interface it to a chunk of > RAM now. Unfortunately, I'm a bit new at cpld and electronics in > general, so yeah, I need some advice. > The device I'm using doesn't have any on board ram. Searching about my > house, I found some DRAM chips. Am I right in thinking that DRAM has > to be refreshed every so often? Is this hard to do? How do I do it? > Are there easier ways (sram?) that I may have chips to do lying > around? Usually DRAM used for video buffers is accessed enough that it doesn't need any refresh cycles. Otherwise, SRAM is probably easier. -- glenArticle: 77590
Hi All, I am programming XCR3032XL CPLD with Xilinx Parallel Cable IV(PC4). Is it possible for me to use 3.3V as power supply for both PC4/DLC7 and XCR3032XL? Any success story? Since Xilinx Guide says PC4 can automatically adjusts to operating voltages from 1.5 to 5V, and this can save my design time. But when I downloaded the code iMPACT gave me an Error 585. Appreciate for any advice. -ZimmerArticle: 77591
thank you Sylvain mentioning the IC number. i would have definitely burnt my spartan3 if i wouldnt think about this. now i can only hope that it is available in the markets nearby (TI is not sampling that one directly). thanks anyway for the help. regards, Shreyas KulkarniArticle: 77592
"FPGA_com" <wojtek@alatek.com.pl> wrote in message news:crtda7$2o4$1@korweta.task.gda.pl... > HI > You should divide 300MHZ to 75 MHZ and try synchronise this clock domains. > For devider use simple counter , it should works. > WZ I'm not sure what you are saying. My 300 MHz clock is in fact divided by four in the PLL loop, but I'm not sure how this helps in synchronizing signals between the two clock domains. One of my concerns is if the jitter between my two clocks minus the propergation delay of a flip flop is greater than the setup time of a flip flop. In this case, if I have two flip flops in series where each flip flop is triggered by a seperate clock, I will lose a bit of data, and incorrect data will be latched (hopefully that is clear). In any case, this seems a common enough problem that there might be some tried methods for dealing with it; any ideas? Thanks, Michael. > Użytkownik "Michael Chan" <mchan@itee.uq.edu.au> napisał w wiadomości > news:newscache$xab3ai$oml$1@lbox.itee.uq.edu.au... >> Hi all, my question is not really related to FPGAs (so let me know if > there >> is a more appropriate forum), but I think it is of some relevance. >> >> Anyway, I have a design that contains a 75 MHz clock, and a PLL that >> multiplies it up to 300 MHz. These two clocks will be in sync except for >> the jitter the PLL introduces. Also, the 75 MHz clock is FM modulated to >> spread its power spectrum out, but the PLL should track this. I'm > wondering >> about the best way to synchronise signals between the two clock domains; >> I >> have two state machines that need to do a small amount of communication. > I >> could simply place some flip flops to sync the signals, but I get the >> feeling that the chance of metastability will be much higher, since the > two >> clock domains are related by the PLL. Is there any particular method >> that >> works well in this situation? >> >> Thanks in advance, >> >> Michael Chan. >> >> > >Article: 77593
I suppose your two frequencies (75 and 300 MHz) are rising-edge aligned. If you run your 300-MHz logic off the falling clock edge, then you have half a period of 300 MHz = 1.5 ns of protection. But you have also lost that much time for the interface, so this works only if the clock-straddling interface is very fast. The previous posting suggested you start with 300 MHz, and derive 75 MHz from it. My suggestion would then be to run everything off the 300 MHz clock, and use CE to achieve 75 MHz operation. Your modulation makesthe whole thing more complex... Peter AlfkeArticle: 77594
Michael Chan wrote: > Anyway, I have a design that contains a 75 MHz clock, and a PLL that > multiplies it up to 300 MHz. These two clocks will be in sync except for > the jitter the PLL introduces. Also, the 75 MHz clock is FM modulated to > spread its power spectrum out, but the PLL should track this. I'm wondering > about the best way to synchronise signals between the two clock domains; I > have two state machines that need to do a small amount of communication. I > could simply place some flip flops to sync the signals, but I get the > feeling that the chance of metastability will be much higher, since the two > clock domains are related by the PLL. Is there any particular method that > works well in this situation? I don't know about your design, but my favorite is to invert one, which keeps their rising edge about a half cycle of the fast clock apart. Then latch them at the boundary, so you have the full clock cycle available. More than metastability is the possibility that some signals will be latched before and some after a clock edge. That is the reason to use gray code when FIFO pointers cross a clock domain. -- glenArticle: 77595
It might be better to use one of the fpga's which have built in sram and save yourself a lot of problems.A full dram interface is quite complex and sdram interface is a major design.Article: 77596
Hello, I'm trying to use Quartus II to functionally simulate my code. I have a VHDL test bench *.vht file. How do I convert it to a *.vwf file so Quartus will allow me to simulate it? Or is there a setting that I need to adjust to get the vht file to work. Thanks, EricArticle: 77597
"Peter Alfke" <peter@xilinx.com> wrote in message news:1105494032.880651.53830@z14g2000cwz.googlegroups.com... >I suppose your two frequencies (75 and 300 MHz) are rising-edge > aligned. If you run your 300-MHz logic off the falling clock edge, then > you have half a period of 300 MHz = 1.5 ns of protection. But you have > also lost that much time for the interface, so this works only if the > clock-straddling interface is very fast. > I guess this is the obvious choice; I'll just have to be careful. > The previous posting suggested you start with 300 MHz, and derive 75 > MHz from it. > My suggestion would then be to run everything off the 300 MHz clock, > and use CE to achieve 75 MHz operation. My original design had everything running off of 300 MHz, but the PLL is disabled in slumber mode, so this clock is not always available(something which I found out about after I had finished *sigh* ). Michael. > Your modulation makesthe whole thing more complex... > Peter Alfke >Article: 77598
I am trying to find the state register which is called state in my code, but of course it can not be found with the node finder. Does anyone have any suggestions on how to find the signals using the RTL viewer, equations, *.map.rpt, or *.fit.rpt. My code is written in VHDL and I am using Quartus II 4.1. I am doing synthisis in Quartus II. Thanks in Advance, DougArticle: 77599
well if you look thru history you will find the greatest physicists have always been the strangest of people... so strange as to wonder what sub-species they are. "Jezwold" <edad3000@yahoo.co.uk> wrote in message news:1105430167.127775.14100@f14g2000cwb.googlegroups.com... > I thought the ply about the experiance of being surrounded by talent > was interesting I spent some time working in Cambridge in England which > is the famous university town and prolly the cloest to sillicon valley > we have in England and it does attract a lot of very talented people > my experience of working with the 'talented' people that you find there > is that I have never met a more highly fucked up sociopathic bunch of > social misfits and boader line autistic personalities in my life. > So I would say if you value your mental health,your integrity and your > dignity then stay away from anywhere which attracts lots of talented > programmers/designers in one place. >
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