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Kolja Sulimma wrote: > Xilinx also has an patent on implementing an 8-input AND in a single > CLB. Hopefully your Microblaze clone does not use this feature, they > could use that patent to come after you. (Peter Alfke stated in this > newgroup that they wouldn't) I guess here you mixed me with Antti Lukats. However, I come from the other side of the gulf, and I'm just beginning to learn the secrets of EE. >> I.e. is a Verilog or VHDL-source file just >> "a description for hardware device" >> or is it yet another (strange) form of software? > > The VHDL source is not patentable. It is covered by copyright. That is > something entirely different and completely unrelated. Yes, of course. However, what I was striving after here was that what happens if the public (and EPO) opinion at some point comes to view the writing of Verilog/VHDL-modules as a creation of SOFTWARE (for these "massively parallel reconfigurable processing chips", i.e. FPGAs), instead of viewing it as a description of HARDWARE? This view might come more prevalent if the FPGA's will be getting more and ASIC's less common, and if the data processing/computing applications will prevail over more traditional EE-fields. For an example, see also John Jakson's view here: http://groups-beta.google.com/group/comp.sys.transputer/browse_thread/thread/73ab172632c442f0/ec98764623671324#ec98764623671324 "I am pushing the idea that FPGAs are in fact Transputer cousins at a much finer level of granularity ..." Yours, Antti KarttunenArticle: 77326
Antti Karttunen (remove .fo from the address) wrote: (snip, someone wrote) >>> I.e. is a Verilog or VHDL-source file just >>> "a description for hardware device" >>> or is it yet another (strange) form of software? >> The VHDL source is not patentable. It is covered by copyright. That is >> something entirely different and completely unrelated. > Yes, of course. However, what I was striving after here > was that what happens if the public (and EPO) opinion > at some point comes to view the writing of Verilog/VHDL-modules > as a creation of SOFTWARE (for these "massively parallel > reconfigurable processing chips", i.e. FPGAs), > instead of viewing it as a description of HARDWARE? If you can argue that there is a continuum between hardware (wired up TTL chips), through ASICs to FPGAs to compiled C code in RAM, then you would have to say that software can be patentable. Where is the line between what is patentable and what isn't? If I remember the story from the IBM S/370 and virtual storage, it was that the algorithm (logical structure of virtual memory) wasn't patentable, but the hardware implementing it was. Now, most, if not all, S/370 were microcoded, so wouldn't that be software? The distinction is not easy at all. -- glen -- glenArticle: 77327
Kolja Sulimma <news@sulimma.de> writes: > There are low cost LDOs that are much better than the LM317. > Most notably less voltage drop. Keep in mind that you need to get rid > of all the heat that comes with a large voltage drop. Since the input to the 1.2V regulator is going to be 5.0V, I don't really need an LDO. I prefer to use a non-LDO regulator when possible, but in this case maybe I'll really need the LDO because I'm concerned about 1.2V being exactly the minimum specified output voltage for the LM317S. I wanted to use a regulator available in a TO263 package (surface mount equivalent of TO220) for good heat-sinking. The only 1.2V fixed linear regulator in that (or any similar) package I found was the very expensive LP3881ES-1.2. > Also note that you can use an LDO with 1.25V reference voltage (for > example the lm1086) without any ressitors to power a spartan-3. Thanks for calling that one to my attention, but I don't think I can use it. The tolerance and the line and load regulation performance could easily result in exceeeding the 1.26V maximium operating spec for Vccint. The LM1086-ADJ adjustable version regulates to keep the feedback at 1.25V, so that wouldn't be any better. Thanks! EricArticle: 77328
Eric Smith wrote: > Kolja Sulimma <news@sulimma.de> writes: > >>There are low cost LDOs that are much better than the LM317. >>Most notably less voltage drop. Keep in mind that you need to get rid >>of all the heat that comes with a large voltage drop. > > > Since the input to the 1.2V regulator is going to be 5.0V, I don't > really need an LDO. OK, I assumed that you can influence the input voltage of the regulator. I prefer to use a non-LDO regulator when possible, > but in this case maybe I'll really need the LDO because I'm concerned > about 1.2V being exactly the minimum specified output voltage for the > LM317S. That should not be a problem. You do not even need the resistors. > I wanted to use a regulator available in a TO263 package (surface mount > equivalent of TO220) for good heat-sinking. If you generate 3.3V for your I/Os you can generate the 1.2V from the 3.3V to spread the among to packages. You can also put one or two high current diodes in series with the ldo to burn heat. > The only 1.2V fixed linear > regulator in that (or any similar) package I found was the very > expensive LP3881ES-1.2. For that price you should use a switching regulator. No heat problems there. >>Also note that you can use an LDO with 1.25V reference voltage (for >>example the lm1086) without any ressitors to power a spartan-3. > > > Thanks for calling that one to my attention, but I don't think I can use > it. The tolerance and the line and load regulation performance could > easily result in exceeeding the 1.26V maximium operating spec for > Vccint. > The LM1086-ADJ adjustable version regulates to keep the feedback at > 1.25V, so that wouldn't be any better. Actually that's what I ment. According to Austin you will only experience a minar degradation in device lifetime if you exceed the spec by a few tens of mVs. Kolja SulimmaArticle: 77329
Antti Karttunen (remove .fo from the address) wrote: > Kolja Sulimma wrote: > >> Xilinx also has an patent on implementing an 8-input AND in a single >> CLB. Hopefully your Microblaze clone does not use this feature, they >> could use that patent to come after you. (Peter Alfke stated in this >> newgroup that they wouldn't) > > I guess here you mixed me with Antti Lukats. However, I > come from the other side of the gulf, and I'm just beginning > to learn the secrets of EE. I did. My apologies. >>> I.e. is a Verilog or VHDL-source file just >>> "a description for hardware device" >>> or is it yet another (strange) form of software? > > Yes, of course. However, what I was striving after here > was that what happens if the public (and EPO) opinion > at some point comes to view the writing of Verilog/VHDL-modules > as a creation of SOFTWARE (for these "massively parallel > reconfigurable processing chips", i.e. FPGAs), > instead of viewing it as a description of HARDWARE? > This view might come more prevalent if the FPGA's > will be getting more and ASIC's less common, > and if the data processing/computing applications > will prevail over more traditional EE-fields. Actually that is the trick (the other way around) that is currently used in the EU to file software patents. You do not patent an algorithm, but the "idea" to run the algorithm on a processor, claiming that the combination of algorithm an CPU is a device, the algorithm beeing the configuration of the hardware. But that really is against the words and the meaning of the law. The idea to run Bresenhams algorithm on a CPU is not a technical invention. If it is, it is so similar to running Quicksort on a CPU that the level of innovation is not high enough for a patent. But of course you have a big grey area. Because it is hard to distinguish a new multiplier architecture from a new multiplication algorithm. And the barrier of where patents get absurd might indeed move more towards hardware. If you look at the discussion about software patents, the core argument is, that software is relative easy to develop, and as a result, software projects tend to get huge and incorporate thousands of patentable ideas (or combination of ideas). To check whether a software project violates any patents therefore becomes impossible and software development becomes a gamble. To check an RF receiver or a new chemical for patent violation on the other hand is relatively easy. With large FPGA projects with ever improving high level synthesis the situation begins to look very similar to the process of software development. I believe that the australien view that the patent system in general is not beneficial for society is right. Kolja SulimmaArticle: 77330
There were times when the internet, and usenet in particular, was used mainly be an academic elite. You could expect most people you meet there to be reasonably smart and cautious. Today with hundreds of millions of internet users we will encounter more and more people who are less polite, more greedy, or just plain stupid. If we let ourself get annoyed to much by these we only hurt ourself because the useful posts get less. Try too keep up a high spirit despite of the annoyances and ignore them. The other alternative would be a more closed community. Either moderated or with membership levels. I do not believe that would work out to well. Kolja Sulimm Peter Alfke wrote: > I find it amazing and disturbing that people have the audacity to ask > for help and favors from this newsgroup, without giving their name, > their affiliation, or at least the reason for their question. > > How would you react if somebody you had never seen before just barged > into your home or office and asked for a favor, without introducing > himself or explaining the reason for his question ? > > Many of us love to help and explain, but I do not like to be taken > advantage of in a totally impersonal way... > Are newsgroups fostering the death of civility ? > Peter Alfke >Article: 77331
Antti Karttunen (remove .fo from the address) wrote: > For an example, see also John Jakson's view here: > http://groups-beta.google.com/group/comp.sys.transputer/browse_thread/thread/73ab172632c442f0/ec98764623671324#ec98764623671324 > > "I am pushing the idea that FPGAs are in fact > Transputer cousins at a much finer level of granularity ..." Also see Andre DeHons PhD Thesis on an approach to fit CPUs, FPGAs and a couple of other archtiectures in a single framework. http://www.cs.caltech.edu/~andre/abstracts/dehon_phd.html Kolja SulimmaArticle: 77332
Kolja Sulimma wrote: (snip on patents and software) > But that really is against the words and the meaning of the law. > The idea to run Bresenhams algorithm on a CPU is not a technical > invention. If it is, it is so similar to running Quicksort on a CPU that > the level of innovation is not high enough for a patent. OK, but say you use Bresenhams algorithm to run the stepper motor on a plotter, implemented in TTL. Would you consider that hardware enough to patent? Consider that it could still be coded in verilog. I think you have the right idea, though. The level of innovation, either software or hardware, should be the deciding point, not the method of implementation. > But of course you have a big grey area. Because it is hard to > distinguish a new multiplier architecture from a new multiplication > algorithm. And the barrier of where patents get absurd might indeed move > more towards hardware. Not to mention the problems with patenting genes, DNA or protein sequences, especially when their function is not known. -- glenArticle: 77333
> > If someone cares to do something... > > > The AT91SAM7S64 is nice for the job. > > * USB Client > > * ARM7 running at 48 MHz (will not handle 70'C at this temp though) > > * Built in Flash and SRAM > > * High speed synch interface for JTAG Master > > > This should be MUCH MUCH fatser than bitbanging. > > There is of course the small matter of programming... > > Looks nice, but: > - Digi has no chips on stock, and the other usual suspects don't have that > chips at all... > > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- They are not in production yet. A new rev comes this month, which will add some nice functionality I cannot really talk about just yet. Order 5 samples free of charege directly from Atmel or disti. There are many companies working with the part at the moment. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This is a personal view which may or may not be share by my Employer Atmel Nordic ABArticle: 77334
Hi everyone, I am trying to design an interface between an XScale PXA255 CPU and an Altera FPGA - we have a working SRAM-like asynchronous interface, but would like to make it synchronous for improved performance and lower latency. I have been considering making the FPGA look like an SDRAM device and using the CPU's internal SDRAM controller to interface, but due to some issues with bust mode and so on, that approach could result in even higher latencies and lower throughput that the SRAM-like interface. Has anyone solved this problem before or know of a suitable way to do it? Kind regards, Hugo Vincent, Bluewater Systems (www.bluewatersys.com)Article: 77335
nospam,
> Another post from a truly prolific information leech bought to you by
> Google.
Prolific. Perhaps.
A leech? I don't agree with this. I don't consider those
who post their code and sometimes their simulation results
when they ask a question to be leech.
Of course you are entitled to your own opinion and can
always create a filter to remove the person from your
viewing consideration.
If you consider the exact issue in this case. The
solution required the full use of the wait statement
(Jonathan Bromley's second solution):
for i in 0 to 4 loop
wait until (order_burst_data = '1') or rising_edge(clock);
exit when order_burst_data_in='1';
end loop;
I think the author (AluPin) put enough consideration and
the solution was difficult enough that I feel your
comment is unjustified.
Regards,
Jim Lewis
P.S.
It would be polite and civil if both of you would
put a by-line with your real name.
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 77336> why JTAG??? For configuring CCLK, DATA and Done are all You need. > - no special knowledge about JTAG (just a Xilinx/Altera/Xxx data sheet) > - no special knowledge about USB and OS (comes from FTDI) > > If debug or CPLD´s come into discussion things may be different.... > You do not need to run a special programming application with the ARM based solution. From your application that generates a bitstream, you define the location of the saved file to be on the flash disk. Lose one step in the development process = faster turnaround time. The FTDI solution is faster and easier to implement, but this is much nicer... I think that the configuration of the FPGA will be much faster as well. > -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This is a personal view which may or may not be share by my Employer Atmel Nordic ABArticle: 77337
hi i want to be familiarized with microblaze usage with ML310 board. Someone can tell me which documents (tutorial, or user guide, etc) will be best to follow up and be familiarized with it.... Thankyou in advanceArticle: 77338
For a real simple tutorial, try http://www.fpga-games.com/edktst.htm This is for ISE 6.3i Service Pack 3, with EDK 6.3i Service Pack 1. It's for a different board, but as long as you are using a board that is supported by the Base System Builder, and you've got an RS232 port and some LEDs, it should behave the same. EricArticle: 77339
Hi R!SC wrote: > i have buy a development board spartan-3 fga based. > http://www.silica.com/en/products/evaluationkits/SP3%20Development%20kit.html > > i heve read from a little time the LEON2 CORE. I have a question: > > Which thing you me councils for this board? uclinux on microblaze or LEON2 > on uclinux? You will achieve a much higher max clock freq with microblaze than LEON2, because Microblaze is specifically tuned for the Xilinx parts (and other reasons). Regards, JohnArticle: 77340
I'm glad that Google now has free web-based
newsgroup service with reasonably quick posting.
At work, I no longer have access to a real news server.
As for the original posting, it was a good,
on-topic question that provoked an illuminating
posting from Mr Bromley. This group is hardly overloaded
with questions in any case.
-- Mike Treseler
Article: 77341I wrote: > The only 1.2V fixed linear regulator in that (or any similar) package > I found was the very expensive LP3881ES-1.2. Kolja Sulimma wrote: > For that price you should use a switching regulator. No heat problems there. True. I was just trying for simple and cheap. The LM317S looks to be cheaper than any switcher I could reasonably use. Kolja Sulimma wrote: > Actually that's what I ment. According to Austin you will only > experience a minar degradation in device lifetime if you exceed the > spec by a few tens of mVs. On closer study of the LM1086 LDO you recommended, I see that there isn't a 1.2V fixed version, and you were most likely suggesting using the adjustable version as a fixed. The spec range of the reference voltage is 1.225 to 1.270V. Taking 0.2% line and 0.4% load regulation into account, the expeced output range is 1.218 to 1.278V. That's below the absolute max rating of 1.32V, so I'm not too worried about damage to the part, but I'd definitely prefer to stay within the recommended operating conditions of 1.140 to 1.260V since the part isn't guaranteed to meet the other specs outside that range. If I was building a one-off prototype, I wouldn't worry about it. As it turns out, the LM317S won't meet the spec either. The first page of the data sheet says that it is suitable for output voltages down to 1.2V, but the actual reference voltage spec has a range of 1.20 to 1.30V with a typical of 1.25V. I'll either use the LP3881ES-1.2 or a switcher, possibly the Linear Tech LTC3406BES5-1.2. The specs of the LP3881 are quite impressive; I suppose I can see why National is so proud of it. Thanks again for the advice.Article: 77342
Jim Lewis <Jim@SynthWorks.com> wrote: >nospam, > > Another post from a truly prolific information leech bought to you by > > Google. >Prolific. Perhaps. > >A leech? I don't agree with this. I don't consider those >who post their code and sometimes their simulation results >when they ask a question to be leech. If you care to check the OPs posting history on Google you will find 10 pages of posts. If you inspect them you will find perhaps two or three posts to threads which the OP did not originate with a question. These are the first line of each post in the first page Hello, does someone know Hi @ all, is it possible to Some additional question: 3.what is the advantages and disadvantages of Some additional thing: "Differential" is the wrong expression. I need LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; Hi, is the following CAM-implementation synthezisable? hi how do i detect a state change of a signal Hi, I have a question Hi everybody, How can I put Notice a pattern? Information leech seems an appropriate term for someone who asks but never answers questions. My recent observation is that it is an appropriate term for the majority of people accessing technical groups via google. Google users seem to regard usenet as a free consultancy service and as long as there are enough suckers who bother to read and contribute to their threads it will work for them. >Of course you are entitled to your own opinion and can >always create a filter to remove the person from your >viewing consideration. I am currently kill filing the majority of Google posters, I wish it could be automated. If you don't want to see usenet turn into a wasteland of unanswered questions I suggest you do the same.Article: 77343
"Peter Alfke" <peter@xilinx.com> wrote: >I find it amazing and disturbing that people have the audacity to ask >for help and favors from this newsgroup, without giving their name, >their affiliation, or at least the reason for their question. >How would you react if somebody you had never seen before just barged >into your home or office and asked for a favor, without introducing >himself or explaining the reason for his question ? How would you react if they offered help and favours in the same manner? I have always regarded usenet as pretty impersonal. As you probably noticed from my other recent posts I am more concerned about the general health of usenet than civility levels. >Many of us love to help and explain, but I do not like to be taken >advantage of in a totally impersonal way... >Are newsgroups fostering the death of civility ? Damn, another post from Google asking a question ;)Article: 77344
"Eric Smith" <eric@brouhaha.com> wrote in message news:qh3bxh6ega.fsf@ruckus.brouhaha.com... > Is there any reason why using an LM317S adjustable linear regulator with > 1% resistors wouldn't be satisfactory for the Spartan 3 power supplies, > particularly Vccint and Vccaux? > > I have a cost-sensitive application for which the LM317S looks to be > much less expensive than using fixed-output LDO regulators, e.g., > $0.58 for the LM317S vs. $4.45 for an LP3881ES-1.2 for Vccint. > > Thanks for any advice! > Eric First, you seem to be comparing LP3881 in qty.1 with LM317 in Qty.100. Alternatively, you can take a look at Sharp regulators PQ012FZ series. Digi-Key sells them for $.66 in qty.100 - aapArticle: 77345
Well, I am an optimist, and I believe that most people are decent, but some are just uneducated. If we point out their misbehavior, we can eliminate many of these problems. Few people like to behave like an insensitive idiot, especially once they got their sins pointed out to them. I will never post anonymously, I will just leave the company name out of this, when the posting is my personal voice and has little or nothing to do with Xilinx. As far as I am concerned, a fake identity is even better (and friendlier) than none. Many of us want to keep this newsgroup functioning, with a pleasant and polite tone of voice. It has been that way for many years, and I have enjoyed it. Peter AlfkeArticle: 77346
"Peter Alfke" <peter@xilinx.com> wrote in message news:1104863148.865070.96790@f14g2000cwb.googlegroups.com... > I find it amazing and disturbing that people have the audacity to ask > for help and favors from this newsgroup, without giving their name, > their affiliation, or at least the reason for their question. > > How would you react if somebody you had never seen before just barged > into your home or office and asked for a favor, without introducing > himself or explaining the reason for his question ? > > Many of us love to help and explain, but I do not like to be taken > advantage of in a totally impersonal way... > Are newsgroups fostering the death of civility ? > Peter Alfke > Peter, There may be cases where anonymity is important. Someone asking particular questions (or giving particular answers) may clue a competitor in on what that person/company is doing. Anonymity and civility are two separate issues. People can be impolite, in newsgroups, the same way that they can be when driving their cars. Would you push someone out of a line in a store? Of course not. Yet, cutting someone off, on the road, is commonplace. The cloak of a 4000 lb car, or a computer's screen, is a tempting excuse for some people to be rude. I'm not a religious person, but the "do unto others..." motto works well, for me. You are a gentleman, Peter -- on the internet and in person, too. Bob (not my real name)Article: 77347
Hello, If I configure Xilinx BRAM for a data width greater than 1, say 8 then will all the 8 bits corresponding to the particular byte be in the same BRAM configuration frame? or will they be distributed among multiple frames? If so are there any equations through which one can extract that data from the configuration bit stream. I read XAPP 151 but that does not give any information in this regard. Though it provides equations for finding the value of the bit based on the bit index there is no mention about the bit indices for the 8 bits within the byte. Thanks HarishArticle: 77348
As far as I know ML310 board comes with virtex II Pro FPGA that have PowerPC. Is there any specific reason you want to use Microblaze? Xilinx provides detailed documentation about ML310. Incase you haven't you might want to take a look at this site http://www.xilinx.com/products/boards/ml310/current/index.html Good luck HarishArticle: 77349
Eric wrote: > >As it turns out, the LM317S won't meet the spec either > - The "A" variants of the LM317 have better reference specs ( 1.262 V max at Tj = 25C, 1.270 V over -40 to +125 C ) Which is within an IR drop of Spartan3 VCCINT max for amp-ish load currents, plus both the load regulation and Vref vs temp curves for the LM317 show a decreasing Vout for Tj > 25 C - IIRC, grounding ADJ on a 317 sets Vout = Vref with no resistors - also, see the very latest S3 errata for brand new VCCINT ramp rate and supply sequencing requirements - National budgetary pricing of $0.43 @ 1K units for LM317AT Speaking of low cost, last year you (Eric) wrote: http://groups-beta.google.com/group/comp.arch.fpga/msg/b52d92042d057d2f > > I desperately need the development software (XACT) > for 2064 and 2018 parts in order to do some maintenance > on a client design. > After reading that post, I emailed you the offer of a box of XACT 5.x disks and manuals for the cost of shipping, to which you agreed. The UPS package was delivered to you on April 23. Some 8+ months later, I'm still waiting for payment or a response to any of my subsequent e-mails. Brian
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