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Rick Fox <NewsGroups@softhome.net> writes: <snip> > Third, is there anyone who has a Master Programmer or other capable > programmer (in the UK, preferably near Manchester) and would be > prepared to help me out and reprogram about 25 CPLD's? I don't mind > donating a few beer tokens if it will help! > We have old Altera programming hardware, and an 84PLCC module for it. It's ISA only, which may cause fun! I assume that the modern software can handle it, dunno if we have any older CDs easily to hand. Contact me offline if you're interested. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 78951
This page:
http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0026_5.html#wp325264
shows some templates for ROM inference in Spartan3 using Xilinx's ISE
software.
One of the templates is:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rominfr is
port (
clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(3 downto 0)
);
end rominfr;
architecture syn of rominfr is
type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);
constant ROM : rom_type :=
("0001","0010","0011","0100","0101","0110","0111","1000","1001","1010"
,"1011","1100","1101","1110","1111","0001","0010","0011","0100","0101"
,"0110","0111","1000","1001","1010","1011","1100","1101","1110","1111" );
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (en = '1') then
data <= ROM(conv_integer(addr);
end if;
end if;
end process;
end syn;
My question is: are they types of the inputs and outputs important for the
software to infer the ROM? For example, could I have:
entity rominfr is
port (
clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector(9 downto 0);
data : out ufixed(0 downto -17) -- ufixed is fixed point
--type from:
--http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html
);
end rominfr;
Would the ROM still be inferred because I didn't use std_logic_vector on
the data output? Just wondering how strict the template must be adhered
to.
There are conversion routines to go to/from std_logic_vector<=>ufixed,
however I'd prefer to keep the output of the ROM in ufixed format if
possible.
Phil
Article: 78952Hi Andre, I think this thread should answer your question ... http://tinyurl.com/4ycl7 If you're trying to keep a wire/combinational logic, use the KEEP attribute. If you're trying to keep a register, use the Assignment Editor as described. HTH, -- Pete [ p s o m m e r f e l d (at) gmail.com ] Andr=E9s wrote: > ALuPin wrote: > > Hi, > > > > in one the last posts Christos recommended me to use Virtual Pins > > if I want the Fitter not to optimize registered unused signals away. > > > > I have a module "sie.vhd" instantiated in my top level schematic design file > > "top_d.vhd". > > > > The module "sie.vhd" has a port "Eop_not_recog" of type std_logic. > > It is a registered signal which is not used at all. > > > > (I use Altera QuartusII v 4.2). > > > > In the Assignment Editor > > under LOGIC OPTIONS --> ADVANCED I define a Virtual Pin by > > going to the NODE FINDER and selecting the signal "Eop_not_recog" of the entity > > "sie.vhd" with the filter "Register : pre-synthesis". > > Then I select ASSIGNMENT NAME=3DVirtual Pin, VALUE=3DOn, ENABLED=3DYes > > > > After compilation I go into the NODE FINDER again to see if "Eop_not_recog" > > is still listed with the filter "Registers : post-fitting", > > but it is not. I conclude from this > > that the fitter optimized the node away although I defined the node > > as a Virtual pin. > > > > Can someone explain to me what went wrong? > > > > Thank you for your help. > > > > Rgds > > Somethin additional: > Christos said: > >One thing that might work is to drive them to outputs and then define > >those > >outputs as virtual pins with the assignment editor. > >They will not be synthesised away. > > In the QuartusII Help it is said: > >This option should be specified only for I/O elements that become > nodes >when imported to the top-level design. > > So do I have to route the signal in the top level file to a FPGA pin and > define it as VIRTUAL then > or do I have to define the Port of the component "sie_rec.vhd" as virtual ? >=20 > It is not explained very clear. >=20 > Thank you. >=20 > Rgds > Andr=E9Article: 78953
Alex <uksb@greenbank.org> wrote: >Alex <uksb@greenbank.org> wrote: >[ SNIP original request ] > >Thank you for all of the replies. I've ordered directly >from Xilinx and I'm looking forward to my new toy >arriving. Did you or anyone else get the now bundled EDK evaluation (and 6.3i ISE evaluation I presume because the 6.3i EDK appears to need it)?Article: 78954
Hi Folks,
I have been working my way through the tutorial that is supplied with
the JBits 3.0 SDK, and have encounter the following problem when
running
the TracerExample.java
(<JBITS_HOME>\src\com\xilinx\demo\tracer\TracerExample.java)
Exception in thread "main" java.lang.NullPointerException
at com.xilinx.JBits.Virtex2.Wire.exists(Wire.java:130)
at com.xilinx.JBits.Virtex2.Pin.<init>(Pin.java:86)
at com.xilinx.demo.tracer.TracerExample.main(TracerExample.java:48)
Which seems to point to the following
...........
/* set the JBits object in the Wire class */
Wire.setJBits(jbits);
/* Get the lookup instance */
Lookup lookup = Lookup.getLookup();
/* Instantiate a RouteTracer */
RouteTracer tracer = new RouteTracer(lookup);
/* Trace CLB(0,0,XQ0) and print out the net */
Pin src = new Pin(Pin.CLB, 0, 0, Wire.XQ0); <-- This is line
48
............
And I was wondering if anyone has came across the same problem and
hopefully found a solution which they could share with me, As I can't
find an pointers to the solution on google.
Any help great fully received,
Regards,
Paddy
Article: 78955Joerg Ritter <ritter@informatik.uni-halle.de> writes: > but now I get an error on that web site Fixed, sorry. -HeinArticle: 78956
Dear all, I have a Xilinx-ML300 at hand,and want to test the Gemac core by connect FPGA with PC via Gigabit-Ethernet. The problem is on ML300 the RJ45 connector is not for gigabit ethernet. There is optical fiber link avaiable and also MultiGigabitTransceivers(MGTs) avaiable. One solution is using the optical links. While another people told me to use MGT to implement the gigabitEthernet? Is that possible? If yes,how? Shall I use both gemac and MGT? Or only MGT? No idea about it? Any information is appreciated. Thanks with regards!Article: 78957
PS:email me by remove '(dot)' appeared. Thanks!Article: 78958
Hi to everyone, I am quite stucked with a problem for several days and I would like to ask for some possible help. I am trying to download a project to a Avnet Board on a Virtex 2 Pro xc2vp7 and debugging with XMD and GBD from EDK 6.3 through JTAG parallel cable IV. First of all I download my design (download.bit) with the download option from the tools menu of EDK. Ok After that finishes correctly I open XMD form a Xygwin shell and type 'connect ppc hw' to connect to the PowerPC core and everything seems to work correctly since I get the message: xmd: starting gdb server for "ppc" target <id=0> at TCP port 1234 I assume that this assures that the PowerPC degugger is listening at port 1234 for any GBD requests. But when I connect to 'localhost' to port '1234' with the software debugger I always recieve the same messages from the XMD console: Accepted a new GDB connection from 127.0.0.1 on port 2325 putpkt<read>: invalid argument Closed GDB connection from 127.0.0.1 on port 2325 This always occurs either choosing 'run' (the code) or 'connect to target' on GBD. After a while I get a Windows alert message with: GDB Couldn't establish connection to remote target Malformed response to offset query, timeout GDB cannot connect to the target board using localhost:1234. Verify that the board is securely connected and, if necessary, modify the port setting with the debugger preferences. I am connected to the board with hyperterminal 9600 bauds with a serial cable, the JTAG parallel cable is powered and so is the board. The board lights seem to be all ok. No malfunction. I really don't know why I can't start downloading the .elf file to the board. For some reason the debug core isn't accepting requests from the software debugger. Could the baudrate be the problem? The board serial port works on 9600 bauds, I even tried choosing other baudrates concluding the same. Am I missing something? Thanks a lot. Adrian.Article: 78959
"nospam" <nospam@nospam.invalid> wrote in message news:dq2n015ge9pgefno5jl0rlod7d7aao9m74@4ax.com... > Alex <uksb@greenbank.org> wrote: > >>Alex <uksb@greenbank.org> wrote: >>[ SNIP original request ] >> >>Thank you for all of the replies. I've ordered directly >>from Xilinx and I'm looking forward to my new toy >>arriving. > > Did you or anyone else get the now bundled EDK evaluation (and 6.3i ISE > evaluation I presume because the 6.3i EDK appears to need it)? > I have not got my EDK either. The Spartan III starter kit came with the ISE eval CD's I emailed the online store on Feb 07, 2005 and got the same answer as Carsten did on Jan 30, 2005 : "quote" The EDK eval is being sent to all who have purchased the Spartan 3 Starter kit and will begin shipping within the next couple of weeks. "unquote" I replied : On or before Jan 30, 2005, you gave the same exact answer to another customer.My question is, has your schedule slipped. The answer on Feb 08, 2005 was : The only information I have at this time is what was provided to us by our Marketing group. If possible, please send me your ship to address and ship to address of the other customer.I will then forward that information directly to the department responsible for the eval. I replied back on Feb 08, 2005 with the information requested. I have yet to receive an answer back as of Feb 10, 2005. - NewmanArticle: 78960
Just an idea.. have you downloaded the download.bit file to the FPGA prior to trying to connect to it via the XMD? you must press the "download" button prior to connecting to the xmd. after pressing it the download.bit file will be loaded to the FPGA and only then the XMD sequence can start. I hope that it will be helpful and that get you to work again. Moti.Article: 78961
I think I understand what went wrong.. look below. "Andrés" <nospam_nussspucke@gmx.de> wrote in message news:3718pjF58afv7U1@individual.net... > ALuPin wrote: > > Hi, > > > > in one the last posts Christos recommended me to use Virtual Pins > > if I want the Fitter not to optimize registered unused signals away. > > > > I have a module "sie.vhd" instantiated in my top level schematic design file > > "top_d.vhd". > > > > The module "sie.vhd" has a port "Eop_not_recog" of type std_logic. > > It is a registered signal which is not used at all. > > Define also in the top level the "Eop_not_recog" as a port. then use the assignment editor as you describe below but only this time for this port. > > (I use Altera QuartusII v 4.2). > > > > In the Assignment Editor > > under LOGIC OPTIONS --> ADVANCED I define a Virtual Pin by > > going to the NODE FINDER and selecting the signal "Eop_not_recog" of the entity > > "sie.vhd" with the filter "Register : pre-synthesis". > > Then I select ASSIGNMENT NAME=Virtual Pin, VALUE=On, ENABLED=Yes > > > > After compilation I go into the NODE FINDER again to see if "Eop_not_recog" > > is still listed with the filter "Registers : post-fitting", > > but it is not. I conclude from this > > that the fitter optimized the node away although I defined the node > > as a Virtual pin. After compilation go to NODE FINDER and search for pins: all and you will find it. > Somethin additional: > Christos said: > >One thing that might work is to drive them to outputs and then define > >those > >outputs as virtual pins with the assignment editor. > >They will not be synthesised away. > > In the QuartusII Help it is said: > >This option should be specified only for I/O elements that become > nodes >when imported to the top-level design. > > So do I have to route the signal in the top level file to a FPGA pin and > define it as VIRTUAL then > or do I have to define the Port of the component "sie_rec.vhd" as virtual ? > > It is not explained very clear. I think you have found it and it is clear. The virtual pin can be only a pin, i.e. in, out or bidir and thus has to be routed up to the top level. > > Thank you. > > Rgds > André > I hope it works for you. if not mail me directly .. Christos dot Zamantzas at cern dot chArticle: 78962
"Jeffsen" <xjf77@yahoo.(dot)com> schrieb im Newsbeitrag news:ee8bbd0.-1@webx.sUN8CHnE... > Dear all, I have a Xilinx-ML300 at hand,and want to test the Gemac core by connect FPGA with PC via Gigabit-Ethernet. The problem is on ML300 the RJ45 connector is not for gigabit ethernet. There is optical fiber link avaiable and also MultiGigabitTransceivers(MGTs) avaiable. One solution is using the optical links. While another people told me to use MGT to implement the gigabitEthernet? Is that possible? If yes,how? Shall I use both gemac and MGT? Or only MGT? No idea about it? Any information is appreciated. Thanks with regards! www.xilinx.com GSRD xapp536.zip gigabit ref design for ML300 Antti PS the ML300 optical things are nice but not sure if you have any other equipment where to plug the optical fibre from them...Article: 78963
Oopps have'nt saw that you already did it.. Sorry.. Moti.Article: 78964
"adrian" <adrian.mora@terra.es> wrote in message news:fxMOd.290563$A7.405663@telenews.teleline.es... > Hi to everyone, > > I am quite stucked with a problem for several days and I would like to ask > for some possible help. > > I am trying to download a project to a Avnet Board on a Virtex 2 Pro > xc2vp7 and debugging with XMD and GBD from EDK 6.3 through JTAG parallel > cable IV. > First of all I download my design (download.bit) with the download option > from the tools menu of EDK. Ok > After that finishes correctly I open XMD form a Xygwin shell and type > 'connect ppc hw' to connect to the PowerPC core and everything seems to > work correctly since I get the message: > > xmd: starting gdb server for "ppc" target <id=0> at TCP port 1234 > > I assume that this assures that the PowerPC degugger is listening at port > 1234 for any GBD requests. > But when I connect to 'localhost' to port '1234' with the software > debugger I always recieve the same messages from the XMD console: > > Accepted a new GDB connection from 127.0.0.1 on port 2325 > > putpkt<read>: invalid argument > > Closed GDB connection from 127.0.0.1 on port 2325 > > This always occurs either choosing 'run' (the code) or 'connect to target' > on GBD. > After a while I get a Windows alert message with: > > > GDB > > > Couldn't establish connection to remote target > > Malformed response to offset query, timeout > > GDB cannot connect to the target board using localhost:1234. > > Verify that the board is securely connected and, if necessary, > > modify the port setting with the debugger preferences. > > I am connected to the board with hyperterminal 9600 bauds with a serial > cable, the JTAG parallel cable is powered and so is the board. The board > lights seem to be all ok. No malfunction. > > I really don't know why I can't start downloading the .elf file to the > board. For some reason the debug core isn't accepting requests from the > software debugger. Could the baudrate be the problem? The board serial > port works on 9600 bauds, I even tried choosing other baudrates concluding > the same. Am I missing something? > > Thanks a lot. > Adrian. > Adrian, Sometimes I have found that after opening XMD and doing a ppcconnect, that if a issue a stop, and then a rst from XMD before I invoke gdb, it works better. - NewmanArticle: 78965
>> > For xilinx FPGAs it isnt necessary :) just dump all the mmc card from >> > sector >> > 0! >> > FPGA will sync itself when the bitstream begins :) >> > >> >> with a card reader, are you sure that the first file will be at sector 0 > in >> a just formatted MMC? >> > No, it want be, but that doesnt matter :) > the all content before the actual bitstream is dumped to FPGA as well > it is discarded by FPGA config logic, as it is looking for sync word > Sounds good. But these SD cards aren't they built with NAND Flash? And NAND Flash can have bad sectors. If one of these bad sectors is one of the first you can't use it. There was a similar idea some time ago to configure the FPGA from a NAND flash. With pointers from one sector to the next good sector. However, this design will take some more resources in an CPLD - not worth the effort. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 78966
"newman5382" <newman5382@yahoo.com> wrote: >> Did you or anyone else get the now bundled EDK evaluation (and 6.3i ISE >> evaluation I presume because the 6.3i EDK appears to need it)? >I have not got my EDK either. The Spartan III starter kit came with the ISE >eval CD's ISE 6.2i? >The answer on Feb 08, 2005 was : >The only information I have at this time is what was provided to us by our >Marketing group. If possible, please send me your ship to address and ship >to address of the other customer.I will then forward that information >directly to the department responsible for the eval. >I replied back on Feb 08, 2005 with the information requested. I have yet >to receive an answer back as of Feb 10, 2005. I got my starter kit from Insight in the UK so I will ask them, from your findings I guess I will be waiting a while.Article: 78967
"nospam" <nospam@nospam.invalid> wrote in message news:l67n01l0igpcron5qtc7u322lkqpgp23bl@4ax.com... > "newman5382" <newman5382@yahoo.com> wrote: > >>> Did you or anyone else get the now bundled EDK evaluation (and 6.3i ISE >>> evaluation I presume because the 6.3i EDK appears to need it)? > >>I have not got my EDK either. The Spartan III starter kit came with the >>ISE >>eval CD's > > ISE 6.2i? ISE 6.3i. > >>The answer on Feb 08, 2005 was : >>The only information I have at this time is what was provided to us by our >>Marketing group. If possible, please send me your ship to address and ship >>to address of the other customer.I will then forward that information >>directly to the department responsible for the eval. > >>I replied back on Feb 08, 2005 with the information requested. I have yet >>to receive an answer back as of Feb 10, 2005. > > I got my starter kit from Insight in the UK so I will ask them, from your > findings I guess I will be waiting a while. >Article: 78968
On Thu, 10 Feb 2005 17:16:27 GMT, "newman5382" <newman5382@yahoo.com> wrote: >I have not got my EDK either. The Spartan III starter kit came with the ISE >eval CD's I emailed the online store on Feb 07, 2005 and got the same >answer as Carsten did on Jan 30, 2005 : > >"quote" >The EDK eval is being sent to all who have purchased the Spartan 3 >Starter kit and will begin shipping within the next couple of weeks. > >"unquote" > >I replied : > >On or before Jan 30, 2005, you gave the same exact answer to another >customer.My question is, has your schedule slipped. Well i havent heard from them since , but then they said a couple of weeks, its just been 1.5 weeks since .... I still think its an excellent service (for free) , and hope they ship an ISE 6.3 eval also as it seems that the ISE 6.2 eval that was with the starterkit cant be used for the EDK CarstenArticle: 78969
Has anyone ever encountered a problem of this type? "newman5382" <newman5382@yahoo.com> escribió en el mensaje news:9VMOd.57800$JF2.36411@tornado.tampabay.rr.com... > > "adrian" <adrian.mora@terra.es> wrote in message > news:fxMOd.290563$A7.405663@telenews.teleline.es... >> Hi to everyone, >> >> I am quite stucked with a problem for several days and I would like to >> ask for some possible help. >> >> I am trying to download a project to a Avnet Board on a Virtex 2 Pro >> xc2vp7 and debugging with XMD and GBD from EDK 6.3 through JTAG parallel >> cable IV. >> First of all I download my design (download.bit) with the download option >> from the tools menu of EDK. Ok >> After that finishes correctly I open XMD form a Xygwin shell and type >> 'connect ppc hw' to connect to the PowerPC core and everything seems to >> work correctly since I get the message: >> >> xmd: starting gdb server for "ppc" target <id=0> at TCP port 1234 >> >> I assume that this assures that the PowerPC degugger is listening at port >> 1234 for any GBD requests. >> But when I connect to 'localhost' to port '1234' with the software >> debugger I always recieve the same messages from the XMD console: >> >> Accepted a new GDB connection from 127.0.0.1 on port 2325 >> >> putpkt<read>: invalid argument >> >> Closed GDB connection from 127.0.0.1 on port 2325 >> >> This always occurs either choosing 'run' (the code) or 'connect to >> target' on GBD. >> After a while I get a Windows alert message with: >> >> >> GDB >> >> >> Couldn't establish connection to remote target >> >> Malformed response to offset query, timeout >> >> GDB cannot connect to the target board using localhost:1234. >> >> Verify that the board is securely connected and, if necessary, >> >> modify the port setting with the debugger preferences. >> >> I am connected to the board with hyperterminal 9600 bauds with a serial >> cable, the JTAG parallel cable is powered and so is the board. The board >> lights seem to be all ok. No malfunction. >> >> I really don't know why I can't start downloading the .elf file to the >> board. For some reason the debug core isn't accepting requests from the >> software debugger. Could the baudrate be the problem? The board serial >> port works on 9600 bauds, I even tried choosing other baudrates >> concluding the same. Am I missing something? >> >> Thanks a lot. >> Adrian. >> > Adrian, > Sometimes I have found that after opening XMD and doing a ppcconnect, > that if a issue a stop, and then a rst from XMD before I invoke gdb, it > works better. > > - Newman > >Article: 78970
This problem was caused because the "tileWireExists.serial" file wasn't accessible on my classpath. Adding the <JBITS_HOME> variable to my classpath fixed it. (note that the jar file must be unzipped)Article: 78971
There is someone who has free VHDL code? "Marco" <marcotoschi@email.it> wrote in message news:cuf9og$6da$1@news.ngi.it... > Hallo to everyone, > I should develop a microcontroller based on microblaze with keypad and > 320x240 graphic LCD for an university exam. > > I should also make a printer interface to print datas displayed on LCD. > > There is someone who could help me? > > Many Thanks in advance > Marco > >Article: 78972
"newman5382" <newman5382@yahoo.com> wrote: > >"nospam" <nospam@nospam.invalid> wrote in message >news:l67n01l0igpcron5qtc7u322lkqpgp23bl@4ax.com... >> "newman5382" <newman5382@yahoo.com> wrote: >> >>>> Did you or anyone else get the now bundled EDK evaluation (and 6.3i ISE >>>> evaluation I presume because the 6.3i EDK appears to need it)? >> >>>I have not got my EDK either. The Spartan III starter kit came with the >>>ISE >>>eval CD's >> >> ISE 6.2i? > >ISE 6.3i. The Xilinx online shop still says the starter kit ships with ISE 6.2i which is what mine came with. Please add to this thread if you have any news, I will if I hear something from my distributor.Article: 78973
I take it that the stop, rst command in XMD before you start gdb did not help. Are you using the jtagppc_cntl in the V2Pro design? If so, the serial baud rate should not be an issue at this point in time. After you do a ppcconnect in xmd, can you do a stop, rst, srrd? The srrd should dump a bunch of Power PC registers. If it does not do these things, there is little point in trying to get gdb to work. -Newman "adrian" <adrian.mora@terra.es> wrote in message news:NyNOd.295281$A7.410288@telenews.teleline.es... > Has anyone ever encountered a problem of this type? > > "newman5382" <newman5382@yahoo.com> escribió en el mensaje > news:9VMOd.57800$JF2.36411@tornado.tampabay.rr.com... >> >> "adrian" <adrian.mora@terra.es> wrote in message >> news:fxMOd.290563$A7.405663@telenews.teleline.es... >>> Hi to everyone, >>> >>> I am quite stucked with a problem for several days and I would like to >>> ask for some possible help. >>> >>> I am trying to download a project to a Avnet Board on a Virtex 2 Pro >>> xc2vp7 and debugging with XMD and GBD from EDK 6.3 through JTAG parallel >>> cable IV. >>> First of all I download my design (download.bit) with the download >>> option from the tools menu of EDK. Ok >>> After that finishes correctly I open XMD form a Xygwin shell and type >>> 'connect ppc hw' to connect to the PowerPC core and everything seems to >>> work correctly since I get the message: >>> >>> xmd: starting gdb server for "ppc" target <id=0> at TCP port 1234 >>> >>> I assume that this assures that the PowerPC degugger is listening at >>> port 1234 for any GBD requests. >>> But when I connect to 'localhost' to port '1234' with the software >>> debugger I always recieve the same messages from the XMD console: >>> >>> Accepted a new GDB connection from 127.0.0.1 on port 2325 >>> >>> putpkt<read>: invalid argument >>> >>> Closed GDB connection from 127.0.0.1 on port 2325 >>> >>> This always occurs either choosing 'run' (the code) or 'connect to >>> target' on GBD. >>> After a while I get a Windows alert message with: >>> >>> >>> GDB >>> >>> >>> Couldn't establish connection to remote target >>> >>> Malformed response to offset query, timeout >>> >>> GDB cannot connect to the target board using localhost:1234. >>> >>> Verify that the board is securely connected and, if necessary, >>> >>> modify the port setting with the debugger preferences. >>> >>> I am connected to the board with hyperterminal 9600 bauds with a serial >>> cable, the JTAG parallel cable is powered and so is the board. The board >>> lights seem to be all ok. No malfunction. >>> >>> I really don't know why I can't start downloading the .elf file to the >>> board. For some reason the debug core isn't accepting requests from the >>> software debugger. Could the baudrate be the problem? The board serial >>> port works on 9600 bauds, I even tried choosing other baudrates >>> concluding the same. Am I missing something? >>> >>> Thanks a lot. >>> Adrian. >>> >> Adrian, >> Sometimes I have found that after opening XMD and doing a ppcconnect, >> that if a issue a stop, and then a rst from XMD before I invoke gdb, it >> works better. >> >> - Newman >> >> > >Article: 78974
I'm trying to implement the following C++ code using NIOS processor's native instruction set. int A; int B; for (int i = 0; i < B; i++) A = (A<<1)+4; Could some1 step out to point me in the right direction of how I am supposed to do this? Thanks...
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