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Peter Alfke wrote: > Jim, I like your idea, but it is not all that straightforward. > I mentioned in the seminar that there is a loadable synchronous counter > inside every DSP Slice, and it runs at 500 MHz, no ifs, no buts. > Now, I will build a 5 GHz counter using the MGT. Is that allowed? Certainly, Yes, just publish what you are using, and how. Ideally, do a design that allows optional enable of that feature. > DDS obviously runs at 500 MHz in the DSP slice, but I will run a > virtual 8 GHz DDS either by using 16 accumulators, or by doing some > clever math. Is that kosher? Again, certainly. I (and others) would be more interested in the ways to push the envelope, than in a simple 500MHz number. I would also suggest doing both, so users can see the performance jump, and resource needed to get that ( and any trade-offs ? ) > If you saw my seminar, I mentioned those things, and there will be app > notes, etc. > Storage oscilloscope is dear to my heart, but it has many arbitrary > parameters. > Its performance and cost are determined by the A/D at the input, not > the FPGA. Understood - but the FPGA tests would be for a virtual A/D - you would design, and state the system can burst acquire [this Size] at [This MHz] and Stream continually at [that MHz]. If there are no (yet) available ADCs, then the FPGA is not (presently) the weak link. I expect with 2Gsps ADCs around, you would struggle to hit that ? - but you could go wider, eg 16 bit datapaths have little extra cost in a FPGA, but a 1Gsps 16 bit ADC is quite different to deisgn than 1Gsps 8 bit ADC... I did see that one can now get 1Gsps 16 bit DACs (!), so there is a ref point for a low distortion, signal generator design for your FPGA .... http://www.analog.com/en/press/0,2890,3%255F%255F55189,00.html Counters/pulse measure/generate you could ship as working demo-board examples [LCD display], but a full storage scope might need a rather special demo board, with a shorter design life... Talk with ADI, or Atmel ? > I suggest we keep generating creative app notes, reference designs, and > evaluation boards, without calling them benchmarks. Call them anything you like :) - just update them real early in the product life cycles, so users can do the comparisons. Call them 'priority updated App notes' if you like, and (re)post the sources, _and_ tool report files, for each speed-grade revision, so users can review the info, without needing to install version XYZ of the tools, or they can fully duplicate if they wish. > > BTW: > Choosing between X and A isn't all that difficult, it's only between > two suppliers. Actel and Lattice might beg to differ....? > Selecting between umpteen brands of breakfast cereals, > washing mashines, cars, or colleges for your kids is a much tougher > task. ( Life in NZ may be simpler, but the choices in the US are > mindboggling. ;-) > Peter Alfke -jgArticle: 78726
Hi Jim, > Funny, I was sure this was an Altera link ( you have seen this ? ) > http://www.altera.com/corporate/news_room/releases/products/nr-perf_power.html > To me that looks rather more than a 5% nudge ? I explicitly noted that toggle rate limitations were an exception to my "5%" rule on core performance. We artificially restrict the performance of some blocks in the chip (relative to HSpice sims) pending silicon correlation. We like to test the chip under harsh conditions -- for example, with many blocks/registers all switching simulateously. Once these tests show that a block can run at a particular speed, we may up the "speed limit" for that block. Memory blocks are funny beasts that may not quite behave the way we expect based solely on simulations, and as such we make sure we spec their performance conservatively until we have silicon in our hands, tested at extreme conditions, to tell us its ok. Why do we do this? The Fmax of plain-old logic and delay of any path that involves multiple block types and hops is not that sensitive to negative changes in spec. If we were (hypothetically speaking) to slow down the LUT by 3%, the user could probably cover the drop in speed by increasing effort levels in the CAD tools or re-optimizing their design. On the other hand, block speed (maximum toggle rate of a M4K block, for example) is a system-architecture issue. If we say our RAMs run at 400 Mhz and we're wrong, this could completely undermine a system design. No level of manual or cad-tool optimization will ever cover a reduction in block performance. > Does this mean the prelim models were not as good as you claim, or are > you more carefully qualifying the best ones, to better compete with > Xilinx's claims ? We're always interested in showing off the best performance we can. In the case of our block speeds, we would like to expose faster speeds, but will only do so if we believe it is safe to do so. In Quartus 4.1, we increased speeds, and it is likely we will do so again in a future release of the software. I'm not terribly worried about competing against Xilinx's block speeds, since (a) the "fast" device is not out yet and (b) it is rare for people to need to run their core blocks at such high speeds, since the logic + routing fabric (particularly in slower chips) can't keep up. Plus we'll see where the final spec for Stratix II ends up. > Will we see a 'bragging rights' bin, that is the > three sigma yield limit, and so very expensive, but hey, look how > fast we are !! Some would argue (probably all from Altera :-)) that you do see that today with Xilinx. Not 3 sigma, but clearly they are pushing the process for the fast speed grade otherwise they'd have it out already. You'll notice that Altera has always released all three speed grades concurrently except for the very largest devices. You can draw your own conclusions from that. Regards, Paul Leventis Altera Corp.Article: 78727
Hi Peter, I congratulate you on your efforts to deflect attention from poor core performance to various IP block toggle rates. But I'd hate to break it to you Peter -- while designs now incorporate more IP than they used to, they continue to have lots and lots of LUTs and routing. I don't think making a superior architecture for these "legacy" functions is a waste of energy. I have never argued that core performance is the only aspect of chip performance, but it is a very important one. Our experience from Stratix was that not too many customers ever pushed blocks (RAMs, MACs) to run at their peak toggle rate. It is difficult to pump enough data through the rest of the fabric at a high enough rate to do so. There are some applications where the block toggle rate is a limiting factor, but they are few and far between. Core performance can be an insurmountable road block to design success, and worse, it is hard to predict in advance. You know early in a design process that you need DDR at 200 Mhz and a memory block operating at 350 Mhz. And you can check the data sheet to see if part will meet this need. You don't know what speed the logic of your design will hit until you've run P&R on the full design. With Stratix II, we minimize the chance that core performance will be an in issue. Faster logic + routing performance translates into less effort for our users and our FAEs, since more designs meet performance goals at the push of a button. What our +39% number is saying is that if both Stratix II and Virtex-4 meet the customer's needs in terms of major features (I/O standards, pins, etc) and critical block performance (say, necessary speed for a memory), then Stratix II will be the better choice -- it will be more likely to meet the overall performance goals of the product and will do so with greater ease. > Altera changed the LUT structure significantly, and I can believe that > this makes certain applications faster, if they can tolerate shared > inputs. But Altera made no systems-oriented functional changes, added > no new functions or structures. Shared inputs do not need to be "tolerated" -- they are an available but not necessary feature. Ignoring all other aspects of the ALM, a 6-input LUT can do a lot more than a 4-LUT, reducing the depth of the critical path and hence increasing its speed. The reason where straight 6-LUTs lose out to 4-LUTs is in area (or silicon cost) -- that's where all the other innovations in the ALM come in, including shared inputs. For example, the ALM can split into two (fully indepedent) 4-LUTs. Or you can share some inputs and/or LUT mask bits and create two larger functions. With the ALM, you get the speed when you need it and good area when you do not. On the system/functional changes, a number of V4 features are merely playing catch up to what was done in Stratix. You now have a MAC block, but you still can't do 36x36 or 9x9 multiplies efficiently. You now have a flexible clock network like Stratix. And some of the innovations are areas of past contention and are nothing new. Hard processors and SRL16 come to mind -- we've debated these before. On the high-speed I/O front, we will have Stratix II GX and eventually you will release your devices with high-speed I/Os... it'll be Virtex II-Pro vs. Stratix GX all over again. That leaves us with FIFOs. They are interesting... but what value do they add over soft-logic implementations? Are they worth the silicon cost? And I should point out that Stratix II contains changes to the memory blocks that allows more efficient soft-logic FIFO implementations; we may not have built a full FIFO, but we made it easier to do so. > I bet there are no dual-clock FIFOs in the Altera benchmarks, or 32-tap > FIR filters, or Gigabit SerDes, or microprocessors, or even SRL16s or > LUT-RAMs. Such applications do not exist in the old designs, or they > are implemented in such different, less efficient ways that they do not > migrate. There are in fact FIFOs, FIR, SRL16s and LUTRAMs in our benchmark set. But you do have a point -- no one will ever be able to make a generic benchmark set that will properly take advantage of system-level features of an architecture, and hence benchmarking will never tell the full story on system throughput. Regards, Paul Leventis Altera Corp.Article: 78728
Pete Fraser wrote: > Just got round to firing up my ML401 last weekend. > > The quality of the video output is terrible. > Do I have a faulty board, or is it a design/layout issue? > > The video out has asynchronous resonant spikes running > through it. The spikes are about 100 mV p-p, and have a > resonant frequency of about 250 MHz, with about 6 half-cycles > present. Mine is rock solid clean image on all the demos that comes built-in. > There is also about 15 mV p-p of pixel clock and harmonics. > > Jitter is about 5ns p-p. > > I have not yet poked around with a scope or stared at > the layout. I was hoping this is a board rather than > a design problem, as I had intended to use the board for > some video tests. > > Also, the V4 is quite toasty. After running the slideshow > for a few minutes the temperature is in the high 60s. > Is this reasonable? (It's an ES part). Mine is comfortably warm to touch. I'm guessing 45 gr Celcius. I sounds like you got a marginal part. I'd return it immediately. TommyArticle: 78729
I have a project which started with MP2 w. Leonardo and was converted by several versions of Quartus (including several new file types). With Quartus 4.2 I thought the project merely consists of proj.qpf and proj.qsf. Having all the assignments in the .qsf file. However, when I compiled the project with the other 'old' project files removed it resulted in a different solution (fmax was 95MHz instead of 100MHz). Adding the proj_assignment_defaults.qpf back to the project I got the original result. So the question is: What's this xxx_as._def.qpf for? Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 78730
Hi Peter, sorry I havent been emailing (to say many thanks,etc) it has been and still is! on my task list. just a quick question - are there any V4 SF363 samples (even mechanical dummies) avaiable for Xilinx-on board product press photo shouting? ah yes I am now working at Eubus! so we have designed a really cool product a FULL computer in DIP40 the module can be used with any SF363 packaged Xilinx FPGA, that is we will have to variants one for S3 one for V4 we where supposed to have one sample this week but I think something went wrong so we would have PCB this thursday (dummy PCB only for presse photo!!) and well the only missing part (possible maybe we get it in time) might be the V4 so please let me know asap if there is something you can do as said maybe we get in time already, but I just want double insurance we are rushing a match to get the photos and ad materials ready for Nurnberg fair 22 FEB with best wishes Antti LukatsArticle: 78731
On Mon, 7 Feb 2005 10:21:42 +0100, "Antti Lukats" <antti@openchip.org> wrote: >Hi Peter, > >sorry I havent been emailing (to say many thanks,etc) it has been and still >is! on my task list. > >just a quick question - are there any V4 SF363 samples (even mechanical >dummies) avaiable >for Xilinx-on board product press photo shouting? ah yes I am now working at >Eubus! > >so we have designed a really cool product a FULL computer in DIP40 >the module can be used with any SF363 packaged Xilinx FPGA, that is we will >have >to variants one for S3 one for V4 > >we where supposed to have one sample this week but I think something went >wrong >so we would have PCB this thursday (dummy PCB only for presse photo!!) and >well >the only missing part (possible maybe we get it in time) might be the V4 > >so please let me know asap if there is something you can do > >as said maybe we get in time already, but I just want double insurance > >we are rushing a match to get the photos and ad materials ready for Nurnberg >fair 22 FEB > >with best wishes >Antti Lukats > Photoshop....?Article: 78732
SORRY I sent private mail to newsgroup!! Please dont read and delete ouch I feel embarraced BRRR SORRY Antti "Mike Harrison" <mike@whitewing.co.uk> schrieb im Newsbeitrag news:s4ee01dudtklsmjtqpdjtgatnfbri1ovl1@4ax.com... > On Mon, 7 Feb 2005 10:21:42 +0100, "Antti Lukats" <antti@openchip.org> wrote: > > >Hi Peter, > > > >sorry I havent been emailing (to say many thanks,etc) it has been and still > >is! on my task list. > > > >just a quick question - are there any V4 SF363 samples (even mechanical > >dummies) avaiable > >for Xilinx-on board product press photo shouting? ah yes I am now working at > >Eubus! > > > >so we have designed a really cool product a FULL computer in DIP40 > >the module can be used with any SF363 packaged Xilinx FPGA, that is we will > >have > >to variants one for S3 one for V4 > > > >we where supposed to have one sample this week but I think something went > >wrong > >so we would have PCB this thursday (dummy PCB only for presse photo!!) and > >well > >the only missing part (possible maybe we get it in time) might be the V4 > > > >so please let me know asap if there is something you can do > > > >as said maybe we get in time already, but I just want double insurance > > > >we are rushing a match to get the photos and ad materials ready for Nurnberg > >fair 22 FEB > > > >with best wishes > >Antti Lukats > > > Photoshop....?Article: 78733
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1107733371.888845.5080@l41g2000cwc.googlegroups.com... > Jim, I like your idea, but it is not all that straightforward. > I mentioned in the seminar that there is a loadable synchronous counter > inside every DSP Slice, and it runs at 500 MHz, no ifs, no buts. > Now, I will build a 5 GHz counter using the MGT. Is that allowed? > DDS obviously runs at 500 MHz in the DSP slice, but I will run a > virtual 8 GHz DDS either by using 16 accumulators, or by doing some Hi Peter I have already done that! its reletivly simple to use MGT as DDS with virtual 10GHz clock for every user clock 40 accu samples are calculated and I also am using MGT as 3GS/S logic analyzer with ChipScope I wish it would make sense for me to publish all that work AnttiArticle: 78734
It looks like that the Atmel AT25Fxxxx is a functional drop-in replacement for the serial configuration devices from Altera (EPCSx). Only the pinout differes. Any comments on this? Has someone managed to program these devices from the FPGA withou using NIOS? Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 78735
"Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag news:i7JNd.33865$2e4.11855@news.chello.at... > It looks like that the Atmel AT25Fxxxx is a functional drop-in replacement for the serial > configuration devices from Altera (EPCSx). Only the pinout differes. > Any comments on this? EPCS are custom labeled ST serial flash devices 25Pxx AT25F might be useable as well, but compare the prices, hmm 25P32 8Mbyte from ST 6.4$ digikey stock AT25P1024 1MByte Atmel 15.6$ digikey stock AT25F1024 1MByte 1.85$ hmm digikey no stock :( hm the P1024 was CASON8 (6x8mm), the F1024 is SAP even smaller 6x5mm well if you are sure you want to deal with Atmel and can by the parts and 1MByte is enough then the price isnt so bad. I am looking for 4MByte serial flash and there doesnt seem to be any alternative to 25P32 and that is unfortunatly only available in SOIC-16 WIDE, so no 4MByte device in Chip Scale available for direct purchases at the moment. Or at least I have not found. The difference betweeen 1MByte and 4MByte is very important for me, in 4MByte there is room for uClinux image in 2MByte devices not :( NexFlash has pin compatible parts to ST so there is second vendor availables, so I think I stick to 25P32 > Has someone managed to program these devices from the FPGA withou using NIOS? hm whats the problem? AnttiArticle: 78736
Hi,
Can anybody shed some light onto a problem that I am having getting the
xilkernel to behave! Essentially, I compile my simple program and the
kernel keeps creating new instances of itself at run time. The
prog_main() is set up as a static thread instance PARAMETER
static_pthread_table = ((prog_main,1)) in the MSS file. See the ouput
below (with verbose debug to true)
source
------
#include "xmk.h"
#include <stdio.h>
void *prog_main(void *arg);
int main ()
{
xilkernel_main ();
}
void *prog_main(void *arg)
{
static Index = 0;
printf("prog_main(%d) called\n\r", Index++);
while(1)
{
printf("In main - Data%d Index:%d\n\r", Data++, Index);
sleep(500);
}
}
output
------
In main - Data18 Index:6
In main - Data19 Index:6
Idle Task
XMK: Start
XMK: Initializing Hardware...
XMK: Initializing interrupt controller
XMK: Connecting timer interrupt
XMK: Starting the interrupt controller
XMK: Initializing PIT device.
XMK: System initialization...
XMK: Enabling interrupts and starting system...
prog_main(6) called
In main - Data20 Index:7
Idle Task
XMK: Start
XMK: Initializing Hardware...
XMK: Initializing interrupt controller
XMK: Connecting timer interrupt
XMK: Starting the interrupt controller
XMK: Initializing PIT device.
XMK: System initialization...
XMK: Enabling interrupts and starting system...
prog_main(7) called
In main - Data21 Index:8
Idle Task
In main - Data22 Index:8
In main - Data23 Index:8
In main - Data24 Index:8
In main - Data25 Index:
In main - Data1099 Index:407
In main - Data1100 Index:407
XMK: Start
XMK: Initializing Hardware...
XMK: Initializing interrupt controller
XMK: Connecting timer interrupt
XMK: Starting the interrupt controller
XMK: Initializing PIT device.
XMK: System initialization...
XMK: Enabling interrupts and starting system...
prog_main(407) called
In main - Data1101 Index:408
Idle Task
In main - Data1102 Index:408
XMK: Start
XMK: Initializing Hardware...
XMK: Initializing interrupt controller
XMK: Connecting timer interrupt
XMK: Starting the interrupt controller
XMK: Initializing PIT device.
XMK: System initialization...
XMK: Enabling interrupts and starting system...
prog_main(408) called
In main - Data1103 Index:409
Idle Task
etc!!!!
Article: 78737> I encountered tremendous of warning messages (2 types). I have exactly the same problem as you, the core is working fine, but all those warnings unsettle me. So I would be very greatful if somebody could help us with this issue Cheers PhilippArticle: 78738
Hi Jack, >From my experience those messages are due to logic optimization that is made by the synthisizer - and it's not likely that there are problematic. when you create a microblaze design you mostly don't use all of its internal signals and capabilties and therefore the synthisizer trims all of the unneeded logic. If your design works fine you should ignore those warnings that's what I do.... Regards, Moti.Article: 78739
Martin Schoeberl wrote: > It looks like that the Atmel AT25Fxxxx is a functional drop-in replacement for the serial > configuration devices from Altera (EPCSx). Only the pinout differes. > Any comments on this? > > Has someone managed to program these devices from the FPGA withou using NIOS? Just use it as normal SPI periphal and use the cyclone_asmiblock for it... rickArticle: 78740
Antti Lukats wrote: > SORRY > I sent private mail to newsgroup!! > Please dont read and delete > ouch I feel embarraced > BRRR SORRY > > Antti > > "Mike Harrison" <mike@whitewing.co.uk> schrieb im Newsbeitrag > news:s4ee01dudtklsmjtqpdjtgatnfbri1ovl1@4ax.com... > >>On Mon, 7 Feb 2005 10:21:42 +0100, "Antti Lukats" <antti@openchip.org> > > wrote: > >>>Hi Peter, >>> >>>sorry I havent been emailing (to say many thanks,etc) it has been and > > still > >>>is! on my task list. >>> >>>just a quick question - are there any V4 SF363 samples (even mechanical >>>dummies) avaiable >>>for Xilinx-on board product press photo shouting? ah yes I am now working > > at > >>>Eubus! >>> >>>so we have designed a really cool product a FULL computer in DIP40 >>>the module can be used with any SF363 packaged Xilinx FPGA, that is we > > will > >>>have >>>to variants one for S3 one for V4 >>> >>>we where supposed to have one sample this week but I think something went >>>wrong >>>so we would have PCB this thursday (dummy PCB only for presse photo!!) > > and > >>>well >>>the only missing part (possible maybe we get it in time) might be the V4 >>> >>>so please let me know asap if there is something you can do >>> >>>as said maybe we get in time already, but I just want double insurance >>> >>>we are rushing a match to get the photos and ad materials ready for > > Nurnberg > >>>fair 22 FEB >>> >>>with best wishes >>>Antti Lukats >>> >> >>Photoshop....? > > Whops :) Hey we all do silly things.. But.. since you DID send it to the list.. care to elaborate on this SOC you are working on? ( if you can that is.. ) And really, if its just a photoshoot.. why worry if its not the real thing? Just as long as it LOOKS like it..Article: 78741
When designing for partial reconfiguration, the ICAP port has to be into the fixed part of the design. ok, but where is it in the xc4vlx60? at the bottom of central column?Article: 78742
> Whops :) Hey we all do silly things.. > > But.. since you DID send it to the list.. care to elaborate on this SOC > you are working on? ( if you can that is.. ) ah, since I already OOPSED, then here it goes: it should really be "Xilinx all you dreamed of.." type of thing - a very small single supply powered module ready to load different hardware and different OS from smallest availabe removable media or from onboard large flash. Board is stuffed with pretty much latest stuff in smallest packages, BGA QFN CSP only. Base conf would be uClinux MicroBlaze but other options will be offered as well. Hm I have a rule of 10 (a design unit with more than 10 IC should be redesigned...) the modue is OK by that rule - so just take less than 10 latest "nice" parts you would like to see on such a module, and if you have done your homework then you should have about the list of whats actually on :) I think that above all I can say at the moment. AnttiArticle: 78743
>> Has someone managed to program these devices from the FPGA withou using > NIOS? > > hm whats the problem? > Don't know if it's a problem. Just havn't done it till now and didn't find any documentation about it from Altera.Article: 78744
Hein Roehrig wrote a detailed description on how to run Impact with parallel cable on a linux kernel of the 2.6 series. I can be found on our server: http://www.fpga.de/tiki/tiki-index.php?page=XilinxSoftwareLinux I also asked philip freidin to upload it to www.fpga-faq.com. I Hope this helps, Kolja SulimmaArticle: 78745
"Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag news:VELNd.33972$2e4.10640@news.chello.at... > >> Has someone managed to program these devices from the FPGA withou using > > NIOS? > > > > hm whats the problem? > > > Don't know if it's a problem. Just havn't done it till now and didn't find any documentation > about it from Altera. > Menu: File->Convert Programming File select .JIC select your serial device select your fpga add .sof convert start programmer add .JIC program That should be it! when it works :) AnttiArticle: 78746
I've seen a few threads recently about warnings in XST so I thought I'd put in my 2 cents. I've got a design where I instantiate the IOB flip-flops that drive the output enables. There are three sections with 5, 8 and 59 IOB's respectively that have equivalent IOB output enable timing. I still want all these flip- flops because they need to push into the IOB's to meet the clock-to-out timing requirements. Now XST decides to warn me that the flip-flops in each group are equivalent to eachother. That isn't too bad because I can ignore the warnings and it builds what I asked. Here's the fun part. In each group the number of warnings I get is 5 times the number of combinations of N things taken 2 at a time, where N is the number of equivalent flip-flops. So for the case of the 59 flops I get 8,555 warnings. Displaying these warnings takes the bulk of the synthesis time for the design. I can see that the synthesizer may be too dumb to whittle down the warnings to one per flop, but why are there 5 times the number necessary to pair each flop with each equivalent flop? It would be really nice to have a way to tell the synthesis not to produce this particular type of warning (or other types you've already seen and don't want to see again on the next build).Article: 78747
>> >> Has someone managed to program these devices from the FPGA withou using >> > NIOS? >> > >> > hm whats the problem? >> > >> Don't know if it's a problem. Just havn't done it till now and didn't find > any documentation >> about it from Altera. >> > > Menu: File->Convert Programming File > select .JIC > select your serial device > select your fpga > add .sof > convert > start programmer > add .JIC > program > > That should be it! when it works :) > Antti, you misunderstood me. I was asking about programming it FROM the FPGA. You know this ASMI stuff. MartinArticle: 78748
"Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag news:I3MNd.33985$2e4.26109@news.chello.at... > >> >> Has someone managed to program these devices from the FPGA withou using > >> > NIOS? > Antti, > > you misunderstood me. I was asking about programming it FROM the FPGA. You know this > ASMI stuff. > > Martin sorry I am bit off today catched some cold, hope it doesnt cathc over newsgroups.. I bet you get no replies regarding the ASMI stuff. I looked into a little a long time but havent actually done anything - from simple reason I still dont have any of your nice cyclone boards on my desk :) The acex board I have, I would like to give it away.. It should be possible but you might have to dig into library sources, etc. etc.. AnttiArticle: 78749
In the past I have built large RPMs that incurred warnings that took minutes to generate and scroll through per run. In the C++ compiler world we have flexible mechanisms like "#pragma warn" that can suppress specific warnings (possibly in selected areas) or even promote certain warnings to errors. A similar mechanism might be of use here. Jan Gray
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