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Why do you want to use distributed RAM, when you can get a ready-made high-performance FIFO in each BlockRAM? The timing is guaranteed for up to 500 MHz clocks, even asynchronous ones. What is it you are really after? Peter Alfke (member of the V4 FIFO design team) Ram wrote: > Hi, I'm looking for Timing info on an Asynchronous FIFO built using Distributed RAM on Virtex4. the part # we are using is : LX100-10, package FF1513. Xilinx publishes the FIFO timing info for Asynchronous FIFOs using Block RAM, but not distributed RAM. Specifically, I'd like to know the timing of all the FIFO signals (FULL/EMPTY, ALMOST_FYLL/ALMOST_EMPTY and other FIFO status signals). If someone could shed some light on where I might find this info, I'd really appreciate it.Article: 78851
> correct: systemace is a PicoBlaze based sort of SVF player > if you look at the ChipScope manual then you see partial listing of the > PicoBlaze > code as example how to use ChipScope load mnenmonics :) > > so the .ELF file (if that is for PowerPC ) will be converted to SVF that > uses > the PowerPC JTAG and it is "played" after the FPGA bitstream is loaded > so yes it kind similar of how it is done by XMD > > to bad the .ACE format is closed information if there is trouble then all > Xilinx users are STUCK. doesnt work and end of story. > > hm in your case I still wonder what the problem is > > you have v2pro and PPC based design with OPB Sysace right? > try this, create a small sysace test - if I find sources of my > system ace image loader you can use that, or maybe you have > a copy it was downloadable before I had to refromat openchip webserver > > so compile the program into BRAMs! > in XPS update bitstream or do it with impact so you will have > download.bit that contains the fpga and ppc code, > then IMPORTANT create ACE from this bitstream > do not add any elf to the ACE !!! the program code is .BIT ! > copy to CF card, and configure from the CF > > now the systemace SHOULD really work. > > if you still have trouble then open a gazilion of webaces :) > > Antti Antti, Thanks for the reply. This information applies to a V2Pro UltraController product and not to a V4. I make a special test case where I stripped pretty much everything in the deisng except the opb_sysace, and some gpio to toggle some led's and some uart support for stdout. I got some code to fit entirely within the brams and loaded it into the compact flash without any elf file stuff. When I boot via the CF, the status led goes green with no lit error led. After it returns from the XSysAce_IdentifyCF routine, the Signature field is 848A which appears correct, but the NumCylinders is also 848A. The registers before rouitne is called are cf dword 0 = 00000001 cf dword 1 = 00150392 cf dword 2 = 00000000 cf dword 3 = 00000CED cf dword 4 = 00000000 cf dword 5 = 100C0200 cf dword 6 = 00000802 cf dword 7 = 000000B3 The registers after XSysAce_IdentifyCF called cf dword 0 = 00000001 cf dword 1 = 003502B2 cf dword 2 = 00000000 cf dword 3 = 00000CED cf dword 4 = 00000000 cf dword 5 = 100C0200 cf dword 6 = 00000802 cf dword 7 = 000000B3 It looks like the reads of the buffer are not incrementing the FIFO that would cause the IdentifyMemCard command to end. What bothers me is that I appear to be able to read the other registers OK. I guess I might have to open a web case, wait for EDK6.3i to arrive, buy Chipscope or borrow a scope, or apply a blow torch to the Memec SysAce card:,) Usually Memec has pretty good reference designs, but this one did not have an MPU interface one for the standalone sysace module. Of course their baseline reference had a bunch of deprecated cores I ended up converting to EDK6.2 sp3. Do you think sysace is going away to be replaced by the platform flash stuff? I'm wondering if I should be researching a more valuable target. -Thanks again, -NewmanArticle: 78852
Hi all, I am a student, and I was trying to convert a .vho file produced by Xilinx Core Generator to a .vhd file so that I can make a standard VHDL project, which I can run in ModelSim Simulator. Can anybody comment/advise on whats the best way to do it? I probably would need to include some Xilinxcore libraries, but I am not too sure.Also, the translate on and translate off things, does that help while simulating?? Thanks, SourabhArticle: 78853
a vho file is already vhdl as you would find if you looked at it. Its just a vhdl representation of the logic which has been produced by your synthesis tool and is meant for simulation so that you can simulate the behavior of your design.Article: 78854
"Bo" <bo@cephus.com> schrieb im Newsbeitrag news:9u8Od.2834$2V1.1897@fe40.usenetserver.com... > We had similar problems in trying to load an ACE file from CF--but Only if > the ACE file was NOT in the root directory. Turns out the issue is that a > Windows 2000/XP formatted CF will NOT work. You must use mkdosfs.exe to > format the CF. After that, pretty much it started acting as expected. This > may or may not be your particular issue. > > Good luck, > > Paul hm I think W2k FAT16 formatted CF actually works, at least it worked for me, anyway I am having trouble with V4LX25-ES using a CF card that DID work on V2Pro board. The sector read commands get error, sometimes after 1 Ok sector sometimes up to 10 sectors are read OK. The CF has not been reformatted and the file I am reading (uclinux image) has not been overwritten since the time it worked on V2Pro so I dont think the formatting is the issue but thanks for the hint, I have had also problems with ACE not in root dir, so that issue DOES exist too in some cases AnttiArticle: 78855
"newman5382" <newman5382@yahoo.com> schrieb im Newsbeitrag news:oShOd.51114$JF2.33907@tornado.tampabay.rr.com... > > I guess I might have to open a web case, wait for EDK6.3i to arrive, buy > Chipscope or borrow a scope, or apply a blow torch to the Memec SysAce > card:,) Usually Memec has pretty good reference designs, but this one did > not have an MPU interface one for the standalone sysace module. Of course > their baseline reference had a bunch of deprecated cores I ended up > converting to EDK6.2 sp3. Do you think sysace is going away to be replaced > by the platform flash stuff? I'm wondering if I should be researching a > more valuable target. > > -Thanks again, > > -Newman Q: What Memec Board are you using? Q: You can use ChipScope Eval version, but well that may or may not help, try bugging memec-xilinx too A: Hm, my personal view is that SystemACE should be considered not recommended for new designs. The SystemACE MP is already discontinued SystemACE SC is availabe but hey that only a Virtex-V50 bitstream + docu! The SystemACE chip - HUUGE space requirments on PCB, etc. I have a project pushed onto my project stack: universal configuration controller - support all type of FPGA mixed chains multiply chains different removable media, etc.. the MMC card FPGA configuration IP core was developed to be used in the "universal config controller". It takes only 21 PLD macrocells to boot Xilinx FPGA in Master serial mode from MMC card (approx 55 cells for SD card). AnttiArticle: 78856
Hi Kolja ASAIK you are a person who should know what has been tested on the micromodule (at least what has been tested internally by Tranz Electronics). As the micro module has trenz@fpga.de in the toplayer and fgpa.de domain belongs to you :) So from what you just said its weird and surprising, if I am understanding you correctly a commercial hardware product from Trenz has not been tested with USB IP Endpoint IP core from Trenz? And only tested with free IP Core from ASICS World Services that has been made available for free out of courtesy of Rudolf Usselman? On the Trenz website Trenz USB IP Core is still listed as current product - I wonder why it has not been tested on the micromodule. Well the world still has its small surprises ;) The USB 2.0 HS core would not be as easy to setup as the 1.1 core, just a friendly hint. The 1.1 core ASICS it sure is easy to setup, I have tested it on some Memec board with P160 Comm 1 module. Hm I was about to test the ASICS 1.1 core on micromodule, but hence its already done by Trenz then I wonder if that design will be made publicly available? It is based on free IP Core so I seen no reason why it should not be included in the demo package supplied with S3 micromodule specially as the current demo and ipcores are published under GPL license AnttiArticle: 78857
Hi Antti, Can you share those tricks with the group? -sg Antti Lukats wrote: > it can be done with v2pro, there are some tricks though > > I have tested this as a working solution with real sata chips on memec VP20 board, sata cable to SMA and OOB sequence all passed ok > > AnttiArticle: 78858
"sg" <sgodey@gmail.com> schrieb im Newsbeitrag news:1107939047.041185.187330@f14g2000cwb.googlegroups.com... > Hi Antti, > > Can you share those tricks with the group? I think I have done that sooome time ago, but I had to reformat the HD on openchip server so the files are not accessible. basically there are 2 possibilities 1) small external circuitry, requires 1 regular IO pin from FPGA this is Xilinx solution, please contact Xilinx for details. 2) my solution, OK to use for development at least, no external hardware, tested with real V2Pro and real SATA chip so my trick is that use 2 MGT RX from one and TX from the other. and using POWERDOWN to turn of the transmitter as the powerdon on-off delay are not equal the SATA OOB transmit timing has the pre-adjusted to get the required chirp timing in the output stream. In the receive section there a specially developed for MGT squelch detector, thats a bit magic too as the MGT receiver when not seing proper inpout (eg during SATA OOB) has weird repeat noise pattern (repeating over 4 bits) this has to cancelled in order to properly and reliably detect the incomign OOB detailed enough? AnttiArticle: 78859
"Antti Lukats" <antti@openchip.org> wrote in message news:cucgqp$rbo$00$1@news.t-online.com... > "newman5382" <newman5382@yahoo.com> schrieb im Newsbeitrag > news:oShOd.51114$JF2.33907@tornado.tampabay.rr.com... >> > >> I guess I might have to open a web case, wait for EDK6.3i to arrive, buy >> Chipscope or borrow a scope, or apply a blow torch to the Memec SysAce >> card:,) Usually Memec has pretty good reference designs, but this one >> did >> not have an MPU interface one for the standalone sysace module. Of >> course >> their baseline reference had a bunch of deprecated cores I ended up >> converting to EDK6.2 sp3. Do you think sysace is going away to be > replaced >> by the platform flash stuff? I'm wondering if I should be researching a >> more valuable target. >> >> -Thanks again, >> >> -Newman > > Q: What Memec Board are you using? I'm using a DS-BD-2VPxLC Revision 1 UltraController V2Pro System Ace Module DS-BD-SAM Rev 1 By the way, the separate interface connector they tell you to buy from another company is inadequate. The loose fit of the pins makes for intermittant contact. I ended up nibbling the ultracontroller connector housing away to make a direct connection with the ACE board. > Q: You can use ChipScope Eval version, but well that may or may not help, > try bugging memec-xilinx too I tried the ChipScope eval version, and burnt through the eval period. I'm thinking that I should buy one, I'm just waiting for a pressing need to get one, cause that starts the clock ticking on the time license period? It was never clear to me if Chipscope was a timebased license, or whether you got updates for a year to the different ISE versions, or whether you have to purchase a new license for every ISE update. On another note, I tried changing the IO power straps to 2.5 volts with 2.5 LVCMOS I/O with a similar change to the SysAce board. It appears that I can no longer achieve an MPU lock, perhaps a write problem. I was thinking of simulating the design now that all the code is contained in BRAM, but since I don't have a model of the XCCACE chip, and maybe its some type of interface compatibility level thing, I'm not sure it would be worth it. Thanks for your consideration, -Newman > > A: Hm, my personal view is that SystemACE should be considered not > recommended for new designs. The SystemACE MP is already discontinued > SystemACE SC is availabe but hey that only a Virtex-V50 bitstream + docu! > The SystemACE chip - HUUGE space requirments on PCB, etc. > > I have a project pushed onto my project stack: universal configuration > controller - support all type of FPGA mixed chains multiply chains > different > removable media, etc.. the MMC card FPGA configuration IP core was > developed > to be used in the "universal config controller". It takes only 21 PLD > macrocells to boot Xilinx FPGA in Master serial mode from MMC card (approx > 55 cells for SD card). > > Antti > > > > > > > > > > >Article: 78860
"John_H" <johnhandwork@mail.com> wrote in message news:<DH5Od.6$iV.232@news-west.eli.net>... > TIMEGRP MyInputs OFFSET = IN 2 ns VALID 7 ns BEFORE MyClk; > > "Thomas" <tb_news@arcor.de> wrote in message > news:9149a016.0502080528.7bee2cad@posting.google.com... > > Hi all, > > > > I have a signal that is valid 2 ns before the active clock edge > > and stays valid until 5 ns after the active clock edge. > > Is there a possibilty to put this constraint into > > the ucf file? > > > > any hints are welcome > > > > Thomas thanks although I cannot meet the spec, up to now :( ThomasArticle: 78861
Hello, This is a beginner question. I have EDK 6.3 installed in a linux system. I dont know how to start the EDK/XPS and begin with Base system builder. can anybody help me . thank youArticle: 78862
>> Yes, I will go with the SDRAM. Do you have an idea what chips are used these days. >> I've found Micron MT48LC4M16A2 could be a choice. > > Yes, looks good to me. If you still have spare IO, routing the address lines for > the superior model might be interesting. Maybe there is no more line to route actually, > I didn't check It's almost the same pinout for up to 64MByte (only one additional address line). >> However, as it looks like that I will use >> the Cyclone I only need one switched power supply (1.5V). > > May I ask why ? > > The EP1C3 has 2910 L.E., 1 PLL and 60kbits of ram. > The XC3S200 has 4320 L.C., 4 DCM/DLL, 216kbits of ram and 12 dedicated multipliers > A little correction: The Spartan-3 has 3,840 LC/Es (multiply the Slices by two and you get the LUT count). Yes you're right, S3-200 is larger, has more memory (but less memory blocks 12 vs. 13) and multipliers. However, my main application for this board, JOP, can be clocked higher in the Cyclone than in the Spartan-3 (101MHz vs 83MHz, both fastest speed grades). The S3-200 is more expensive than the EP1C3. However, both are large enough for a CPU with some peripherals. That's the main application, in my opinion, for this board. And another reason: There are many Xilinx boards (and also cheap one) available, but not so many for Cyclones. This board would be very similar to Koljas Micromodule. >>>If there is a spare centimeter square, adding an unpopulated space for another >>>XTAL maybe. >> Why? You can use the internal PLL. And I'm not using an XTAL, but an integrated osci. >> If you really need a different frequency than you can change the osci yourself. > > First yes sorry I always write XTAL while I mean a complete osc ... ;) > Why : It's not big and when you have a specific frequency for a screen / uart / ... generating > it with the PLL is sometimes annoying ... Yes, a good idea! I will add the spare pads on the back side of the pcb. That does not cost pcb place resources. >>>Other remarks : Having a few I/Os routed as differential pair to the connector could be nice >> >> Do you mean LVDS standard with the termination resistor network? > > Yes, that what I meant. Don't put the resitors by default, just route them as if they were > differential. You mean same lenghth, constant distance. However, there will be almost no routing from the FPGA to the connector. I'll expect only a few mm from pin to connector. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 78863
Hi, maybe someone can give her/his opinion concerning the following question: Thank you in advance. I have a FIFO template with one write clock and one read clock. These clocks are full asynchronous to each other. Apart from that I have an asynchronous reset port in the FIFO. My question: Let us assume that I sychronize the asynchronous reset coming from FPGA input pin in a flip flop chain to synchronize it to the write clock and in a second flip flop chain to synchronize it to the read clock. Which synchronized reset do I have to use to reset the FIFO in a safe manner ? Rgds AndréArticle: 78864
> Is there some trick to do a sort of "make clean" in a project > directory? So it deletes all created files during synthesis? I have a little batch file for this job. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/ clean.bat: del *.cnf del *.rpt rem del *.sof rem del *.pof del *.ttf rem del *.jbc del *.hif del *.mmf del *.ndb del *.hex del *.fit del *.snf del *.idx del *.pin del *.jam del *.db? del *.scr del *.sum del *.xdb del *.edf del *.edo del *.log del *.his del *.vmo rem this is for quartus del *.ini del *.fsf del *.eqn rem del *.esf del *.psf del *.qws del *.ssf del *.fsf del *.qws del *.bak del *.xrf del *.done del /s db rd dbArticle: 78865
You normally get a PS2 (keyboard/mouse) power breakout cable with these. A bit of a pain on most laptops as many don't have PS2 now. You can buy a DC plug in brick separately. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "adrian" <adrian.mora@terra.es> wrote in message news:FpNNd.200108$A7.292999@telenews.teleline.es... > hi everyone, > > simple question... > IMPACT doesn't recognize my xilinx parallel cable IV when downloading > projects to the board. > I have read in some articles that a power supply is necessary to power up > the cable, but there is no power supply or adapter in the box where the > cable came. > Do I have to buy a separate adapter or is there any other way of powering > the cable?? > What kind of adapter do I need?? > > Thanks in advance. > >Article: 78866
it seems that it trying to generate libraries and write it on ppc_405/lib but it fails..please check folder permissions...to allow the users to write something in it...make it sure you have admin rights for the system...you can check it through folder ..options..security...allow users...full control...then try again... all the best,.... sudheerArticle: 78867
Dear Kolja,
the compilation of the kernel module windrv6.ko under kernel 2.6.x using
the distribution SuSE 9.2 fails.
Here are my steps to get it work:
a) download evaluation version of Windriver.tgz from www.jungo.com,
extract to <some-path>/WinDriver
b) install kernel-sources, cd /usr/src/linux ; make cloneconfig; make
prepare
c) cd <some-path>/WinDriver/redist
d) ./configure
e) edit makefile
-change KERNEL_DIR: KERNEL_DIR = /usr/src/linux/
-modify CFLAGS:
i) delete all -I flags
ii) add -I/usr/src/linux/include
iii) add -I/usr/src/linux/include/asm-i386/mach-default/
f) make
Maybe you should add this to the description of Hein Roehrig.
I have reopened the xilinx case 549715, too.
Joerg
> Hein Roehrig wrote a detailed description on how to run Impact with
> parallel cable on a linux kernel of the 2.6 series.
>
> I can be found on our server:
> http://www.fpga.de/tiki/tiki-index.php?page=XilinxSoftwareLinux
>
> I also asked philip freidin to upload it to www.fpga-faq.com.
>
> I Hope this helps,
>
> Kolja Sulimma
Article: 78868Hi can I get free(open source) IP cores for USB 1.1 or 2.0 and firewire modules. if not where can I get them for low cost. any one has an idea...suggestions... thanks a lot..Article: 78869
I have been searching for a good laptop for fpga design. My research (??) indicates that AMD Athlon 64 chips perform faster than P4 chips on average. Of course it depends on which P4, and which AMD, but for the same cost it seems that AMD wins. Can anyone tell me if this is correct? Based on this assumption, I have only found 2 Brand Name AMD based laptops. The HP - Compaq design based - R3000Z series, and the Acer Ferrari. There are also some sites that do custom laptops, but I don't really like that idea at all. I am also looking for a light to medium weight laptop, nothing heavy like some of the big Toshibas. Any advice or experience in this area would be welcome, Thank you, nachumArticle: 78870
I have read that quartus is optimized to take advantage of the SSE instruction sets in Linux, yet not in Windows. Can I assume from this that quartus will run faster on Linux? I am buying a new computer, and I want to decide what OS to run, and if Linux will be faster for FPGA design, than that is what I will run. Thanx again, nachumArticle: 78871
Hi together. I'm new with FPGA and I'm trying to implement a logic circiut which collects special data from some IO-pins and transfers it to the boards ram. Can anybody tell me how to interface the ram? Do I have to write my own little memory controller and access the ram via the specified pins or are there special constructs for this reason. I use a Memec Spartan IIELC Development Board with 32MB SDRAM onboard. My design is done in verilog. Thanks an advance for every piece of advice. Best regards, Michael PieberArticle: 78872
I have an ACER 1502, almost an earlier model of the Ferrari. It is very quick. The only thing that lets it down is the disk speed but this is a common issue for power users with laptops. There are faster laptop drives so it is worth finding out disk spec on any given laptop. I have done benchmarking in the past on Intel v AMD and found one faster on some parts of the flow whilst the other does better on the other bits. Overall when I ran these tests the factors balanced out and ther was not much difference. These results will vary as design but it would be interesting to know how the latest batch offerings perform. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "nachum" <nachumk@gmail.com> wrote in message news:1107956041.878727.33690@g14g2000cwa.googlegroups.com... > I have been searching for a good laptop for fpga design. My research > (??) indicates that AMD Athlon 64 chips perform faster than P4 chips on > average. Of course it depends on which P4, and which AMD, but for the > same cost it seems that AMD wins. > > Can anyone tell me if this is correct? > > Based on this assumption, I have only found 2 Brand Name AMD based > laptops. The HP - Compaq design based - R3000Z series, and the Acer > Ferrari. There are also some sites that do custom laptops, but I don't > really like that idea at all. I am also looking for a light to medium > weight laptop, nothing heavy like some of the big Toshibas. > > Any advice or experience in this area would be welcome, > > Thank you, > nachum >Article: 78873
Hi, I'm working on a design that will require external memory, and I'm trying to find some learning resources for Xilinx DDR SDRAM memory controllers. I don't have much VHDL/FPGA design experience and all the resources I can find assume that you implicitly know how to use a memory controller. The Xilinx models from their web site just unzip to a whole bunch of vhdl files and their documentation is not user oriented - it's an explanation of how their controller is implemented (I don't care!). The memory controller performance/specification isn't important to me right now, but without being able to simulate a controller I can't proceed further with my circuit design. I'm using ISE and ModelSim. Do I need to go down the Denali route and purchase a memory model then lean on their technical support? Or should I just give up and get a consultant to help? Andy.Article: 78874
Opencores.com has a couple USB 1.1 and 2.0 projects for free. It doesn't look like they have any firewire projects though.
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