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Kolja, >> CPU design. Here is the suggested part list: >> >> FPGA: Cyclone EP1C3 or Spartan XC3S200 >> 256Kx16 15ns SRAM >> 2 MBit serial Flash >> 3.3V linear regulation >> switching regulator for the core voltage >> 20MHz clock to the PLL input > [..] >> What do you guys think about this idea? Does it make sense to build a another FPGA board? > > What you describe is essentially our Micromodule minus USB plus SRAM. > http://www.trenz-electronic.de/prod/proden18.htm > > If you can live with our form factor we could collaborate on a version with sram instead of usb. > I think the Micromodule is a very nice design in it's version as it is (with USB). If you only add SRAM you still need a base board. > For a cluster you can build a stack of these boards. Stacking is a nice idea. I also thought about stacking my Cyclone modules when I've too many of them laying around ;-) > > However I doubt that it makes sense to have boards that are so similar. > I think I will go with a Cyclone. So our two boards are not so similar. MartinArticle: 78826
"newman5382" <newman5382@yahoo.com> schrieb im Newsbeitrag news:655Od.15899$qB6.3561@tornado.tampabay.rr.com... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:cuakor$itp$05$1@news.t-online.com... > > "newman5382" <newman5382@yahoo.com> schrieb im Newsbeitrag > > news:1t4Od.15793$qB6.2868@tornado.tampabay.rr.com... > >> > >> "Antti Lukats" <antti@openchip.org> wrote in message > >> news:cua695$on8$01$1@news.t-online.com... > >> > Hi > >> > > >> > has any one some hints or tips how to get an Virtex4 LX25-ES configured > >> > from > >> > SystemACE? > >> > we can configure from iMpact and if we load the uclinux kernel from XMD > > it > >> > works too. > >> > but now when I try to load the uclinux image from CompactFlash then > > there > >> > are problems > >> > if the FPGA is configured by impact then there will always be random > >> > sector > >> > read errors > >> > when attempting to load the image.bin from CompactFlash. On ML300 I had > > to > >> > load from > >> > CF in order to access the CF, but with V4LX the FPGA config from > >> > CompactFlash doesnt > >> > seem to work, the status led blinks once and then the error led goes > >> > on. > > I > >> > assume it is the TDO > >> > >> I get this symptom with a V2Pro board. When I load the compact flash > >> with > >> the bit, bmm, and elf file. When I just load the bit file into the > > compact > > how? > > you mean when the bit file in the ACE file containts both fgpga bitstream > > and elf data? > > there is now way to directly load the Cf with elf and bmm, or > > > > well with V2Pro boards I havent had problems, except that I wasnt able > > to access the OPB_sysace unless the bitstream was loaded from CF > > as well, but this was maybe becuase I did not chanhe the systemace > > init mode to disable the auto load > > > > I generate the ace file via impact > - Prepare Configuration Files > - System ACE File > - System ACE CF Novice > - 128 Mbits Reserve Space > - etc > - add file download.bit, system.bmm, executable.elf ahok yes that proper, it is adds the bit+elf as ACE same as you can create a BIT with FPGAbit+elf > I read somewhere that the sysace is like some type of JTAG player, I > assumed that the elf would get loaded somehow like it does with xmd, except > without xmd. Perhaps I am wrong, and that is why it does not work for me. > Also, when I try to read a sector via the MPU interface, it goes busy and > never goes ready again (i.e. Status Reg bit 8 goes low and stays low even > after I read out a sector of data.) The sector reads 256 16 bit words of > the same value. When I use XSysAce_IdentifyCF, I get the expected > Signature, but all the other fields come back with the Signature value also, > and bit 8 of the status reg never goes busy. correct: systemace is a PicoBlaze based sort of SVF player if you look at the ChipScope manual then you see partial listing of the PicoBlaze code as example how to use ChipScope load mnenmonics :) so the .ELF file (if that is for PowerPC ) will be converted to SVF that uses the PowerPC JTAG and it is "played" after the FPGA bitstream is loaded so yes it kind similar of how it is done by XMD to bad the .ACE format is closed information if there is trouble then all Xilinx users are STUCK. doesnt work and end of story. hm in your case I still wonder what the problem is you have v2pro and PPC based design with OPB Sysace right? try this, create a small sysace test - if I find sources of my system ace image loader you can use that, or maybe you have a copy it was downloadable before I had to refromat openchip webserver so compile the program into BRAMs! in XPS update bitstream or do it with impact so you will have download.bit that contains the fpga and ppc code, then IMPORTANT create ACE from this bitstream do not add any elf to the ACE !!! the program code is .BIT ! copy to CF card, and configure from the CF now the systemace SHOULD really work. if you still have trouble then open a gazilion of webaces :) AnttiArticle: 78827
>> However, SRAM is way much simpler to handle. I think SDRAM is a pain. > > SDRAM is not that hard and having a lot more capacity is a big plus IMHO, that > worth the extra work. Yes, I will go with the SDRAM. Do you have an idea what chips are used these days. I've found Micron MT48LC4M16A2 could be a choice. >> The 3.3V linear regulation is only for the IO. The core voltage gets a switching >> regulator. If you are using this module in a 3.3V SimmStick bus you can go >> without the linear regulation on board (will be a sloder jumper) > > Have a look at > http://focus.ti.com/lit/ds/symlink/tps75003.pdf > > Really nice little chip ;) Nice, but still many external components. However, as it looks like that I will use the Cyclone I only need one switched power supply (1.5V). >>>> 20MHz clock to the PLL input > > If there is a spare centimeter square, adding an unpopulated space for another > XTAL maybe. Why? You can use the internal PLL. And I'm not using an XTAL, but an integrated osci. If you really need a different frequency than you can change the osci yourself. > Other remarks : Having a few I/Os routed as differential pair to the connector could be nice Do you mean LVDS standard with the termination resistor network? MartinArticle: 78828
TIMEGRP MyInputs OFFSET = IN 2 ns VALID 7 ns BEFORE MyClk; "Thomas" <tb_news@arcor.de> wrote in message news:9149a016.0502080528.7bee2cad@posting.google.com... > Hi all, > > I have a signal that is valid 2 ns before the active clock edge > and stays valid until 5 ns after the active clock edge. > Is there a possibilty to put this constraint into > the ucf file? > > any hints are welcome > > ThomasArticle: 78829
> Martin, > > If you do decide to build a new proto board make sure you've got some form of > securely mounting it. If you go with a SimmStick this is taken care of, but I > had problems mounting your Cyclone JOP boards for prototyping. I didn't > have time to design/build a motherboard to plug the modules into to get access > to the connectors so had to build a complicated jig to hold them securely. He he. You do not need a real motherboard. Just single row connectors on a breadboard and go (or the expensive version of this that I provide: Simpexp) MartinArticle: 78830
"Rudolf Usselmann" <russelmann@hotmail.com> schrieb im Newsbeitrag news:cu9leb$rv5$1@nobel.pacific.net.sg... > > > Thanks to the excellent support from Xilinx this problem has > been solved !!! > Turns out the Memec-Insight board had a 100 ohm (yes 100 !) > pull-up on the TDO line. That basically broke everything. > > Removing the pullup, got rin of the CRC bit errors and chip- > scope appears to work now as well. > > Thanks a lot for going the extra mile, to all the good folks > at Xilinx ! > > Kind Regards, > rudi can you download with ChipScope as well after removing the pull-up ? we can use ChipScope but can not download with it, well I have not yet removed that pullup resistor AnttiArticle: 78831
it can be done with v2pro, there are some tricks though I have tested this as a working solution with real sata chips on memec VP20 board, sata cable to SMA and OOB sequence all passed ok AnttiArticle: 78832
dear all
I have a question about calculating a BRAM utilzation.
I am using XC2VP30 and data sheet says
-----------------------------
Block SelectRAM+
-----------------------------
18kb Blocks | Max. BRAM (kb)
-----------------------------
136 | 2448
-----------------------------
and in my MHS file, BRAM is specified as
-----------------------------
...
BEGIN lmb_bram_if_cntlr # 64 kb
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_BASEADDR = 0x0000ffff
BUS_INTERFACE SLMB = ilmb
...
END
BEGIN lmb_bram_if_cntlr # 64 kb
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_BASEADDR = 0x0000ffff
BUS_INTERFACE SLMB = dlmb
...
END
-----------------------------
as far as I understand, the BRAM utilization should be
(64 + 64 ) kb / 2448 kb = 5.3 %
But log file says
-----------------------------
Device utilization summary
Number of Block RAMs : 32 out of 136 23%
...
-----------------------------
I understand this as a NUMBER of BLOCKS out of total NUMBER of BLOCKS.
Anyway, the memory utilization is very low.
Questions are
- Is my understanding correct ?
- How can we utilize more efficiently ?
Thankyou and thankyou for previous Q & A too.
Article: 78833"Jack" <JEmoderatz@yahoo.com> schrieb im Newsbeitrag news:1107883607.877297.20670@z14g2000cwz.googlegroups.com... > dear all > > I have a question about calculating a BRAM utilzation. > > I am using XC2VP30 and data sheet says > > ----------------------------- > Block SelectRAM+ > ----------------------------- > 18kb Blocks | Max. BRAM (kb) > ----------------------------- > 136 | 2448 > ----------------------------- Kbits !! > > and in my MHS file, BRAM is specified as > > ----------------------------- > ... > BEGIN lmb_bram_if_cntlr # 64 kb > PARAMETER C_BASEADDR = 0x00000000 > PARAMETER C_BASEADDR = 0x0000ffff > BUS_INTERFACE SLMB = ilmb > ... > END > > BEGIN lmb_bram_if_cntlr # 64 kb > PARAMETER C_BASEADDR = 0x00000000 > PARAMETER C_BASEADDR = 0x0000ffff > BUS_INTERFACE SLMB = dlmb > ... > END > ----------------------------- > > as far as I understand, the BRAM utilization should be > > (64 + 64 ) kb / 2448 kb = 5.3 % NO 64 KByte ! the ilmb and dlmb use A and B ports of the same 64KByte block > Number of Block RAMs : 32 out of 136 23% correct 32 brams, each 2KB = 64Kb when counting bits each bram has 18bits so 2 bits are wasted, so the bit percent will differ a little AnttiArticle: 78834
Each BRAM has 18kbit of memory 136 BRAM has 136*18kbit = 2448 kbit (not kbyte) 64 kbyte of memory is requiring 32 BRAMs (each BRAM has 2 kbyte of memory) So 64 kbyte of memory is requiring 32 BRAMs which is 32/136 = 23% of the available BRAMs Göran Jack wrote: > dear all > > I have a question about calculating a BRAM utilzation. > > I am using XC2VP30 and data sheet says > > ----------------------------- > Block SelectRAM+ > ----------------------------- > 18kb Blocks | Max. BRAM (kb) > ----------------------------- > 136 | 2448 > ----------------------------- > > and in my MHS file, BRAM is specified as > > ----------------------------- > ... > BEGIN lmb_bram_if_cntlr # 64 kb > PARAMETER C_BASEADDR = 0x00000000 > PARAMETER C_BASEADDR = 0x0000ffff > BUS_INTERFACE SLMB = ilmb > ... > END > > BEGIN lmb_bram_if_cntlr # 64 kb > PARAMETER C_BASEADDR = 0x00000000 > PARAMETER C_BASEADDR = 0x0000ffff > BUS_INTERFACE SLMB = dlmb > ... > END > ----------------------------- > > as far as I understand, the BRAM utilization should be > > (64 + 64 ) kb / 2448 kb = 5.3 % > > But log file says > > ----------------------------- > Device utilization summary > > Number of Block RAMs : 32 out of 136 23% > ... > ----------------------------- > > I understand this as a NUMBER of BLOCKS out of total NUMBER of BLOCKS. > Anyway, the memory utilization is very low. > > Questions are > - Is my understanding correct ? > - How can we utilize more efficiently ? > > Thankyou and thankyou for previous Q & A too. >Article: 78835
Martin Schoeberl wrote: >>>However, SRAM is way much simpler to handle. I think SDRAM is a pain. >> >>SDRAM is not that hard and having a lot more capacity is a big plus IMHO, that >>worth the extra work. > > > Yes, I will go with the SDRAM. Do you have an idea what chips are used these days. > I've found Micron MT48LC4M16A2 could be a choice. Yes, looks good to me. If you still have spare IO, routing the address lines for the superior model might be interesting. Maybe there is no more line to route actually, I didn't check > However, as it looks like that I will use > the Cyclone I only need one switched power supply (1.5V). May I ask why ? The EP1C3 has 2910 L.E., 1 PLL and 60kbits of ram. The XC3S200 has 4320 L.C., 4 DCM/DLL, 216kbits of ram and 12 dedicated multipliers (Note that it's _not_ a A vs X issue ! Theses chips are just not of the same generation ...) >>>>> 20MHz clock to the PLL input >> >>If there is a spare centimeter square, adding an unpopulated space for another >>XTAL maybe. > > Why? You can use the internal PLL. And I'm not using an XTAL, but an integrated osci. > If you really need a different frequency than you can change the osci yourself. First yes sorry I always write XTAL while I mean a complete osc ... ;) Why : It's not big and when you have a specific frequency for a screen / uart / ... generating it with the PLL is sometimes annoying ... >>Other remarks : Having a few I/Os routed as differential pair to the connector could be nice > > Do you mean LVDS standard with the termination resistor network? Yes, that what I meant. Don't put the resitors by default, just route them as if they were differential. SylvainArticle: 78836
indeed, i did it like that afterwards and i have both (with and without the wizard) working heheh ... thanx for the advice ... "Moti" <moti@terasync.net> wrote in message news:1107691152.730676.107730@o13g2000cwo.googlegroups.com... > Hi Peter, > > I think that the easy way for you to update your peripheral > functionally is to re-import your peripheral(using the wizard) after > updating your vhdl files (user_logic.vhd and the peripheral_name??.vhd) > that way (i believe..) it will work just fine. > > Regards, Moti. >Article: 78837
idd, that was one of the reasons ... i also started to do everything in a different editor and just compile in EDK ... thanx for the information ... "Duane Clark" <junkmail@junkmail.com> wrote in message news:cu33lo0lak@news4.newsguy.com... > Peter Soerensen wrote: > > Hi, > > > > I have created a periperal IP device using the "Create/Import.." > > wizard of the EDK 6.3. The IP has 4 32 bit registers. I have been > > able to connect the IP as a slave to the OPB and write a small > > program that can write and read these registers. However when I make > > changes in the vhdl files of the IP it seems to have no effect. I > > tried reading one of the four registers return a constant value but > > it still returns the value I previously read .. Do I have do > > soemthing to make the EDK update the IP? > > > > First, let me say that I am not using the EDK GUI except to create an > initial project. Thereafter, I make all changes with a normal text > editor, and compile by executing make commands at the command line (on > Linux). So keep that in mind when reading my comments. > > I also noticed that when I made changes to one of the cores in my > project's pcores directory, that the changes were not automatically > compiled in. Eventually, I discovered somewhere in the EDK documentation > that you had to set a flag somewhere for that to happen (I don't > remember the flag, or where it was in the docs). Unfortunately, once I > set the flag, EDK insisted on recompiling the core every time, rather > than when a change had been made to the code. > > So instead I hand edited the makefiles. In system_incl.make, I added > lines that look like: > > MY_DDR_CLOCKS_IMPLN = implementation/my_ddr_clocks_wrapper.ngc > MY_DDR_CLOCKS_FILES = pcores/ddr_clocks_v1_00_a/hdl/vhdl/ddr_clocks.vhd \ > pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.mpd \ > pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.pao > > MY_DIMM_IMPLN = implementation/my_dimm_wrapper.ngc > MY_DIMM_FILES = pcores/wsoa_dimm_v1_00_a/hdl/vhdl/clock_gen.vhd \ > pcores/wsoa_dimm_v1_00_a/hdl/vhdl/command_statemachine.vhd \ > pcores/wsoa_dimm_v1_00_a/hdl/vhdl/coregen_comp_defs.vhd \ > ... > > MY_BITS_IMPLN = implementation/my_bits_wrapper.ngc > MY_BITS_FILES = pcores/plb_bits_v1_00_a/hdl/vhdl/bits_core.vhd \ > pcores/plb_bits_v1_00_a/hdl/vhdl/plb_ipif_ssp1.vhd \ > pcores/plb_bits_v1_00_a/hdl/vhdl/plb_bits.vhd \ > ... > > MY_WRAPPER_NGC_FILES = $(MY_DDR_CLOCKS_IMPLN) \ > $(MY_DIMM_IMPLN) $(MY_BITS_IMPLN) > > MY_DEVELOPMENT_FILES = $(MY_DDR_CLOCKS_FILES) \ > $(MY_DIMM_FILES) $(MY_BITS_FILES) > > Then in system.make, I have lines that look like: > > ################################################################# > # HARDWARE IMPLEMENTATION FLOW > ################################################################# > > $(MY_DDR_CLOCKS_IMPLN): $(MY_DDR_CLOCKS_FILES) > rm -f implementation/my_ddr_clocks_wrapper.ngc > rm -f implementation/cache/my_ddr_clocks_wrapper.ngc > > $(MY_DIMM_IMPLN): $(MY_DIMM_FILES) > rm -f implementation/my_dimm_wrapper.ngc > rm -f implementation/cache/my_dimm_wrapper.ngc > > $(MY_BITS_IMPLN): $(MY_BITS_FILES) > rm -f implementation/my_bits_wrapper.ngc > rm -f implementation/cache/my_bits_wrapper.ngc > > implementation/$(SYSTEM).bmm \ > $(CORE_WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ > $(MY_DEVELOPMENT_FILES) > @echo "****************************************************" > @echo "Creating system netlist for hardware specification.." > @echo "****************************************************" > platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE) > > A little extra effort, but well worth it in the end for me. > > -- > My real email is akamail.com@dclark (or something like that).Article: 78838
Antti Lukats wrote: > > to bad the .ACE format is closed information if there is trouble then all > Xilinx users are STUCK. doesnt work and end of story. > There is a utility SVF2ACE available from xilinx. One can use this to create an .ACE file most .SVF files. IMPACT can be used to generate an SVF. We have found it useful when debugging configuration issues to remove the bitstream and/or various other JTAG commands, from the SVF and test with a minimal ACE file to verify that that the JTAG chain is in intact, and will run at speed. We used this technique in various stages of a V2Pro design to discover first that we needed a pullup on TDO, and z few months later, that internal to our bitstream we had set up the PPC405 cores on the JTAG chain incorrectly, and at startup this problem was hosing JTAG. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 78839
I am trying to get the soft boot functionality working with vxWorks on an ML310 platform PPC405 platform. I have tried the following: adding "sysace=0(0,0):/vxWorks" to the default bootline, per the Xilinx sysSystemAce.c file. adding "sysace=0(0,0):cfgaddr" to the default bootline, per the Xilinx sysSystemAce.c file. adding "sysace=0(0,0):cfgaddr7" to the default bootline, per the Xilinx sysSystemAce.c file. I have also tried, #define INCLUDE_BOOT_FLASH so that XSYSACE_INSTALL_RESET_VEC is defined (again according to xilinx C file comments). All of my attempts yield the same result: OPB ERROR LED being lit and the system hanging. I CAN from the vxWorks shell, issue sysSystemAceJtagSetConfigAddr 1 followed by sysSystemAceJtagReboot() and the system will properly reconfigure FPGA and restart vxWorks as expected. What am I missing here? I know the underlying mechanisms to make the reboot are good, it's just that "reboot" and "Ctl-X" from the shell, cause OPB error and send the system into never land. Any ideas? Thanks, PaulArticle: 78840
We had similar problems in trying to load an ACE file from CF--but Only if the ACE file was NOT in the root directory. Turns out the issue is that a Windows 2000/XP formatted CF will NOT work. You must use mkdosfs.exe to format the CF. After that, pretty much it started acting as expected. This may or may not be your particular issue. Good luck, Paul <widding@birger.com> wrote in message news:1107886066.047123.120470@f14g2000cwb.googlegroups.com... > Antti Lukats wrote: >> >> to bad the .ACE format is closed information if there is trouble then > all >> Xilinx users are STUCK. doesnt work and end of story. >> > > There is a utility SVF2ACE available from xilinx. One can use this to > create an .ACE file most .SVF files. IMPACT can be used to generate an > SVF. We have found it useful when debugging configuration issues to > remove the bitstream and/or various other JTAG commands, from the SVF > and test with a minimal ACE file to verify that that the JTAG chain is > in intact, and will run at speed. > > We used this technique in various stages of a V2Pro design to discover > first that we needed a pullup on TDO, and z few months later, that > internal to our bitstream we had set up the PPC405 cores on the JTAG > chain incorrectly, and at startup this problem was hosing JTAG. > > > Regards, > Erik. > > --- > Erik Widding > President > Birger Engineering, Inc. > > (mail) 100 Boylston St #1070; Boston, MA 02116 > (voice) 617.695.9233 > (fax) 617.695.9234 > (web) http://www.birger.com >Article: 78841
> Hi all, > > I'm thinking about a new board for JOP (or MB, NIOS). The board should be > small and > cheap (below the S3 Starter Kit). It should only contain the absolute > necessary parts for a > CPU design. Here is the suggested part list: > > FPGA: Cyclone EP1C3 or Spartan XC3S200 > 256Kx16 15ns SRAM > 2 MBit serial Flash > 3.3V linear regulation > switching regulator for the core voltage > 20MHz clock to the PLL input > > I've not yet decided about a X or A device. > > A remaining question is about the form factor. I still think it makes > sense to build > the board as a module that can be integrated in a board with the > peripherals (similar > to the ACEX and Cyclone modules I've done). There are two 'standards' > available: > > 1.) SimmStick, where the boards are designed as the 'old' PC SIMMs (see > [1]). > > 2.) The 'Basic Stamp' design is a board in the form of an old 40-pin (or > less) DIL IC. > An example (from a Java processor competitor): [2] > > For a Java solution in an FPGA this board should beat the Systronix aJ100 > Java processor > modules (JStamp or JStick [3] - they have both form factors) in > performance and price. > One nice thing about the SimmStick is that there are plenty of I/O boards > already available > (see [4, 5, 6]). > It seems a relative 'old' design, but it's a bus and I can build my first > JOP cluster with those > boards ;-) > > What do you guys think about this idea? Does it make sense to build a > another FPGA board? > > [1] http://www.simmstick.com/ > [2] http://jstamp.systronix.com/jstamp_photos.htm > [3] http://www.jstik.com/ > [4] http://www.dontronics.com/dt.html > [5] http://www.hobbyengineering.com/SectionSS.html > [6] http://www.simmstick.com/simmstic1.htm > > Martin > ---------------------------------------------- > JOP - a Java Processor core for FPGAs: > http://www.jopdesign.com/ > I personally thought that the simmstick standard has way too few pins (30) for any serious work. That was the main reason for me to 'invent :-)' my own bus standard. The latest incarnation is called 'H-Storm' and can be found here: http://h-storm.tantos.homedns.org. I would suggest you to take a look. It has more pins (72) and thus much more versatile than the simmstick. It's already 3.3V powered so you can save the regulator. Even better: it has pins for 2.5 and 1.8V power as well, so you might not need to deal with power at all (not with the SpartanIII, the core power there is 1.2V). I'm in the process of building an FPGA board to that bus myself, using a spartan II-e device, but it shure would be nice to see someone else building something along those lines. Regards, Andras TantosArticle: 78842
Yes, that is the preferred way. Change the default to what is appropriate and then remove the qdf file from your project directory. Quartus 4.1 and higher has the feature that if defaults change in a new version you will be informed when you open the project the first time with the new version. Hope this helps, Subroto Datta Altera Corp. Martin Schoeberl wrote: > So the cleanest way to handle this would be to identify the change of the defaults > that caused my difference and add this assignment to the 'regular' project file and > remove the <project>_assignment_defaults.qpf. > > Martin > ---------------------------------------------- > JOP - a Java Processor core for FPGAs: > http://www.jopdesign.com/ > > "Subroto Datta" <sdatta@altera.com> schrieb im Newsbeitrag > news:1107808734.098840.311310@c13g2000cwb.googlegroups.com... > > With QII 4.0, all assignments were consolidated into a single file the > > qsf, instead of being stored in several different files (csf, psf, ssf, > > fsf) etc. Also as part of QII 4.0, default values of assignments were > > no longer stored in the qsf file. In the past all defaults were stored > > in the csf file. > > > > Instead defaults for converted projects were stored in the qdf file in > > the project directory, with the name being > > <project_name>_assignment_defaults.qdf. Therefore projects which have > > been converted from older (i.e before Quartus II 4.0)will have a qdf > > file in their project directory. > > > > When assignments are resolved the default values specified in > > <project_name>_assignment_defaults.qdf have a higher priority than > > those specified in quartus\bin\assignment_defaults.qdf. Therefore when > > you removed the <project_name>_assignment_defaults.qdf file some of the > > values of your default settings would have changed, and this explains > > the change in results. If you look at the file > > quartus\bin\assignment_defaults.qdf you will find a history of the > > default changes between releases from 4.1 onwards. An example of the > > comments in the QII 4.2 assignmnet_defaults.qdf file is: > > > > # Default value changes > > # > > # In 4.2, the default value of assignment DO_MIN_ANALYSIS has changed > > to "OFF" > > # In 4.1, the default value of assignment FITTER_EFFORT has changed to > > "Auto Fit" > > > > Hope this helps, > > Subroto Datta > > Altera Corp. > > > > > > Martin Schoeberl wrote: > >> I have a project which started with MP2 w. Leonardo and was converted > > by > >> several versions of Quartus (including several new file types). With > > Quartus 4.2 > >> I thought the project merely consists of proj.qpf and proj.qsf. > > Having all the assignments > >> in the .qsf file. > >> However, when I compiled the project with the other 'old' project > > files removed it resulted > >> in a different solution (fmax was 95MHz instead of 100MHz). > >> Adding the proj_assignment_defaults.qpf back to the project I got the > > original result. > >> So the question is: What's this xxx_as._def.qpf for? > >> > >> Martin > >> ---------------------------------------------- > >> JOP - a Java Processor core for FPGAs: > >> http://www.jopdesign.com/ > >Article: 78843
Hmm... Is there some trick to do a sort of "make clean" in a project directory? So it deletes all created files during synthesis? rickArticle: 78844
See http://www.altera.com/literature/hb/qts/qts_qii52002.pdf Pgs 15-17. It has a makefile with a "clean" target. Hope this helps. - Subroto Datta Altera Corp. Jedi wrote: > Hmm... > > Is there some trick to do a sort of "make clean" in a project > directory? So it deletes all created files during synthesis? > > > rickArticle: 78845
Martin Schoeberl wrote: > Hi all, > > I'm thinking about a new board for JOP (or MB, NIOS). The board should be small and > cheap (below the S3 Starter Kit). It should only contain the absolute necessary parts for a > CPU design. Here is the suggested part list: > > FPGA: Cyclone EP1C3 or Spartan XC3S200 > 256Kx16 15ns SRAM > 2 MBit serial Flash > 3.3V linear regulation > switching regulator for the core voltage > 20MHz clock to the PLL input > > I've not yet decided about a X or A device. > > A remaining question is about the form factor. I still think it makes sense to build > the board as a module that can be integrated in a board with the peripherals (similar > to the ACEX and Cyclone modules I've done). There are two 'standards' available: > > 1.) SimmStick, where the boards are designed as the 'old' PC SIMMs (see [1]). > > 2.) The 'Basic Stamp' design is a board in the form of an old 40-pin (or less) DIL IC. > An example (from a Java processor competitor): [2] > > For a Java solution in an FPGA this board should beat the Systronix aJ100 Java processor > modules (JStamp or JStick [3] - they have both form factors) in performance and price. > One nice thing about the SimmStick is that there are plenty of I/O boards already available > (see [4, 5, 6]). > It seems a relative 'old' design, but it's a bus and I can build my first JOP cluster with those > boards ;-) > > What do you guys think about this idea? Does it make sense to build a another FPGA board? > > [1] http://www.simmstick.com/ > [2] http://jstamp.systronix.com/jstamp_photos.htm > [3] http://www.jstik.com/ > [4] http://www.dontronics.com/dt.html > [5] http://www.hobbyengineering.com/SectionSS.html > [6] http://www.simmstick.com/simmstic1.htm > > Martin > ---------------------------------------------- > JOP - a Java Processor core for FPGAs: > http://www.jopdesign.com/ > > Hi Martin, I would not support the design of your product based on the simmstick for the following reasons: (1) The signaling standards supported by the simmstick are very limited and I doubt very much whether you could support any of the newer, low voltage , high speed, differential signaling standards. (2) It is very difficult for hobbyists to create their own simm sticks to run in parallel to your proposed design as most Internet based prototyping companies will not support the thickness of the pcb required( this was the case, as far as I know, from my inquires last year). (3) As mentioned previously and discussed in other Internet based discussions the limited number of GPIOs pins that will be available to the user is an extreme disadvantage. It seems to me that your best bet is to use a SODIMM socket compatible design, but this will be only reinventing the wheel. BenArticle: 78846
Gabor wrote: >>Third, remember that DDR-SDRAM has a MINIMAL clock rate > This is less likely to bite you if you bothered to use DDR in the first > place. Minimum for some chips is 83 MHz, others 66 MHz for DDR 1. Well, I once used a Graphics-RAM (because of the 32bit-data-width, wasn't a speed-critical application) and hooked it up to the plb_ddr. Turns out the RAM had a minimal clock rate of 100MHz, which is equal to the maximum clock rate the PLB can handle (or at least could handle back then). Initially, I hadn't planned on running it at that speed, so of course it didn't work until I went up to 100MHz. Took me awhile to figure this out, though. Too many damn datasheets to read. :) cu, SeanArticle: 78847
Thanks all for the infos !Article: 78848
I also had the same problem before. What I did to solve this problem is
to include the system include/lib path BEFORE the project specific
include/lib path. This is accomplished with a custom Makefile and a
snippet of the Makefile is shown below:
#################################################################
# SOFTWARE APPLICATION TESTAPP
#################################################################
TestApp_program: $(TESTAPP_OUTPUT)
$(TESTAPP_OUTPUT) : $(TESTAPP_SOURCES) $(TESTAPP_HEADERS)
$(TESTAPP_LINKER_SCRIPT) \
$(LIBRARIES) __xps/testapp_compiler.opt
@mkdir -p $(TESTAPP_OUTPUT_DIR)
$(TESTAPP_CC) $(TESTAPP_CC_OPT) $(TESTAPP_SOURCES) -o
$(TESTAPP_OUTPUT) \
-IC:/EDK/gnu/microblaze/nt/microblaze/include \
-LC:/EDK/gnu/microblaze/nt/microblaze/lib \
$(TESTAPP_OTHER_CC_FLAGS) $(TESTAPP_INCLUDES) $(TESTAPP_LIBPATH) \
-xl-mode-$(TESTAPP_MODE) \
$(TESTAPP_CFLAGS) $(TESTAPP_LFLAGS)
$(TESTAPP_CC_SIZE) $(TESTAPP_OUTPUT)
As you can see, the system include/lib path is hardcoded and appears
BEFORE any other path. I know this is a hack, but it solves my problem
for now! :)
To invoke this makefile, use: "make -f Makefile TestApp_program" et
voila~!
Let me know if this helps you or if you need more help... :-)
Jung Ko
Article: 78849Hi, I'm looking for Timing info on an Asynchronous FIFO built using Distributed RAM on Virtex4. the part # we are using is : LX100-10, package FF1513. Xilinx publishes the FIFO timing info for Asynchronous FIFOs using Block RAM, but not distributed RAM. Specifically, I'd like to know the timing of all the FIFO signals (FULL/EMPTY, ALMOST_FYLL/ALMOST_EMPTY and other FIFO status signals). If someone could shed some light on where I might find this info, I'd really appreciate it.
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