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Hello, I just (finally) got Foundation 3.1i from Xilinix as an upgrade to my 2.1i. I also downloaded the SP IV for it from Xilinx. My understanding is that applying this patch would give me 3.2I SPIV from my 3.1 on CD. After applying the patch and going to help about I still get Foundation 3.1i Build 3.1.179. It seems to me I used to get some sort of Service pak message when I applied paks for the older 2.1. From this message can I assume the service pak is not installed? What could i be doing wrong. My install path is Programs/FNDTN. Thanx RickArticle: 26976
You might look at : The NSA Hardware Analysis: VHDL models developed by NSA to evaluate the hardware performance of the AES finalists http://csrc.nist.gov/encryption/aes/round2/r2anlsys.htm http://blowfishvhdl.sourceforge.net/ http://www.cs.berkeley.edu/~iang/isaac/hardware/ This ones's in German http://www.ra.informatik.uni-stuttgart.de/~stankats/ ajd wrote: > Hi, > > Is anyone writing any cryptographic algorithms or block ciphers on an FPGA. > I'm interested as to what sort of throughput to aim for on my Xilinx > Virtex1000 -4. > > thanks > AndrewArticle: 26977
You might look at : The NSA Hardware Analysis: VHDL models developed by NSA to evaluate the hardware performance of the AES finalists http://csrc.nist.gov/encryption/aes/round2/r2anlsys.htm http://blowfishvhdl.sourceforge.net/ http://www.cs.berkeley.edu/~iang/isaac/hardware/ This ones's in German http://www.ra.informatik.uni-stuttgart.de/~stankats/ ajd wrote: > Hi, > > Is anyone writing any cryptographic algorithms or block ciphers on an FPGA. > I'm interested as to what sort of throughput to aim for on my Xilinx > Virtex1000 -4. > > thanks > AndrewArticle: 26978
You might look at : The NSA Hardware Analysis: VHDL models developed by NSA to evaluate the hardware performance of the AES finalists http://csrc.nist.gov/encryption/aes/round2/r2anlsys.htm http://blowfishvhdl.sourceforge.net/ http://www.cs.berkeley.edu/~iang/isaac/hardware/ This ones's in German http://www.ra.informatik.uni-stuttgart.de/~stankats/ ajd wrote: > Hi, > > Is anyone writing any cryptographic algorithms or block ciphers on an FPGA. > I'm interested as to what sort of throughput to aim for on my Xilinx > Virtex1000 -4. > > thanks > AndrewArticle: 26979
> How exactly could the tools know to optimize the duplicate register > away? Even if it uses the same input signal and the same logic to the > register, the output nets are different. I don't think the tools are > smart enough to know that the duplicate registers could be removed. Have > you seen this happen? Software compilers call is common subexpression elimination. The technology is well understood. Yes, I've seen it happen in Verilog/Synplify. There is a special flag "syn_preserve=1" to prevent it. My guess is that it happens more often than most people expect if you are using high level languages. You won't understand every gate in a design because many are hidden in library blocks. -- These are my opinions, not necessarily my employers. I hate spam.Article: 26980
Hi Rick, You are correct - SP4 will indeed upgrade your Xilinx software to 3.2i (specifically, 3.2.04i). However, what you are seeing in the Foundation Project Manager ' Help --> About ', is the version of the graphical front-end (this interface is created by Aldec, and hence (and unfortunately) different versions), rather than the Xilinx tools versioning. Any 'Xilinx tool' that you run should have the correct 3.2 software version listed. Common examples of these could be : Some command line tools : - ngdbuild - map - par (all of these should show the Xilinx version in the corresponding report) Or doing a Help-->About in the GUIs: - Design Manager - FPGA Editor - Constraints Editor - Floorplanner - JTAG Programmer / Hardware Debugger You can also quickly check which version you have by running the 'XRAY' diagnostic tool, and click on the 'Software Environment'. Hopefully this clears things up! Curtis Hawker wrote: > Hello, > > I just (finally) got Foundation 3.1i from Xilinix as an upgrade to my > 2.1i. I also downloaded the SP IV for it from Xilinx. My > understanding is that applying this patch would give me 3.2I SPIV from > my 3.1 on CD. After applying the patch and going to help about I still > get Foundation 3.1i Build 3.1.179. It seems to me I used to get some > sort of Service pak message when I applied paks for the older 2.1. From > this message can I assume the service pak is not installed? What could > i be doing wrong. My install path is Programs/FNDTN. > > Thanx > RickArticle: 26981
Thank you very much, that helps me a lot. I still have another question. In the case I want to upload a new configuration in the XC18V00 through JTAG port, which instruction should I put in the instruction register? Is there a good example of this type of application anywhere? Thank you Alexandre Boyer In article <3A06D5DB.E2896812@cae.ca>, Etienne Racine <etienne@cae.ca> wrote: > Bonjour Alexandre, > > alexboyer@my-deja.com wrote: > > > I'm not familiar with jtag algorithms. What is the exact purpose of the > > Boundary Scan register of the serial eeprom XC18V00 => what is the > > purpose of the data written in this register in the Shift-DR state? > > The Boundary-Scan Register (BSR) is one of the test registers that can > be > serially loaded and read by JTAG (there are a few ones). The BSR is > special > since it can sense the values applied to the I/O pads of the device (in > your case, the XC18v00 PROM); if needed, the BSR can also drive values > for > test purposes. > > I took a look at one of the programming algorithms of the XC18V00 and I > haven't seen any place where the BSR is written/read. In any cases, > writing > to the BSR (specifically) is usually an operation done for testing > purposes > and/or to ensure safe values are applied to the board when programming > the > chip. > > > What is the exact difference between the EXTEST and the SAMPLE/PRELOAD > > instructions? > > Both instructions give the ability to read/write from/to the BSR. In the > case of SAMPLE/PRELOAD, the device continues to operate normally (the > output pads get their value from the core logic). With EXTEST, however, > the > chip is placed in its test mode and the outputs are driven with the > values > from the BSR. > > In addition, in the case of the XC18V00 PROM, the inputs to the core > logic will also be driven with the values coming from the BSR when the > EXTEST instruction bacomes active. Such functionality is usually seen in > another standard JTAG instruction named INTEST, but Xilinx folks > integrated this optional feature in EXTEST. > > Regards, > > Étienne. > -- > ______ ______ > *****/ ____// _ \_\************************************************* > * / /_/_ / /_/ / / Etienne Racine, Hardware Designer * > * / ____// __ /_/ Visual Systems Engineering * > * / /_/_ / / /\ \ \ CAE Electronics Ltd. * > */_____//_/_/**\_\_\************************************************* > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26982
I have some old design files done with Synario schematics and Abel. I am looking for a Synario Dongle and associated license file that someone is willing to sell. The license file must have the following feature enabled: Product=Programmable IC Entry Licensed Software=SYN-ENTRY Product Version=4.11 Please email the license file for my inspection, with your offer to sell the associated Dongle. I am willing to purchase up to two license files and dongles. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 781.481.9233 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26983
alexboyer@my-deja.com wrote:
> In the case I want to upload a new
> configuration in the XC18V00 through JTAG port, which instruction
> should I put in the instruction register? Is there a good example of
> this type of application anywhere?
Well, the configuration process involves not just one but a few instructions
(depending of the options you selected, such as "verify", "erase before
programming", etc.).
I'd say the best answer is to look at the algorithm yourself: in JTAG
Programmer, instead of using a cable for configuration (the default choice),
create a SVF file. This is a standard ASCII file that should contain SIR
(instruction reg.) and SDR (data reg.) sequences.
If you need help reading a SVF file, there's an appnote available (can't
remember the number) on the Xilinx website; this is an industry-standard
format that should also be described in details on Asset's website.
Étienne.
P.S.: Has anyone been able to succesfully download any WebPack module since
Xilinx decided to turn their website into a flashy, fully Java-enabled,
great-looking but absolutely unuseable site? I tried to get the latest
versions but they download soooo slooooowly that I always end up pressing
"cancel" before they finish (that's when the transfer is not aborted all by
itself, of course).
Hey, Xilinx! Just a "Fast text-based site for downloads -> click here" link
would be something good to have...
--
______ ______
*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
* / /_/_ / / /\ \ \ CAE Electronics Ltd. *
*/_____//_/_/**\_\_\*************************************************
Article: 26984> P.S.: Has anyone been able to succesfully download any WebPack module since > Xilinx decided to turn their website into a flashy, fully Java-enabled, > great-looking but absolutely unuseable site? I tried to get the latest > versions but they download soooo slooooowly that I always end up pressing > "cancel" before they finish (that's when the transfer is not aborted all by > itself, of course). > > Hey, Xilinx! Just a "Fast text-based site for downloads -> click here" link > would be something good to have... > -- > ______ ______ > *****/ ____// _ \_\************************************************* > * / /_/_ / /_/ / / Etienne Racine, Hardware Designer * > * / ____// __ /_/ Visual Systems Engineering * > * / /_/_ / / /\ \ \ CAE Electronics Ltd. * > */_____//_/_/**\_\_\************************************************* Yes, I downloaded all the WebPACK modules from the "new" Xilinx site. I also was disappointed by the new look of the site because it takes too many hops from the homepage to get to any real technical content. And each hop takes longer because of the heavy graphics and Java. It would be nice to move back to a functional web site for engineers and leave the other stuff for their investors. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 26985
"Peter Dennett" <pdennett@padsoft.com> wrote in message news:D80554580569F2EE.743E0A7942AB9796.7CA462C6B0873E38@lp.airnews.net... > Is there any GNU or like open source system for conversion of > C to VHDL? Or for that matter any other higher level language. No response on the first take, so I guess not.... -- Peter Dennett Email: pdennett@padsoft.com 61 Harbor Lane Web: www.padsoft.com Kemah, TX 77565 Web: www.boatbrains.com Voice: 281 334 3800 Cell: 713 899 6100 Fax: 281 521 1032Article: 26986
Hi all, I'm trying, rather unsuccessfully, to instantiate a Xilinx coregen dual port RAM into my design. I'm trying to use the HDL flow in the Foundation tool set, as I am comfortable with their simulator. I generated a coregen dual port RAM. Then, using the HDL tool assistant, I looked at the reccomendation for instantiating the RAM in VHDL. When I try using the reccomended code I get wierd errors. I would post the errors, but I'd like to see what a successful instantiation looks like first. Is there some example someplace that shows how to instantiate coregen RAMs? Will this simulate using the Foundation simulator? Thanks, John Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26987
In article <39F373A2.8D2CC1C9@xilinx.com>, peter.alfke@xilinx.com wrote: > Of course, this is unpleasant and expensive for many > users, and we regret this development. > But if anybody knows a smarter solution, let me know. Well, It would have been nicer if the XPLA3 family was a superset of the XPLA Enhanced family. A few months ago, I started down the path of redesigning for the XPLA3 to get the cost savings and product availability. I quickly discovered that neither of my designs fit in the XPLA3 with the required speed. The XPLA3 series has less than half the total number of Pterms than the XPLA Enhanced does (48 vs 112 per block). Since I wasn't sure I was reading the datasheet correctly, I asked a very direct question about this to Xilinx. The only answer I got was "Don't worry about that. Give us your code and we'll make it fit." Grrrr.. At least that got me started on a Spartan II design. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26988
If you are not using the Foundation Base version, then you must have the ability to lock the pins using FPGA Express constraints editor. Just export the constraints together with the netlist file(s). Another approach is to use UCF file to lock the pins manually. You may also be able to do the same using Xilinx Constraint Editor. --Yury Wolf In article <MPG.147062b9482962529896c8@news.supernews.com>, George Pontis <geo@z9.antispam.com> wrote: > Hello FPGA users, > > I am trying my best to intelligently lock at least some of the pins in a > design using a Spartan XL, in this case it is the XCS20XL-4TQ144. The > compiler does not produce an attractive design, in that the buses are > ordered in a seemingly random fashion. Also, it does not appear to > produce an optimum placement from the standpoint of routing, even though > it probably meets the requirements of the design. > > The pins that I seek to lock are for several 16 bit buses. The design > contains a 16b bidirection data bus D[15:0], a buffered version of it > that is enabled for certain operations BD[15:0], an input bus from an ADC > that can drive onto the data bus ADC[15:0], and an output bus that can > latch data from the data bus L[15:0]. > > My first thought is to place D[] and BD[] at opposite ends of horizontal > longlines. Then intersperse ADC[] with D[] on one side, and L[] with BD[] > on the opposite side. Alternatively one could put intersperse ADC[] and > L[], and place them at the top and bottom of the chip to take advantage > of splitting the vertical longlines. (Say ADC[7:0]/L[7:0] at the top and > ADC[15:8]/L[15:8] at the bottom.) > > But I am quickly getting beyond my understanding of the device and the > subtleties of routing. Can someone offer a suggestion on this specific > layout ? Or perhaps better for all, give us a pointer to some general > information on human-assisted pin locking ? > > Any suggestions or discussion on the subject will be much appreciated ! > > -- > George Pontis > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26989
Look at chapter "Synthesis and Simulation Design Guide" after following
the link below:
http://toolbox.xilinx.com/docsan/2_1i/
In article <3A06C0EB.A4BCDFB6@asicentrum.cz>,
Michal Prokes <michal.prokes@asicentrum.cz> wrote:
> Hello,
> I'm student and I'm interested in encoding of internal states in FSMs
> (finite state machine) in relation to realization these FSMs to Xilinx
> FPGA.
> I try to use different encoding of internal states (binary, gray,
> johnson, onehot, twohots, fanin ... etc) and I woud like to find out
> some relations between encoding and number of used CLBs, etc..
>
> So, could you send me some tips to literature or www links (about
this)?
>
> Thanks,
>
> MICHAL (michal.prokes@asicentrum.cz)
>
>
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 26990greg wrote-> >Is it possible to build a crosspoint switch in CPLD/FPGA, or is the solution >to use a Lattice device? > >The desire is to put a bi-directional bridging layer between dedicated CPU >pins & the IO circuitry to allow programmable rerouting to IO pins. Having >it all live in the one prog device ALONG WITH any other interface glue logic >would be handy. > >Cheers > >Greg Sure! All of the above. My guess is you are referring to the GDX/GDXVA devices from Lattice, which implement 4input, cascadable muxes with registered or combinatorial outputs in the i/o pads, and have a global routing resource to allow construction of buffers, muxes, crosspoints, programmable routing,etc... Crosspoint switches can be implemented in FPGAs/CPLDs as well, although probably not with the 3.5ns performance of the GDXVA series. I/O increases for large busses usually bring a higher price for PLDs as well. GDX is not a PLD, but simple functions of 2 or 3 variables can be implemented in one 4 input mux, and allow you to design simple logic functions for signal controls. Cascading mux stages will allow much larger size gating. There are quite a number of other features within the deivce family, so I would encourage a discussion with the friendly local Lattice FAE! :-) good luck in the design- Michael Thomas LSC SFAE New York/New Jersey 631-874-4968 fax 631-874-4977 michael.thomas@latticesemi.com for the latest info on Lattice products - http://www.latticesemi.comArticle: 26991
P wrote: > > In article <39F373A2.8D2CC1C9@xilinx.com>, > peter.alfke@xilinx.com wrote: > > Of course, this is unpleasant and expensive for many > > users, and we regret this development. > > But if anybody knows a smarter solution, let me know. > > Well, > > It would have been nicer if the XPLA3 family was a superset > of the XPLA Enhanced family. A few months ago, I started > down the path of redesigning for the XPLA3 to get the > cost savings and product availability. I quickly discovered > that neither of my designs fit in the XPLA3 with the required > speed. The XPLA3 series has less than half the total > number of Pterms than the XPLA Enhanced does (48 vs 112 per > block). If you can work with a PTerm Fan-in of 80 look at the ATMEL ATF1504AS family Some minor edits of the XPLA.pla file, and you can feed it into an Atmel fitter - pinouts I think are the same. We have ported XCR5032 -> ATF1502. The ATF1504 has lower static Idd then XCR, but a higher mA/MHz slope. > Since I wasn't sure I was reading the datasheet correctly, > I asked a very direct question about this to Xilinx. The > only answer I got was "Don't worry about that. Give us > your code and we'll make it fit." And did they ? -jg -- ======= 80x51 Tools & PLD IP Specialists ========= = http://www.DesignTools.co.nzArticle: 26992
Peter Dennett wrote: > > "Peter Dennett" <pdennett@padsoft.com> wrote in message > news:D80554580569F2EE.743E0A7942AB9796.7CA462C6B0873E38@lp.airnews.net... > > Is there any GNU or like open source system for conversion of > > C to VHDL? Or for that matter any other higher level language. > > No response on the first take, so I guess not.... I don't think that there's ANY tool that does this, although I'm under the impression that several very smart people have tried hard. This isn't to say that it's impossible, but if you want to make something work a hardware description language like VHDL, Verilog, JHDL, or even JBits might be appropriate. As to why this might be difficult, just imagine hardware built so that the runtime stack works... Or worse yet, the recursive factorial algorithm! The best way I can think to do this is to put a CPU on an FPGA and run compiled code -- not exactly taking advantage of what an FPGA has to offer. Hopefully someone else has a better idea. AFAIK, the VHDL simulators generate C code, compile the C code, and then run that on a conventional processor.... :-) -Luke P.S. I only install the HDL above tools -- I don't use them. It may be a stretch to imply that I'm qualified to say what I've said... -- Luke Scharf, Student Researcher & Sysadmin Virginia Tech Configurable Computing http://www.ccm.ece.vt.edu/scharf.htm :wqArticle: 26993
> Use logiblox or coregen to set a constant. Why not use a buf and tie power/ground on the input side to what ever your constant wants to be?Article: 26994
Hello all, I am using the WebPACK 3.2 to do a Spartan2 design in VHDL. Is the "Xilinx Unified Library" present in WebPACK 3.2i? I have been able to instantiate a RAMB4_S8 by manually having a component declaration, probably because RAMB4_S8 is a primitive. But the compiler won't recognize other design elements, such as the ADSU4 macro. Is there any way of using the ADSU4 macro from VHDL? Regards, Karl OlsenArticle: 26995
Why not use a 100 ohm resistor at the FPGA input/output, and some value pullup to 5V on the other side? I don't know what FPGA you are talking about, but the Virtex-E spec says the I/O is 5V tolerant with a 100 ohm resistor... I also don't know what speed these signals are. Perhaps you could elaborate? Stuart J Adams <sja@world.std.com> wrote in article <G3Gtyx.GzC@world.std.com>... > I have a 3.3 volt (non 5 volt tolerant) > bidirectional bus coming out of an FPGA and > need to shift it to true 5 volt CMOS > levels. > > Can anyone recommend an octal level > shifting buffer where I can get 3.3 volt > CMOS on one side and 5 volt true CMOS levels > on the other side ??? > > Thanks, > Stuart > > >Article: 26996
> > Is there any GNU or like open source system for conversion of > > C to VHDL? Or for that matter any other higher level language. Since no one else has come up with anything, here's a possible lead. Quoting from my earlier posting on "generators vs. synthesizers", (http://www.fpgacpu.org/usenet/generators.html), I wrote "... 2. HLL synthesis (behavioral compilers / hardware inference systems), such as * C/C-like: Napa-C [7], Streams-C [8], Handel-C [9], Leong's lcc-VHDL system [10], 'Tsukuba' C-HDL compiler [11] ... [7] FCCM98 [8] Gokhale et all, FCCM00, also e.g. http://www.arpa.gov/ito/psum1998/F282-0.html [9] http://www.embeddedsol.com/technology/info_sheets/info_sheet_01.htm [10] "Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping", FCCM99, http://www.cse.cuhk.edu.hk/~phwl/papers/fccm99_fixed.ps.gz [11] Maruyama, FCCM00 " See reference #10 in particular. If I recall correctly, it describes a VHDL generator backend for the lcc retargetable C compiler. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 26997
In article <01c0485f$f7630a90$b30bf7a5@drt1>, "Austin Franklin" <austin@darkroom89.com> wrote: > > Use logiblox or coregen to set a constant. > > Why not use a buf and tie power/ground on the input side to what ever your > constant wants to be? > > This works just fine, but for large numbers the buffers take up a lot of room on the schematic sheet. Also, a logiblox constant is more readable from a documentation perspective. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26998
John, > I'm trying, rather unsuccessfully, to instantiate a Xilinx coregen dual > port RAM into my design. I'm trying to use the HDL flow in the > Foundation tool set, as I am comfortable with their simulator. > > I generated a coregen dual port RAM. Then, using the HDL tool > assistant, I looked at the reccomendation for instantiating the RAM in > VHDL. When I try using the reccomended code I get wierd errors. I > would post the errors, but I'd like to see what a successful > instantiation looks like first. this is how an instantiation of a coregen module could look like. Please note that I am using a "wrapper" entity in simulation. This avoids the requirement of having configuration clauses throughout the whole design hierachy. The file a) is only required during simulation, it will be replaced by the EDIF file during synthesis. File b) shows how the resulting entity (be it from case a) or the EDIF netlist) is instantiated. Hope this helped, Best regards Felix Bertram Trenz Electronic www.trenz-electronic.de ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ a) in simulation only library IEEE; use IEEE.STD_LOGIC_1164.all; -- synopsys translate_off Library XilinxCoreLib; -- synopsys translate_on entity dpram256x32 is port ( addra: IN std_logic_VECTOR(7 downto 0); clka: IN std_logic; addrb: IN std_logic_VECTOR(7 downto 0); clkb: IN std_logic; dia: IN std_logic_VECTOR(31 downto 0); wea: IN std_logic; dob: OUT std_logic_VECTOR(31 downto 0)); end entity; architecture CoreGen of dpram256x32 is component dpram256x32ii port ( addra: IN std_logic_VECTOR(7 downto 0); clka: IN std_logic; addrb: IN std_logic_VECTOR(7 downto 0); clkb: IN std_logic; dia: IN std_logic_VECTOR(31 downto 0); wea: IN std_logic; dob: OUT std_logic_VECTOR(31 downto 0)); end component; -- synopsys translate_off for all : dpram256x32ii use entity XilinxCoreLib.C_MEM_DP_BLOCK_V1_0(behavioral) generic map( c_depth_b => 256, c_depth_a => 256, c_has_web => 0, c_has_wea => 1, c_has_dib => 0, c_has_dia => 1, c_clka_polarity => 1, c_web_polarity => 1, c_address_width_b => 8, c_address_width_a => 8, c_width_b => 32, c_width_a => 32, c_clkb_polarity => 1, c_ena_polarity => 1, c_rsta_polarity => 1, c_has_rstb => 0, c_has_rsta => 0, c_read_mif => 0, c_enb_polarity => 1, c_pipe_stages => 0, c_rstb_polarity => 1, c_has_enb => 0, c_has_ena => 0, c_mem_init_radix => 16, c_default_data => "0", c_mem_init_file => "dpram256x32.mif", c_has_dob => 1, c_generate_mif => 1, c_has_doa => 0, c_wea_polarity => 1); -- synopsys translate_on begin U0 : dpram256x32ii port map ( addra => addra, clka => clka, addrb => addrb, clkb => clkb, dia => dia, wea => wea, dob => dob); end CoreGen; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ b) in synthesis and simulation library IEEE; use IEEE.std_logic_1164.all; entity Ctrl is end Ctrl; architecture BHV of Ctrl is component dpram256x32 port ( addra : in STD_LOGIC_VECTOR (7 downto 0); addrb : in STD_LOGIC_VECTOR (7 downto 0); clka : in STD_LOGIC; clkb : in STD_LOGIC; dia : in STD_LOGIC_VECTOR (31 downto 0); wea : in STD_LOGIC; dob : out STD_LOGIC_VECTOR (31 downto 0) ); end component; constant DANGLING_INPUT_CONSTANT : STD_LOGIC := 'Z'; signal Dangling_Input_Signal : STD_LOGIC; begin ---- Component instantiations ---- U1 : dpram256x32 port map( addra(0) => Dangling_Input_Signal, addra(1) => Dangling_Input_Signal, addra(2) => Dangling_Input_Signal, addra(3) => Dangling_Input_Signal, addra(4) => Dangling_Input_Signal, addra(5) => Dangling_Input_Signal, addra(6) => Dangling_Input_Signal, addra(7) => Dangling_Input_Signal, addrb(0) => Dangling_Input_Signal, addrb(1) => Dangling_Input_Signal, addrb(2) => Dangling_Input_Signal, addrb(3) => Dangling_Input_Signal, addrb(4) => Dangling_Input_Signal, addrb(5) => Dangling_Input_Signal, addrb(6) => Dangling_Input_Signal, addrb(7) => Dangling_Input_Signal, dia(0) => Dangling_Input_Signal, dia(1) => Dangling_Input_Signal, dia(2) => Dangling_Input_Signal, dia(3) => Dangling_Input_Signal, dia(4) => Dangling_Input_Signal, dia(5) => Dangling_Input_Signal, dia(6) => Dangling_Input_Signal, dia(7) => Dangling_Input_Signal, dia(8) => Dangling_Input_Signal, dia(9) => Dangling_Input_Signal, dia(10) => Dangling_Input_Signal, dia(11) => Dangling_Input_Signal, dia(12) => Dangling_Input_Signal, dia(13) => Dangling_Input_Signal, dia(14) => Dangling_Input_Signal, dia(15) => Dangling_Input_Signal, dia(16) => Dangling_Input_Signal, dia(17) => Dangling_Input_Signal, dia(18) => Dangling_Input_Signal, dia(19) => Dangling_Input_Signal, dia(20) => Dangling_Input_Signal, dia(21) => Dangling_Input_Signal, dia(22) => Dangling_Input_Signal, dia(23) => Dangling_Input_Signal, dia(24) => Dangling_Input_Signal, dia(25) => Dangling_Input_Signal, dia(26) => Dangling_Input_Signal, dia(27) => Dangling_Input_Signal, dia(28) => Dangling_Input_Signal, dia(29) => Dangling_Input_Signal, dia(30) => Dangling_Input_Signal, dia(31) => Dangling_Input_Signal, clka => Dangling_Input_Signal, clkb => Dangling_Input_Signal, wea => Dangling_Input_Signal ); Dangling_Input_Signal <= DANGLING_INPUT_CONSTANT; end BHV; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ end! 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I am trying to infer a RAM for a EPF10K100A with Synplify 5.1.5a.
I used the following example from Synplicity for a single port RAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_test is
port (q:out std_logic_vector(3 downto 0);
d:in std_logic_vector(3 downto 0);
addr:in std_logic_vector(2 downto 0);
we :in std_logic;
clk:in std_logic);
end ram_test;
architecture rtl of ram_test is
type mem_type is array(7 downto 0) of std_logic_vector(3 downto 0);
signal mem:mem_type;
begin
q <= mem(conv_integer(addr));
process(clk,we,addr)
begin
if rising_edge(clk) then
if (we='1') then
mem(conv_integer(addr))<=d;
end if;
end if;
end process;
end rtl;
Synplify always wants to map this RAM to a dual port RAM (altdpram), when
10KE is selected. Since the 10KA devices do not support dual port ram
the technologie mapper maps the RAM to flipflops.
Does anybody know how to tell Synplify to use a single port RAM?
Regards
Rainer
--
-----------------------------------------------------------------
Rainer Becker rainer@pentatec.de
PentaTec GmbH Tel. +49 89 456918-21
Hermann-Oberth-Str. 18, 85640 Putzbrunn Fax +49 89 6884310
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