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Xilinx CoreGen has a sine/cosine generator and a numerically controlled oscillator that might help. You can check their web page for details or run CoreGen if you have a copy. <andrew_f66@my-deja.com> wrote in message news:8s99h0$9v7$1@nnrp1.deja.com... > I'm a final year undergraduate doing a project on implementing a PWM > circuit on a Xilinx FPGA for driving an induction motor. Somehow I need > to be able to generate a digital sine wave to compare with a triangular > carrier wave to generate the PWM. Someone suggested programming an > EEPROM with a look-up table of Sine values, but this doesn't seem a > very flexible way of doing it. > > Can anyone help, with a reference or anything else? Any suggestions on > any other part of the project? > > Thanks, > > Andrew F. > Bristol Uni. > > > Sent via Deja.com http://www.deja.com/ > Before you buy. >Article: 26401
The 9500 family has product term clocks, so I think you should be able to have as many 'event statements as you have macrocells. I wouldn't give up on the architecture until you find out if it's an FPGA express problem.Article: 26402
rickman <spamgoeshere4@yahoo.com> writes: > Neil Franklin wrote: > > > > rickman <spamgoeshere4@yahoo.com> writes: > > > > > Neil Franklin wrote: > > > > > > > > Emulate historical CPUs. PDPs for the beginning. > > > > > > I would be very interested in working on a PDP-8 or PDP-11 design. I > > > > Depends on what you want the processor to do. If an 12 bit, single > > PDP-11 is an 8x16 register CISC architecture, which is mainly > > I am actually looking for a very small engine that can be programmed. It > should have very small memory requirements (< 1K words, maybe << 1K So from address generation out, 10bits is already enough. > control an IO chip doing DMA and data formatting. It may not be in the > direct data path, but will have to do high speed control of the data > path. So either data path width (if it does end up in the data path) or what ever width is needed to switch as many control bits that you want to switch in one IO cycle of the processor. From that width you will get the amount of instruction bits available per memory read. That will then determine the type of instruction set (single accumulator like PDP8 need few, multiple registers and 2 or 3 operand instructions require more, Forth requires very few). Without knowing what the IO register set of the processor (= control register set of the data path you are controlling) I can not give any more detailled advice. > I have fully formed the requirements in my mind. I am exploring new > territory to see if there is something useful here. My best wishes for success. > > > I am also toying with the idea of a Forth processor. > > > > Try: http://www.cse.cuhk.edu.hk/~phwl/msl16/msl16.html, it runs 3 > > instructions per memory access, runs on a XC4006E. > > Yes, I found that site today, thanks. And given that you seem to be familiar with using Forth it may be the best idea for you. Thanks to very small instruction words it can crank out signals at a high rate. I am not good enough at Forth to contemplate using one. I just about understand the concepts and admire the simplicity, but I never managed to wrap my mind around it good enough to instictively come up with solutions. > > > I think you will find the place and route time on even the > > > fastest Sparc to take a lot longer than the download time for a > > > configuration file. > > > > This being? Worst case I can start and log out. > > I don't know what it takes on a Sparc, but my place and route times for > a 4013 design are from 30 min to an hour on a 233 MHz PC. Wow. > I guess this may shrink a lot on a current Sparc. The Sparc I have is not current. Dual 200MHz UltraSparcII, 2.5 years old. > > Editing will have to be local. But with the target being ASCII files > > with publically specified content (EDIF, XNF) that is something I can > > write myself if neccessary. So only non-graphical compiling will need > > the Sun. > > You are thinking about the source. But there are other tools that need > to show you the chip layout, floorplanner for one. I also use EPIC which > actually lets you connect the dots inside the chip in infinite detail. > doing. This involves boatloads (thats a technical term invented by Dave > Berry) of graphics. From the description that looks like a CAD program. That definitely rules out modems. (I work with CAD-ing (building-)architects). > > > > So generating EDIF or XNF ASCII files by some means and then compiling > > > > them to bitstreams on a Sun or WINE is all the tools I need? > > > > > > You make that sound so simple, but yes. > > > > Where are the difficulties? What are these? > > You are the one who is going to do it, right? Yes. Possibly others then duplication the finished design. > after you have tried. Maybe it is no big deal. I think it can be done > easily in forth if you know what you want in terms of a design. I just > don't know how easy it will be to read the resulting HDL source that > way. Hierarchical design by schematic can be a bear to see what you > really have. You can't see all the levels at the same time. Actually a problem I have run into in programming, so I will have to simply try if it becomes unmanagable. My C code gets described as "very readable". I also tend to be an very methodical programmer (at cost of taking more time and generating slower code). > I have the same problem with VHDL. I think I should learn to apply > software development techniques to my hardware. :-) > One problem is that I > feel a very strong need to optimize my design for single cycle speed and > this often requires iterative design. Like the type of programmers who unroll loops in source. Lookily I tend to not mind slower code, so long it simplifies the source. > > > What is "this box here"? Do the chip vendors offer tools for it? > > > > AMD K6-2 350 running Linux 2.2.13. > > So you want tools that run under Linux, right? Why does that require > open source? Well it actuall requires any of the following: - vendor binary for Linux (not existant, I can not make it happen) - vendor source for compiling to Linux (dito) - other commercial binary for Linux (either non existant or expensive) - other commercial source for linux (AFAIK non existant) - non commercial (= open source) source for Linux - emulator that will run 1 or 3 (emulators often are slow/problematic) So I naturally looked for 5. It looks that everyone is recommending 6, and 5 does not exist, so I suppose that I will have to settle for 6. > > > If your design is not too complex, > > > > If I am making own boards (wire wrap perfered), I am limited to PLCC84, > > so 20x20 CLBs (XC4010) seems to be the limit (and enough for the first > > few projects, use 2 of them if neccessary). > > Any reason that you can't buy a board with a larger chip? That is the other possibility. But I have so far only found boards with 8/16/32bit RAM. Makes 18/36bit processors problematic. I am actually surprised that no board I have found so far offers 18/36bit to enable designs with parity (and parity generator/checker in the FPGA). Perhaps I will have to start with 12/16bit projects with an 16bit board. Or waste 7/16 of board RAM (folding 36 to 2*18 or 4*9 and then using 9/16 of bits). > what is available. But I thought there were boards for $159 from Xess. I had a look at the Xess XS40 board, but I disliked: only 32k*8 RAM, few IO pins (so I can not add more RAM), unneccessary 8051. The board seems to be designed for "FPGA as IO for CPU" style designs (most likely more common, so sensible for an trainings board, but not my case). I am looking for: 1-16 MByte+parity RAM (preferably 36 or 18 bit, if not then 32 or 16), IO analog hardware for: RS232, EIDE harddisk, preferably also PC-AT or PS/2 Keyboard and VGA video, ideally also Ethernet (not to be used for quite a while, so it may be missing from first board). Actually an premade board would make copying the design by others without manufacturing experience easier. I will have to go looking for more boards. > should give you a lot of bang for the buck and you won't have to worry > about board construction. Not to mention ordering all the parts (uses surprising amounts of time, as I found out when I did an Transputer board (prefab PCB, self solder)). -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 26403
Neil Franklin wrote: > > One problem is that I > > feel a very strong need to optimize my design for single cycle speed and > > this often requires iterative design. > > Like the type of programmers who unroll loops in source. Lookily I > tend to not mind slower code, so long it simplifies the source. That can be nice in software where you often have loads of headroom for the slower processing. But you often are much more pressed when designing chips. You either need to utilize the CLBs in the chip very close to 100%, or you need to push this speed grade for another ns or two improvement in performance, or *both*. Often you just don't have the luxury of not optimizing your design. > > > > If your design is not too complex, > > > > > > If I am making own boards (wire wrap perfered), I am limited to PLCC84, > > > so 20x20 CLBs (XC4010) seems to be the limit (and enough for the first > > > few projects, use 2 of them if neccessary). > > > > Any reason that you can't buy a board with a larger chip? > > That is the other possibility. > > But I have so far only found boards with 8/16/32bit RAM. Makes > 18/36bit processors problematic. I am actually surprised that no > board I have found so far offers 18/36bit to enable designs with > parity (and parity generator/checker in the FPGA). > > Perhaps I will have to start with 12/16bit projects with an 16bit > board. Or waste 7/16 of board RAM (folding 36 to 2*18 or 4*9 and > then using 9/16 of bits). Interesting that you feel you need parity. I believe most of the reasons parity was used in early DRAM was alpha particle related softerrors from contamination in the package materials. Now they have cleaned up the package materials and very few machines use or need any error detection or recovery. > > what is available. But I thought there were boards for $159 from Xess. > > I had a look at the Xess XS40 board, but I disliked: only 32k*8 RAM, > few IO pins (so I can not add more RAM), unneccessary 8051. The board > seems to be designed for "FPGA as IO for CPU" style designs (most > likely more common, so sensible for an trainings board, but not my case). > > I am looking for: 1-16 MByte+parity RAM (preferably 36 or 18 bit, if > not then 32 or 16), IO analog hardware for: RS232, EIDE harddisk, > preferably also PC-AT or PS/2 Keyboard and VGA video, ideally also > Ethernet (not to be used for quite a while, so it may be missing from > first board). > > Actually an premade board would make copying the design by others > without manufacturing experience easier. > > I will have to go looking for more boards. Interesting requirements. This is almost the DSP board that I intend to build shortly. I already have one that I sell which does not have the DRAM. It contains four FPGAs, 256K x 32 SRAM memory, 2 MB of Flash, dual RS-232/422/485, a parallel interface that can be used for IDE via the 2mm 44 pin connector and analog IO. I am looking at adding an Ethernet interface via a daughterboard in the near future as well. The next board I build will likely have up to 32 MB of SDRAM. But I don't think anyone makes an 18 bit wide version. If they do, that could be used. BTW, these days 32 MB is a single SDRAM chip! To add Parity would require an entire second chip for two bits! I am pretty sure that SyncSRAM comes in parity widths, but that is only slightly more dense than standard async SRAM. I believe it can be found in 1 MB or maybe 2 MB chips at this time. So I could not fit 16 MB on a PC/104 board with all the other circuitry. > > should give you a lot of bang for the buck and you won't have to worry > > about board construction. > > Not to mention ordering all the parts (uses surprising amounts of > time, as I found out when I did an Transputer board (prefab PCB, self > solder)). You don't need to tell me about the hassels of ordering parts. I have so much more respect for purchasing personel now than I did before I started my own company. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26404
andrew_f66@my-deja.com wrote: > > I'm a final year undergraduate doing a project on implementing a PWM > circuit on a Xilinx FPGA for driving an induction motor. Somehow I need > to be able to generate a digital sine wave to compare with a triangular > carrier wave to generate the PWM. Someone suggested programming an > EEPROM with a look-up table of Sine values, but this doesn't seem a > very flexible way of doing it. > > Can anyone help, with a reference or anything else? Any suggestions on > any other part of the project? Generating a sine wave is often done via a lookup table like an EPROM. A counter is incremented at rate that sets the period of the wave and the value of the counter at each clock is used as addresses into the EPROM. The data in the EPROM is the value for the sine wave. It is common to only store a half cycle of the sine wave and invert separately. It is also common to invert the address into the table on every other quadrant to further reduce the size of the table. But the real question is, are you comparing the triangle wave to the sine wave in analog or in the digital domain? If in the digital domain, I would not use the triangle wave. I would just use the output of the sine table to load a counter which is then counted down. This sets the width of your PWM output. The PWM counter maximum value loaded should correspond to a max voltage output and the minimum should correspond to the minimum voltage output. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26405
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:39E6BF1D.DCF02AC6@yahoo.com... > I am actually looking for a very small engine that can be programmed. It > should have very small memory requirements (< 1K words, maybe << 1K > words) so that it can operate from on chip memory. It will be used to > control an IO chip doing DMA and data formatting. It may not be in the > direct data path, but will have to do high speed control of the data > path. Check out KCPSM by Ken Chapman (Xilinx), an embedded 8-bit MCU core for Virtex-family devices. 35 Virtex CLBs and one block RAM. Nice. See www.xilinx.com/xapp/xapp213.pdf. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 26406
Jan Gray wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:39E6BF1D.DCF02AC6@yahoo.com... > > I am actually looking for a very small engine that can be programmed. It > > should have very small memory requirements (< 1K words, maybe << 1K > > words) so that it can operate from on chip memory. It will be used to > > control an IO chip doing DMA and data formatting. It may not be in the > > direct data path, but will have to do high speed control of the data > > path. > > Check out KCPSM by Ken Chapman (Xilinx), an embedded 8-bit MCU core for > Virtex-family devices. 35 Virtex CLBs and one block RAM. Nice. See > www.xilinx.com/xapp/xapp213.pdf. > > Jan Gray, Gray Research LLC > FPGA CPU News: www.fpgacpu.org Thanks, that will be useful. But they don't supply source, only EDIF files. I will see if I can use it as is. I am not sure how to extend the design. I guess I can attach to the address, data bus and control signals. But I would like to be able to poke around in the "guts" of it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26407
Stuart, Not sure what you mean here. Do you want to lock to the CDMA PRN code using the DLL? If so, then the answer is no. But you can implement a code tracking loop using the logic in an FPGA. This is done with a Delayed Locked Loop, but this is a differnent kind of DLL. / Jonas Thor On Sat, 14 Oct 2000 10:40:53 GMT, sja@world.std.com (Stuart J Adams) wrote: > Anyone know if the Xilinx Virtex/Spartan II > DLL's will work with Spread Spectrum input > clocks ?? > >-- StuartArticle: 26408
andrew_f66@my-deja.com wrote: > > I'm a final year undergraduate doing a project on implementing a PWM > circuit on a Xilinx FPGA for driving an induction motor. Somehow I need > to be able to generate a digital sine wave to compare with a triangular > carrier wave to generate the PWM. Someone suggested programming an > EEPROM with a look-up table of Sine values, but this doesn't seem a > very flexible way of doing it. > > Can anyone help, with a reference or anything else? Any suggestions on > any other part of the project? You need to determine what resolution, or distortion is needed, what Freq PWM your power inverter needs, and the Freq Range needed. Also, you will probably need 3 phase generation, and dead band in the PWM drives. We did some research into sine wave generation from CPLD's, and the best method is to use a Up/Down counter ( stepped triangle ), addressing what is effectively a Sine ROM, but synthesied within product terms. In modern FPGA's, which have poor product term 'gathering', you would use the BLOCK RAM initialised to perform the ROM. There is an optimal amplitude ratio, for lowest distortion, and that is the amplitude where the slopes at maximum rate on the Sine, match the triangle. -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 26409
>It just makes the parts very hard to use in small, power limted designs. >I have to design my power supply for 500 mA per chip when I only expect >to use half that power (or less) in normal operation. I wonder why >Xilinx thinks this is not a problem? I just cannot believe I am reading this!! This makes the device useless for almost all battery-powered products. A few years ago I designed a complicated pulse generator which used 32 XC3064 devices. Now, at 500mA startup current each, that's 16 AMPS.. I saw something similar years ago, with a masked 68HC05 drawing 1 AMP for about 100us at power-up. Motorola initially stonewalled but fixed it in a later mask. This was for a lithium battery powered product whose consumption had to be below 3mA! The old XC3k devices were great for that stuff, drawing < 1mA quite feasibly. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26410
>hi at all >anyone use palasm??? CUPL is a lot better, with its state machine preprocessor. And it has PALASM import facility. I even used CUPL, with a PDS2XNF program, to design state machines in Xilinx devices. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26411
> Not sure what you mean here. Do you want to lock to the CDMA PRN code > using the DLL? I think he is refering to a hack used to reduce EMI. If you FM modulate the system clock slightly, then you get a blob rather than a spike when you look at the spectrum on the EMI tests. So I think what he's asking is what is the bandwidth or the loop filter and/or what is the max slew rate? Can the DLL track the clock when the frequency wobbles? -- These are my opinions, not necessarily my employers. I hate spam.Article: 26412
rickman <spamgoeshere4@yahoo.com> writes:
> Neil Franklin wrote:
> > > > Hmm, VHDL doesn't seem to me to have any of the above atributes.
> > > > Sure, you can code hardware in VHDL as if it's a schematic (i.e.
> > > > a markup language), but trust me. you soon learn that isn't the
> > > > way to go.
> >
> > Could you expand on this? What is the problem? What the better method?
>
> The "better" method is to describe your design as an RTL (register
> transfer level) or even behavioral description.
Which is AFAIK something of the form Register = expression involving
registers and logic combining their output.
> The VHDL compiler will
> then generate (synthesize) the logic to make it happen. Somewhat like
> magic, but only until you learn what the compiler does with your code.
Just the impression I got at an ex-assembler programmer, when I saw
the first C compiler generate an .EXE file that worked and when looked
at (disassebled) with DEBUG.COM contained real binary code. Then I
read the "Dragon Book" and magic became just an nifty program. Since
then I instinctively believe Assimov, that any sufficiently advanced
technology is indistinguishable from magic.
> Until you learn, it is a PITA! You don't get at all what you wanted.
Reminds me of my first C attempts to write into video memory. One
crash after annother. Until I grokked how to get the compiler to
generate the sequence of codes I knew I wanted (A000 in ES Register,
not 000A).
> Example:
OK, at long last I have time to study your example (Thursday and
Saturday at 24:00 was the wrong time to study an unknown programming
language).
> TrxDataInit <= '1' when SPIFSM = INIT else '0';
Do I get this right as: TrxDataInit is a FF, loaded from an MUX with 0
and 1 as its two inputs, 2nd input selected when "SPIFSM = INIT".
> This sets TrxDataInit to a 1 when the state machine, SPIFSM, is in the
> INIT state. I expect the FSM to be one-hot encoded.
Do I get this right as: 1 FF per state, only one =1, all others =0?
> That will make this
> line a simple connection between the two signals.
The INIT FF from the SPIFSM set connected to the MUX control line.
> If I don't tell VHDL
> to use one-hot encoding, I get a binary encoded 6 bit field that
> requires a lot of logic to generate TrxDataInit.
That "lot of logic" would be a state decoder. Up to 64 combinatoric
logics with each some of the 6 FFs as input. Having 64 FFs may well
be cheaper, particularly given the 4LUT type logic and abundance of
FFs in FPGAs. Good to know that tip.
> RcvDataRegister: process (SysClk, AsyncReset) begin
I will assume: process() is some macro that defines a independant
block of logic with a few inputs and outputs, which the rest of the
design can look at as an black box.
> if (AsyncReset = '1') then
> RcvDataReg <= (others => '0');
If the high-active signal AsyncReset is active, set all FFs of the
shift register to 0. The "others =>" bit I do not have an interpretation
for.
> elsif (rising_edge (SysClk)) then
When not resetting, use SysClk (an global clock of the FPGA?) to do
the shifting...
> if (SPIRiseClkEn = '1') then
.. but only if shifting is desired (the ClkEn in SPIRiseClkEn suggests
clock enable signal). FPGAs, according to the data sheets I have read
seem to prefer clock enable to MUX-ing in the FFs own output.
> if (SPI_CSNot = '0') then
> RcvDataReg <= RcvDataReg(14 downto 0) & SP_DOut;
I assume that to be the shifting itsself. You are moving FF 14 to FF 15,
FF 13 to FF14, ... FF 0 to FF 1, and loading the input (SP_DOut) to FF 0.
I can not see anywhere the definiton of RcvDataReg being a set of 16
FFs, I assume this to be somewhere else in the code. The "(14 downto
0)" looks like a subset selection, what I can not see either is some
sort of target subset selection, I assume that adding "& SP_DOut" to
the end implies how the shift will need to be.
SP_DOut must be defined in some other piece of code. This needs no
declaration in the process() bit? Does that only define "special"
FF inputs like global clocks and set/reset)?
> else
> CTS <= RcvDataReg(9);
That sets CTS (an output, an further FF?) to the FF 9, when SPI_CSNot
("Not" suggests low active signal) is active.
> This is a 16 bit shift register with a clock enable and a load signal.
Load being the reset?
> Oh, and I add a one bit register that gets loaded with the output of bit
> 9 when the register is not being shifted. Does this look anything like a
Actually if I read it right, it gets loaded only if the SPIRiseClkEn
is active (would shift), but SPI_CSNot intercepts the normal shifting
action.
> language you have seen before? It doesn't to me! This is logic
> "synthesis"!
A bit different, but comprehensible to someone who has played around
with assembler bit shift and mask instructions (and seen how they
are represented in C as bitfields).
Actually I see an non-programmer with only TTL experience having
trouble, lacking the experience in expressing actions in formulas.
Of course an C programmer without TTL experience will be at an total
loss, having no such concepts as FFs, logic, LUTs, MUXes, what signals
do, etc.
> So download the free (beer) tools and try a few simple designs. What do
> you have to lose???
Only time and download of the tools (carry computer to work, for such
size downloads). So I will go ahead.
Thanks for your helpfull posts.
--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic
Article: 26413
On Wed, 11 Oct 2000 09:34:10 +0200, "news tin" <rinux@iternet.it>
wrote:
>hi at all
>anyone use palasm???
I still use it often.
M. Simon Space-Time Productions http://www.spacetimepro.com
Free CNC Machine Control Software
Free Source Code
Control the World From a Parallel Port
Article: 26414
On Wed, 11 Oct 2000 16:39:41 +0100, Jon Seddon <js297@ecs.soton.ac.uk>
wrote:
>Hi,
>
>I'm going to have to design my own PCB with a Xilinx 4000 series FPGA on
>it. I was wondering if anyone knew of example designs on the web?
>
>
>Many thanks,
>
>
>Jon
You might want to look at my Design Your Own Processor stuff for
ideas.
URL below.
M. Simon Space-Time Productions http://www.spacetimepro.com
Free CNC Machine Control Software
Free Source Code
Control the World From a Parallel Port
Article: 26415There was a thread where this came out awhile back. The Subject is "Re: 3.3/2.5 voltage regulators". You may have to use DejaNews since the messages are starting to disappear from my server. http://x72.deja.com/getdoc.xp?AN=666891645&CONTEXT=971621936.404422731&hitnum=18 But in some of the messages, Austin Lesea from Xilinx gives some details on this. The power up current spike occurs in the 4K, the Virtex and the Spartan II (I guess the Spartan as well). Austin sent me a graph of the current spike. It appears to last about 0.5 mS. Be aware that it is much higher in the Virtex parts in low temps, up to 2 Amps! I am very surprised at all this. But I guess the primary market for these chips is telecom applications where there is normally tons of power supply available and the parts are run hot and heavy so that the normal current is not light. There it would not be a problem. I guess you can't have one chip fit every application. Austin is a good source of information. You might try asking him for the details. But you do need to dig. They are not pretty! Peter wrote: > > >It just makes the parts very hard to use in small, power limted designs. > >I have to design my power supply for 500 mA per chip when I only expect > >to use half that power (or less) in normal operation. I wonder why > >Xilinx thinks this is not a problem? > > I just cannot believe I am reading this!! This makes the device > useless for almost all battery-powered products. > > A few years ago I designed a complicated pulse generator which used 32 > XC3064 devices. Now, at 500mA startup current each, that's 16 AMPS.. > > I saw something similar years ago, with a masked 68HC05 drawing 1 AMP > for about 100us at power-up. Motorola initially stonewalled but fixed > it in a later mask. This was for a lithium battery powered product > whose consumption had to be below 3mA! The old XC3k devices were great > for that stuff, drawing < 1mA quite feasibly. > > Peter. > -- > Return address is invalid to help stop junk mail. > E-mail replies to zX80@digiYserve.com but remove the X and the Y. > Please do NOT copy usenet posts to email - it is NOT necessary. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26416
Neil Franklin wrote:
> rickman <spamgoeshere4@yahoo.com> writes:
> > TrxDataInit <= '1' when SPIFSM = INIT else '0';
>
> Do I get this right as: TrxDataInit is a FF, loaded from an MUX with 0
> and 1 as its two inputs, 2nd input selected when "SPIFSM = INIT".
Nothing here directly infers a FF. This is just a signal assignment.
TrxDataInit is assigned values from combinatorial logic. You do have the
mux part right. Of course, however, the mux will be optimized away and
only the essential logic (ands and ors) will remain. Or in this case,
none!
> > This sets TrxDataInit to a 1 when the state machine, SPIFSM, is in the
> > INIT state. I expect the FSM to be one-hot encoded.
>
> Do I get this right as: 1 FF per state, only one =1, all others =0?
That is what one-hot encoding is, yes.
> > That will make this
> > line a simple connection between the two signals.
>
> The INIT FF from the SPIFSM set connected to the MUX control line.
No, there is no FF, and the MUX disappears althogether. TrxDataInit is
connected directly to the output of the SPIFSM(INIT) state FF.
> > If I don't tell VHDL
> > to use one-hot encoding, I get a binary encoded 6 bit field that
> > requires a lot of logic to generate TrxDataInit.
>
> That "lot of logic" would be a state decoder. Up to 64 combinatoric
> logics with each some of the 6 FFs as input. Having 64 FFs may well
> be cheaper, particularly given the 4LUT type logic and abundance of
> FFs in FPGAs. Good to know that tip.
I don't have that many FFs, and you only decode the states you need to
decode, but yes, that is the idea. Not only size, but speed. No logic is
usually faster than logic.
> > RcvDataRegister: process (SysClk, AsyncReset) begin
>
> I will assume: process() is some macro that defines a independant
> block of logic with a few inputs and outputs, which the rest of the
> design can look at as an black box.
No, this is where you have to forget everything you know about software
and what you expect these statements to do and act. It is actually a bit
too involved to go into here. But this is neither a function call, nor a
function defintion. This is a statement of sensitivity. The code inside
will only be executed when one of the signals in the list *change*. Is
there anything like that in the software you have seen? I don't think
VHDL uses *new* concepts. So there may be other, non-HW, languages out
there that use some of the same concepts.
> > if (AsyncReset = '1') then
> > RcvDataReg <= (others => '0');
>
> If the high-active signal AsyncReset is active, set all FFs of the
> shift register to 0. The "others =>" bit I do not have an interpretation
> for.
The others => is the way you say "all the rest of the bits in this
vector", or in this case, just "all the bits".
> > elsif (rising_edge (SysClk)) then
>
> When not resetting, use SysClk (an global clock of the FPGA?) to do
> the shifting...
Yes.
> > if (SPIRiseClkEn = '1') then
>
> .. but only if shifting is desired (the ClkEn in SPIRiseClkEn suggests
> clock enable signal). FPGAs, according to the data sheets I have read
> seem to prefer clock enable to MUX-ing in the FFs own output.
Yes, but I don't understand the last part. Xilinx and others can use a
dedicated CE or they can use the look up table (LUT) to impement the
mux. They are equivalent.
> > if (SPI_CSNot = '0') then
> > RcvDataReg <= RcvDataReg(14 downto 0) & SP_DOut;
>
> I assume that to be the shifting itsself. You are moving FF 14 to FF 15,
> FF 13 to FF14, ... FF 0 to FF 1, and loading the input (SP_DOut) to FF 0.
Yes.
> I can not see anywhere the definiton of RcvDataReg being a set of 16
> FFs, I assume this to be somewhere else in the code. The "(14 downto
> 0)" looks like a subset selection, what I can not see either is some
> sort of target subset selection, I assume that adding "& SP_DOut" to
> the end implies how the shift will need to be.
I left out the declarations since it was pretty far back in the code. I
also really did not expect to be doing a blow by blow analysis :) The &
concatenates the two parts into a single 16 bit vector with 14 to 0
being the 15 MSBs.
All this uses FFs only because this is inside a "clocked process"
meaning it has the assignments within the if (rising_edge()) condition.
> SP_DOut must be defined in some other piece of code. This needs no
> declaration in the process() bit? Does that only define "special"
> FF inputs like global clocks and set/reset)?
>
> > else
> > CTS <= RcvDataReg(9);
>
> That sets CTS (an output, an further FF?) to the FF 9, when SPI_CSNot
> ("Not" suggests low active signal) is active.
>
> > This is a 16 bit shift register with a clock enable and a load signal.
>
> Load being the reset?
I am sorry, I mistyped. No load, but a clock enable and a shift enable.
The CTS is also a separate signal which others have said I should have
left out as good programming style. But I am not a slave to "good"
programming style. I did not want to have an entire process for this one
lousy FF and I think this shows its relationship to what is happening
better.
They should see some of my testbench code! Whew, that can be a bit
messy.
> > Oh, and I add a one bit register that gets loaded with the output of bit
> > 9 when the register is not being shifted. Does this look anything like a
>
> Actually if I read it right, it gets loaded only if the SPIRiseClkEn
> is active (would shift), but SPI_CSNot intercepts the normal shifting
> action.
Yes, this bit is loaded anytime we are not shifting. The input has two
states, shifting and not shifting. When we are not shifting, the data
should be valid and we can do things with it such as hold it in another
register so that it is always valid.
> > language you have seen before? It doesn't to me! This is logic
> > "synthesis"!
>
> A bit different, but comprehensible to someone who has played around
> with assembler bit shift and mask instructions (and seen how they
> are represented in C as bitfields).
>
> Actually I see an non-programmer with only TTL experience having
> trouble, lacking the experience in expressing actions in formulas.
>
> Of course an C programmer without TTL experience will be at an total
> loss, having no such concepts as FFs, logic, LUTs, MUXes, what signals
> do, etc.
I have 20 years experience designing logic and 8 years experience doing
FPGAS and I find this stuff to be tricky. I have only been doing VHDL
for two or three years and I am far from having it mastered. My C and
assembly experience got in the way initially as I expected VHDL code to
operate like C software. You have only scratched the surface on the
differences. Wait until you learn about signals vs. variables.
> > So download the free (beer) tools and try a few simple designs. What do
> > you have to lose???
>
> Only time and download of the tools (carry computer to work, for such
> size downloads). So I will go ahead.
>
> Thanks for your helpfull posts.
No problem.
I learned HTML by reading online references and looking at web pages. I
have 5 different books on VHDL and this is still not good enough. I
recommend that you take a VHDL course if you really want to learn the
language properly. Otherwise you may find that you have learned a lot of
misconceptions and will later have to "unlearn" them. Good luck.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design
Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
Internet URL http://www.arius.com
Article: 26417rickman <spamgoeshere4@yahoo.com> writes: > > > > If I am making own boards (wire wrap perfered), I am limited to PLCC84, > > > > so 20x20 CLBs (XC4010) seems to be the limit (and enough for the first > > > > few projects, use 2 of them if neccessary). > > > > > > Any reason that you can't buy a board with a larger chip? > > > > That is the other possibility. > > > > But I have so far only found boards with 8/16/32bit RAM. Makes > > 18/36bit processors problematic. I am actually surprised that no > > Interesting that you feel you need parity. Oops. There I was open to an missunderstanding. I will not be using the 9th bits for parity. What I will be using them for, is 18 or 36 bit wide RAM. After PDP8 and PDP11 I would like do go to an PDP1 or PDP10, which were 18 and 36bit data bus CPUs. A board which provides 18 or 36 bits, with the board designers assumption that it will be used for parity, would accidently solve my problem, by using the parity bits as additional data bus width. That is why the board would have to be designed for generation/checking in the FPGA, so I get 18/36 bits into the FPGA. > > I am looking for: 1-16 MByte+parity RAM (preferably 36 or 18 bit, if > > not then 32 or 16), IO analog hardware for: RS232, EIDE harddisk, > > preferably also PC-AT or PS/2 Keyboard and VGA video, ideally also > > Ethernet (not to be used for quite a while, so it may be missing from > > first board). Small addition: alternative to VGA video I would also accept BAS b&w TV video. That seems to actually be what VT05/VT52/VT100 used. Also alternatively I would accept keyboard and video on an separate card, so only RS232, IDE and possibly Ethernet need to be on board. > The next board I build will likely have up to 32 MB of SDRAM. But I > don't think anyone makes an 18 bit wide version. If they do, that could > be used. So I will have to go to FP or EDO DRAMs (both of which I have seen in 9bit and 36bit. > BTW, these days 32 MB is a single SDRAM chip! 256Mbit chips. Were only a question of time. I am typing this on 8*64Mbit. > I am pretty sure that SyncSRAM comes in parity widths, but that is only > slightly more dense than standard async SRAM. I believe it can be found > in 1 MB or maybe 2 MB chips at this time. Assuming 9bit wide, that would make 4 for 36bit, so 4MByte, enough. Given how little RAM old computers had, I may end up using SRAM, and saving the work of implementing DRAM refresh. > So I could not fit 16 MB on a PC/104 board with all the other circuitry. Oh, you want it _that_ small. :-) -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 26418
Hi Stuart, I asked the same question awhile back & got a very comprehensive answer from Austin Lesea of Xilinx. try searching back thru' this newsgroup archives or send him an email. cheers, mark harvey. Stuart J Adams <sja@world.std.com> wrote in message news:G2F1o5.DB3@world.std.com... > Anyone know if the Xilinx Virtex/Spartan II > DLL's will work with Spread Spectrum input > clocks ?? > > -- Stuart >Article: 26419
> only need very basic pci functionality, enough to control a pci ethernet > card, with dma). I don't know exactly what you mean by 'very basic PCI functionality'. PCI can be implemented as a target only or target/master. Typically, 'very basic' in PCI land means target only. If the PCI Ethernet card supports master, then you probably can do what you want with your PCI interface supporting target only. There are multiple 'levels' of target support also. There is target and target burst. You probably want to be able to support target burst, unless your data rate is quite slow. A simple target in an FPGA is pretty easy, burst gets quite a bit more complicated, and master (which can also support burst or no burst) is quite a bit more complicated.Article: 26420
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I think : so... People have said, "what if the plan is played out and no : one sends you the money? So what! What are the chances of that : happening when there are tons of new honest users and new honest : people who are joining the internet and newsgroups everyday and are : willing to give it a try? Estimates are at 20,000 to 50,000 new : users, every day, with thousands of those joining the actual : internet. Remember, play FAIRLY and HONESTLY and this will really: work. ------------------------------------------------------------------------ Follow Ups: •Re: Attention Carlton Sheets Graduates! Dynamic Results Vincent 01:00:52 9/21/98 (0) •Re: Attention Carlton Sheets Graduates! Jan 18:06:37 9/13/98 (4) •IT'S ALMOST LIKE MAGIC!!!!!!!!!!!!!!! LEE 19:41:33 9/15/98 (2) •Re: IT'S ALMOST LIKE MAGIC!!!!!!!!!!!!!!! PAUL JOLLY 09:41:57 9/29/98 (0) •Re: IT'S ALMOST LIKE MAGIC!!!!!!!!!!!!!!! olatutu akinyelure 17:15:54 9/24/98 (0) •IT'S ALMOST LIKE MAGIC!!!!!!!!!!!!!!! LEE 19:39:53 9/15/98 (0) •Re: Attention Carlton Sheets Graduates! Jon Morris 19:29:43 9/09/98 (0) •Re: Attention Carlton Sheets Graduates! Jon Morris 19:18:00 9/09/98 (0) ------------------------------------------------------------------------ Carlton Sheets Graduates! Dynamic ResuArticle: 26421
I also had some weird system error during the compiles of 10K30, something to do with "fitme.C". Forgot the details, but I was able to get rid of this error by removing Quartus compile options in MaxPlus. Good Luck. LS Gary Cook <gary_cook@ntlworld.com> wrote in message news:39DCFE2C.82E5AF94@ntlworld.com... > Running Maxplus 9.64 and am having problems getting > internal errors during fitting ... sometimes during > partitioner and even 1% through netlist compiler. It's > not consistant at all ... I can run fine for a while and > then bang! all of a sudden I can't compile a thing. > Altera support aren't much help and the web-site mentions > a similar error but doesn't give much help either ... > just wondering if anyone here's got any info that could > help... > > not sure if it's an os thing ... running it on nt and get no > problems, running on win98 and get problems ... ??? > > Cheers, > > Gary Cook. >Article: 26422
Neil Franklin wrote: > rickman <spamgoeshere4@yahoo.com> writes: > > Interesting that you feel you need parity. > > Oops. There I was open to an missunderstanding. > > I will not be using the 9th bits for parity. What I will be using them > for, is 18 or 36 bit wide RAM. After PDP8 and PDP11 I would like do go > to an PDP1 or PDP10, which were 18 and 36bit data bus CPUs. > > A board which provides 18 or 36 bits, with the board designers > assumption that it will be used for parity, would accidently solve my > problem, by using the parity bits as additional data bus width. That > is why the board would have to be designed for generation/checking in > the FPGA, so I get 18/36 bits into the FPGA. I understand. > Also alternatively I would accept keyboard and video on an separate > card, so only RS232, IDE and possibly Ethernet need to be on board. I expect this will be best done on a separate board. When you say you will "accept" this "BAS" video, what exactly does this mean? Are you looking to redititize the video or just combine the video with your own generated video? > > The next board I build will likely have up to 32 MB of SDRAM. But I > > don't think anyone makes an 18 bit wide version. If they do, that could > > be used. > > So I will have to go to FP or EDO DRAMs (both of which I have seen in > 9bit and 36bit. No, I would not recommend that. Or you will end up with the same problem that you would have trying to build a PDP11 using the original parts. FP and EDO DRAM will be all but gone in another year to two. Instead you will need to use x4 configurations to build a x36 bank of memory. I believe the last time I checked, the 128 Mbit SDRAMs were the cheapest per bit. The 256 Mbit parts are not at bit price parity yet. So you could use 9 chips and get 32 MWord of memory. Or if you really don't need all that RAM, you can use 5 chips of x4 and get 32 Mword of your 18 bit memory plus two bits spare or 5 chips of x8 and get 16 MWord of 36 bit memory and have 4 bits extra. Actually, I believe I worked on a machine once that had 40 bit memory. It used 32 data bits plus an 8 bit ECC. > > BTW, these days 32 MB is a single SDRAM chip! > > 256Mbit chips. Were only a question of time. I am typing this on 8*64Mbit. > > > I am pretty sure that SyncSRAM comes in parity widths, but that is only > > slightly more dense than standard async SRAM. I believe it can be found > > in 1 MB or maybe 2 MB chips at this time. > > Assuming 9bit wide, that would make 4 for 36bit, so 4MByte, enough. Or it comes in x18 bit or x36 bit as well. They use TQFP packages at 100 pins, IIRC. Small, but high IO count. They also come in BGAs. But you won't want to build your own board with BGAs. > Given how little RAM old computers had, I may end up using SRAM, and > saving the work of implementing DRAM refresh. > > > So I could not fit 16 MB on a PC/104 board with all the other circuitry. > > Oh, you want it _that_ small. :-) PC/104 is what we build at Arius, Inc. The processor board I will be building that uses the TMS320VC5510 fixed point processor will have Flash, SyncSRAM and one chip of SDRAM for mass storage along with the several FPGAs, IO connectors and the two sites for IO daughterboards. So it is a very full board. If you are trying to tie FPGAs to dense memories, then you will have a hard time trying to use wire wrap. I don't think they have put anything above 4 Mbit DRAM or 256 Kbit SRAM in DIP. But I am not sure, so keep looking. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26423
> I'm a final year undergraduate doing a project on implementing a PWM > circuit on a Xilinx FPGA for driving an induction motor. Somehow I need > to be able to generate a digital sine wave to compare with a triangular > carrier wave to generate the PWM. Someone suggested programming an > EEPROM with a look-up table of Sine values, but this doesn't seem a > very flexible way of doing it. > > Can anyone help, with a reference or anything else? Any suggestions on > any other part of the project? > > Thanks, > > Andrew F. > Bristol Uni. > You will need a non volatile memory (EEPROM) to store the configuration anyway. If you need flexibility and if your FPGA is XC4000 or 5200 or low end spartan, then you might be able to fit the Atmel FPSLIC which includes an AVR processor which can change things in FPGA SRAM. It is pin compatible for most devices. Look at www.atmel.com/atmel/products/prod39.htm It also contains up to 12 kB of 8 bit memory available to the FPGA, so you can get some buffering. (The SRAM is dual port so it can be written by the processor) -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel SwedenArticle: 26424
In article <o7OF5.75745$O95.6492260@typhoon.tampabay.rr.com>, "S. Ramirez" <sramirez@deleet.cfl.rr.com> wrote: > Then try using VHDL to program your 22V10s! > -Simon Ramirez, Consultant > Synchronous Design, Inc. Which tools can be used to program a 22V10 in VHDL? I could not find any compiler and fitter for a PAL. Thank you. -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Before you buy.
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