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On Fri, 13 Oct 2000 15:35:31 +0100, "Brendan Lynskey" <brendan.lynskey@pace.co.uk> wrote: >In the ATA spec., (for IDE hard disk drives), a parallel implementation of a >simple CRC generator polynomial is given. > >Does anyone out there know how the serial->parallel conversion is done? > >Cheers, > > Bren I'm not quite sure what you mean. If you mean 'how do you convert a serial CRC algorithm into a parallel one', then it's pretty straightforward. If you imagine that you have a, say, 16-bit serial generator, and then shift in, say, 8 bits, you can derive a function for the new value of the generator after the 8 bits have been shifted in. You have 16 functions, one for each generator bit, and you just implement all these in parallel, so that you get the result after one clock instead of 8. I think I've got a couple of references somewhere if it would be useful. Easics has a tool which does it automatically for you (http://www.easics.com/webtools/crctool). EvanArticle: 26376
The merger between AOL & Time Warner will be approved -
BUT - the F.C.C. is going to require some form of open access.
The question is - open access for WHOM? Will the conditions
protect ONLY THE CORPORATIONS or will they also protect YOU
the END USER?
This is what AOL and Time Warner have to say about censorship
and speed capping:
IF TIME WARNER DETERMINES THAT THE SUBSCRIBER HAS FAILED TO
COMPLY WITH THE SERVICE'S STANDARDS OF CONDUCT OR LIMITS ON
BANDWIDTH UTILIZATION, TIME WARNER MAY SUSPEND SUBSCRIBER'S
ACCOUNT. TIME WARNER COMMUNICATIONS SHALL HAVE THE SOLE AND
UNREVIEWABLE RIGHT TO DETERMINE WHETHER CONTENT VIOLATES
THESE STANDARDS.
DID YOU KNOW:
These are the things that Colette Lantelme, Security Administrator
of Road Runner, claims are against the Road Runner Acceptable Use
Policy.
1. Posting a message on any "For Sale" message board.
2. Listing a product on any Ebay, Ubid, or similar service. (Boy, is
EBAY gonna be PISSED!)
3. Announcing a job availability.
4. Replying to a job availability.
5. Mentioning that the user had tried any product and found
it satisfactory - or unsatisfactory.
6. Posting a message to any "personals" board.
7. Asking a user for a date.
8. Calling attention to any commercial or non-commercial
website, including personal websites provided as part
of the purchase price of the service sold by Time-Warner.
9. Calling attention to any IRC chat channel.
DID YOU KNOW:
AOL cancelled the account of the President of the Chemically
Disabled Americans - they said it was a commercial usage! The
president ran it from his bedroom. As a public service. His
comment expressing his outrage is contained in the F.C.C. file.
Want to say that Al Gore can't be elected because he is a democrat?
No problem! Want to say that Leiberman can't be elected because he
is Jewish? BANNED FROM AOL!
A very small effort on your part can well induce the F.C.C. to
outlaw this censorship and Speed Capping, and protect YOU as well
as the corporations. You have some powerful allies; Consumer's Union,
Disney, and many commercial software companies. Even the Attorney
General of the State of Connecticut is on YOUR side - you may read
their petitions at the link below.
But YOU MUST HELP!
You can F.I.L.E YOUR C.O.M.M.E.N.T IN THE O.F.F.I.C.I.A.L C.A.S.E FILE!
---> This is NOT merely a EMAIL message which will be ignored <---
Any response which you file will be an OFFICIAL document included in
the F.C.C. FILINGS!
It will appear in the OFFICIAL CASE FILE as a comment
read by ALL THE ATTORNEYS who are participating in the action, as well
as ALL THE F.C.C. C.O.M.M.I.S.S.I.O.N.E.R.S! It will remain there
FOREVER as part of the O.F.F.I.C.I.A.L R.E.C.O.R.D of the AOL - Time
Warner merger! With YOUR name on it!
Since this internet campaign started, approximately 250 comments have
been received by the F.C.C from individuals. (Some are funny as hell!)
We need twice that!
The FCC is on the verge of requiring the protections this letter asks
for. Your letter might PUSH THEM OVER THE EDGE and make the internet
a BETTER PLACE for EVERYONE, INCLUDING YOU!
PLEASE - can you HELP PROTECT IRC and USENET? SEND the SAMPLE COMMENT
to the F.C.C!
MAKE A DIFFERENCE TO USENET AND IRC! This letter WILL MAKE A DIFFERENCE
if there are enough of them received by the FCC. If at least 500
letters are received, we can probably count on the FCC to take decisive
action to prohibit both censorship and speed capping - and to protect
the users, not merely the corporations.
GET A CHAIN RESPONSE STARTED! I can do only so much. I can only post
to so many newsgroups - I can't do it alone. WE ALL NEED YOUR HELP!
Copy this message and post it to (at least) 3 newsgroups where it does
not appear! Then, Send this message by EMAIL to (at least) 5 friends!
If everyone does that, we can FLOOD THE F.C.C. with comments and THEY
WILL LISTEN!
The major ccorporations and the politicians are coonducting this merger
on their terms, for their benefit, and giving no thought whatsoever to
the users. They are all fighting over our dollars, but do they give any
concern whatsoever to us? Does a fish ride a bicycle?
They believe that the internet, which WE, not them, made great, is now
too valuable to be left the users. Their attitude is, "let them comment,
they don't count, they are not rich corporations, they are merely poor
users. Will YOU let them get away with this?
They can ignore 250 users. They can't ignore thousands of users.
LET THE F.C.C. know that THE INTERNET DOSEN'T STAND FOR ANY BULL! Tell
the F.C.C. I'M MAD AS HELL AND I'M NOT GONNA TAKE IT ANYMORE!
The future of USENET and IRC depends on the FCC forcing all ISP's
starting with Time Warner and AOL to recognize free speech and fair
marketing practices. PLEASE HELP!
TO FILE YOUR COMMENT WITH THE F.C.C:
1. Copy the letter to a file. You can put it on your letterhead
with MS Word or just use a text file. You can make any change to
the letter you want, or add any comment you have. CHANGES ARE GOOD!
They show you READ THE LETTER and REALLY CARE! If you had a bad
experience with AOL or Time Warner PUT IT IN!
2. go to:
https://gullfoss2.fcc.gov/cgi-bin/websql/prod/ecfs/upload_v2.hts
(This is the official FCC page where electronic filing of petitions
is accomplished)
3. Fill out Cover sheet
Put your name, Address, Email address, and all other required
information on the form. (Remember this is an OFFICIAL FILING so
the FCC requires this information. It is not published unless you
put it in the letter as well as the form)
Proceeding is
00 - 30
(Leave out the spaces, they are there to get by the spam filter.
Put in the -)
(this is VERY IMPORTANT, it is the case number of the AOL TIME
WARNER APPLICATION for merger. If you get it wrong, your comment
WILL NOT BE FILED!)
4. Send Cover Sheet.
5. After you send the Cover Sheet, THEN select the filename of the
letter you are sending, and send that.
6. After you send the file, you will receive an official
confirmation of the filing from the FCC.
7. You can TYPE a comment instead of sending this sample comment, but
DON'T PASTE THE SAMPLE COMMENT into the Short Comment box - it
DOESN'T FIT!
Comment will appear for all to read in about 4 hours
(but won't appear after business hours or on the weekend.)
8. If you want to see your letter, or read the other submissions,
other letters, the AOL petition, the Disney or Consumer's Union
objections, etc, here is the URL - Its long! Put in the case
number, 00 - 30 (no spaces) and nothing else.
https://gullfoss2.fcc.gov/cgi-bin/websql/prod/ecfs/comsrch_v2.hts?ws_mode=retrieve_list&id_proceeding=00-30&start=1
IF YOU LIVE N A FOREIGN COUNTRY and wish to make a comment (This is a
world wide problem) the Cover Sheet will not accept your address. You
can do this: Enter your real name and address including country in
the address lines, but in the STATE box put CA and in the ZIP (first
field) put 90001. Ignore the 2nd zip field. Ignore the 2nd form, and
TYPE your SHORT COMMENT in the 3rd form. Please identify the country
you live in the message. Don't use the sample letter supplied
because it isn't appropriate for non-US residents.
***>Remember the FORM INFORMATION will NOT appear, only the letter.
NOTE: There is NO WORD WRAPPING on the letter below, to make it
easy for you to format so it may be hard to read until you copy it,
depending on your news reader.
SAMPLE MESSAGE
------------cut here----------------------------------------------
TO THE COMMISSIONERS:
Is it ever in the public interest for a private corporation to control what the average citizen can say? Is it ever in the public interest foe a private corporation to determine what speech the private citizen can access?
It is often said that "The freedom of the press is limited to he who owns one." What we have here is a more diabolical situation. The internet gatekeeper not only owns the press, he owns the newsstand. While any citizen can concevably purchase a press and distribute his opinions, no citizen distribute his speech if the gatekepper simply refuses to allow it to propagate to the internet at all.
Please understant exactly what we are talking about. AOL institutes a "teen filter." At this instant, AOL determines that the Republician National Committee is suitable for teens, but the Democratic National Committee website is not.
Do you REALLY want the President of AOL to have veto power on which Government information is suitable for their customers? Today it is merely teens - tomorrow, who knows? There is no doubt that the result will be that the President of AOL, whether or not he chooses to use it, will have more power in formulating public opinion than the President of the United States. And as history tells us, if he has the power to use it, sooner or later he will.
Time Warner's current policy is as follows:
IF TIME WARNER DETERMINES THAT THE SUBSCRIBER HAS FAILED TO COMPLY WITH THE SERVICE'S STANDARDS OF CONDUCT OR LIMITS ON BANDWIDTH UTILIZATION, TIME WARNER MAY SUSPEND SUBSCRIBER'S ACCOUNT. TIME WARNER COMMUNICATIONS SHALL HAVE THE SOLE AND UNREVIEWABLE RIGHT TO DETERMINE WHETHER CONTENT VIOLATES THESE STANDARDS.
Time Warner, and AOL, which has a similar and even more restrictive policy, claims to have the right to terminate anyone, at any time, for any reason.
Gentlemen, at this moment you are depending on the "good faith" of AOL and Time Warner to protect our most valuable heritage, our freedom of speech. Have you asked the City of Daytona Beach or the Town of Carey what their opinion is of Time Warner's good faith? Are you really willing to let your heritage depend on this good faith?
Don't try to tell me that AOL and Time Warner close that gate only on "bad" speech, the pornographers, the hate-mongers, the "spammers," and gives the rest of us "nice" people free reign to post "acceptable" messages. It is well known what these companies find unacceptable - anything whatsoever that rubs them, or anyone else, the wrong way.
Gentlemen, you cannot give a private corporation the power to prohibit only "bad" speech; you can only give it the power to prohibit ALL speech. And history tells us most definitely that if they have that power, sooner or later they will certainly use it.
You cannot be Pilot - you cannot merely wash your hands and leave the problem to "market forces." You can only, by your action, prohibit this danger, or by your inaction, insure that, sooner or later, all speech on the internet will be at the mercy of the President of AOL. Including, of course, yours.
Is this REALLY what you want to do?
Thank You for your attention.
----> YOUR NAME <----
urtwmfbeugehhhqergphtwlulkjphhwxzglwouonzpzzejkecxxxysiqkdgwrjrijrub
Article: 26377I would use the shift-register feature of the LUTs ( new in Virtex and all later versions ) to modify the LUT content. You can shift the 16-bit content "sideways" into the LUT using SRL16 . Peter Alfke, Xilinx Applications Lars wrote: > Hi everybody! > > In my design I have to implement a couple of 8x8 bit multipier. One coefficient is constant. > Since I have to change this constant coefficient in runtime (partial reconfig. of the Virtex chip) the easiest way would be a implementation just with LUTs (so I know the exact location of the LUTs and can change them). Has somebody an idea how I can handle this?? > > Thank you! > > LarsArticle: 26378
bob elkind wrote: > > I have clients who occasionally "need" palasm, to support an old design. > > Anyone have a suggestion for where one might find/buy/download palasm ? > > Originally, it was a freebie that AMD distributed to encourage > design-ins > of their PALs... Um, I think it's still available on the Lattice/Vantis web site. It doesn't like NT very much, tho'. Lattice also has their ispDesignExpert stuff, which is ABEL, and works fine for their small PALs. (I recently used it when I added a 16V8 to a design.) I just hate trying to remember syntax for forty-seven different languages! -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26379
rickman writes:
> I assume you realize this was not my comment you were responding to.
Yup.
>> I'm in a privileged position though -- most Handel-C users don't know
>> how the source is translated into logic. I do have a very good idea,
>> and just like writing C for a CPU, I bear it in mind when coding.
> Then why could you not figure out why the C HDL result was slower than
> the AHDL?
Indeed. I've got a good idea how Handel-C works because I worked on a
similar compiler called Handel about 6 years ago.
The AHDL source defined cliques, into which logic is grouped. Handel-C
doesn't have that facility. I didn't try compiling the AHDL without
cliques.
I suspect that no. 1 reason was simply that the AHDL had a lot of speed
optimisation done to it. On an FPGA, rearranging a register here and
there makes a lot of diffence sometimes.
That's a lot harder to do in Handel-C -- everything takes a cycle.
Unlike VHDL, you don't say "this register takes this value NOW", you say
"this register takes this value at the end of the current cycle".
It is actually not at all painful to work with, though there are
occasions when a VHDL-style signal would be handy. However, it makes
those slight rearrangements of registers very difficult, to the extent
that doing so turns your code into something unreadable. I.e. it
defeats the point of using Handel-C at all.
A trade off. (I think the next version of Handel-C adds signals, but I
haven't looked at it yet).
I should do another comparison sometime. The newer chips and newer
tools from Altera ("Quartus fitter" in Maxplus2) are compiling my
Handel-C to something faster than I expected.
-- Jamie
Article: 26380Uwe wrote: > > Hi, > > i use a Xilinx fifo and devider core in my design and want to simulate it > functionally. > What have i done? > 1. I compiled the XilinxCoreLib with ModelSim > 2. include all parts of the .VHO file also the configuration > but while compiling the top level ModelSim give the folowing Warnings: [snip the usual warnings] > So i'm not sure if the configuration is ok Note: The "synopsys translate_off" directive needs to be BEFORE the configuration statement because FPGA Express doesn't work with configurations. (It shouldn't affect simulation, tho'.) > configuration cfg_SHC of U2 is > for SHC > > -- synopsys translate_off > for all : fifo_1023_32 use entity > XilinxCoreLib.async_fifo_v2_0(behavioral) > generic map( [snip] > end for; > > for all : div_21_14si1 use entity XilinxCoreLib.dividervht(behavioral) > generic map( [snip] > end for; > > -- synopsys translate_on > end for; > end cfg_SHC; -- put the synopsys translate_on here at the end of the configuration. You also need a configuration in your higher-up code. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26381
Caleb Hess wrote: > > We're finding that occasionally the Foundation Express schematic editor will > refuse to read or write a file if the name is more than 8 characters. The > strange thing is that sometimes it works OK, other times it fails. The > software is 2.1i, with and without patches, on WinNT and Win98. Anyone have > an explanation for what's happening? Sounds like it's not a Win32 application. And that software came out when, 1999? You'd think that since Windows 95 came out (in 1995) that they'd get their shit together. But you'd be wrong. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26382
Is there a way to perform post-route(timing) simulation on ModelTech Vsim using outputs derived from Xilinx's old XACT place/route tool set? It appears that the XACT tools only contain scripts to prepare timing simulation for Synopsys' simulator not Modeltech's Vsim. Thanks in advance...Article: 26383
Keith R Williams writes: >> You're aware of attempts to translate Java into hardware aren't you? :-) > No. A JVM, yes. Java, no. Search for the "Harpoon" project. Compiling Java into hardware. > This is *not* software. It will be :-) > I do believe the hardware types are the ones trying to do the > hardware JVM. Hmm, would it then be called a JHM? ;-) -- JamieArticle: 26384
Hi, the Virtex and Spartan devices from Xilinx can operate in LVTTL mode and this mode is 5V tolerant on inputs and the output operates at 3,3V that is over the logic High Level of TTL until you have not to drive too much inputs.(Fan Out). reards Uwe jean-francois hasson <jfhasson@club-internet.fr> schrieb in im Newsbeitrag: 39E73E13.F86B5DA5@club-internet.fr... > Hi, > > I am working on a design involving an FPGA which could be either a > Xilinx or an Altera. I know Altera is about to propose a 5V compatible > APEX without any glue outside and I was wondering if Xilinx has a > similar part in the Virtex family. > > Thanks in advance for your time and information. >Article: 26385
rickman wrote: >> Me: > > The point, of course, is that the synth tool may or may not do what you > > expect regarding the flop's clock enable. And it probably doesn't > > matter, assuming the logic is correct. > > Oh, but it does matter, very much if you want to run at >50 MHz with > SPIRiseClkEn driving the CE to boost your top clock speed. This is a > common technique to operate much of a design at multiple clock cycles > rather than in a single cycle. Often only a small portion of a design > needs to run at the full rate and this lets you back off on the timing > constraints for the other sections. Oh, I understand that. > I don't have the full tools yet, so I can't test it. But I remember from > my previous experience with FPGA Express that if you want a CE, you need > to put in in a separate IF with no ELSE clause as the outermost IF, just > inside the clock test IF. Did that make sense? > But of course I need to test that with the current tools. Actually, I > seem to remember that I had a lot of trouble getting Express *not* to > use the CE. I think it may have used the CE on *every* IF that had no > ELSE. It does make sense, but I don't think that's exactly what FPGA Express does. I think I did some tests, and it turns out that FPGA Express does whatever it does to minimize the logic. I'll have to try test cases with both FPGA Express and Synplify. Here's a thought: assuming your clock-enable signal is registered, you should be able to set your timing constraint endpoints from that register to the CE'd register. > I chose to include the CTS in the same process since the logic is > related and I think a separate section for a single FF is not always > warranted. I am not worried about the startup state of CTS since it > follows the state of the register. So it will not have a problem being > unknown on startup in the simulation. The default in a chip is reset. > But really, I forgot... thanks. I don't think the synthesis tools care whether you put everything into one process, or split it up. I usually go for "clarity of code." The only thing about forgetting to reset a flop is that if you want to use GSR, the synthesis tool will complain that not all of your flops are reset by GSR and it won't be inferred. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26386
> I am working on a design involving an FPGA which could be either a > Xilinx or an Altera. I know Altera is about to propose a 5V compatible > APEX without any glue outside and I was wondering if Xilinx has a > similar part in the Virtex family. Yes, it's called a Virtex. Virtex-E is not 5V compatible. Alun CamdigitalArticle: 26387
On Fri, 13 Oct 2000 16:53:39, jean-francois hasson <jfhasson@club-internet.fr> wrote: > Hi, > > I am working on a design involving an FPGA which could be either a > Xilinx or an Altera. I know Altera is about to propose a 5V compatible > APEX without any glue outside and I was wondering if Xilinx has a > similar part in the Virtex family. Virtex (and I suppose Spartan-II ?) is 5V tollerant. However, it won't drive 5V CMOS reliably without help on the up level. Any version of TTL (or HCT) is fine though. Virtex-E is *not* 5V tollerant. Ooops! It's a good thing I had time to put in a quick-switch on the one 5V CMOS input before I turned the board for the Virtex-E spin. ;-) ---- KeithArticle: 26388
Hi, I'm having trouble using this clk'event in VHDL. I'm using it for a rising edge condition, i.e. if (clk'event and clk='1') then ... etc. In my code, I have several different clocks, i.e. if (clk1'event and clk1='1') then ... etc. if (clk2'event and clk2='1') then ... etc. if (clk3'event and clk3='1') then ... etc. and so on. The syntax checks OK, but when I synthesize, I get this error: Error: This use of clock edge specification not supported It synthesizes fine with less than 3 'events statments like those, but any more and I get the error. Is this a device limit? Is there a way around it? I'm using Xilinx Foundation 3.1i software and coding for an XC95108 CPLD. Thanks for any help, JamesArticle: 26389
Hello! I have a follow up question. Do you know of any 3.3V <-> 5V integrated translaters around? I can do the translation with a few discrete componentents but I rather use a IC. Any hints??? / Jonas On Fri, 13 Oct 2000 20:19:39 GMT, krw@attglobal.net (Keith R. Williams) wrote: >On Fri, 13 Oct 2000 16:53:39, jean-francois hasson ><jfhasson@club-internet.fr> wrote: > >> Hi, >> >> I am working on a design involving an FPGA which could be either a >> Xilinx or an Altera. I know Altera is about to propose a 5V compatible >> APEX without any glue outside and I was wondering if Xilinx has a >> similar part in the Virtex family. > >Virtex (and I suppose Spartan-II ?) is 5V tollerant. However, it >won't drive 5V CMOS reliably without help on the up level. Any >version of TTL (or HCT) is fine though. > >Virtex-E is *not* 5V tollerant. Ooops! It's a good thing I had >time to put in a quick-switch on the one 5V CMOS input before I >turned the board for the Virtex-E spin. ;-) > >---- > Keith >Article: 26390
Then try using VHDL to program your 22V10s!
-Simon Ramirez, Consultant
Synchronous Design, Inc.
> Um, I think it's still available on the Lattice/Vantis web site. It
> doesn't like NT very much, tho'.
>
> Lattice also has their ispDesignExpert stuff, which is ABEL, and works
> fine for their small PALs. (I recently used it when I added a 16V8 to a
> design.) I just hate trying to remember syntax for forty-seven
> different languages!
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
>
Article: 26391rickman wrote: > > What did IDT do that you consider SPAM? Unsolicited bulk email about their latest products totally unrelated to the chip sample I have requested on their web. There was no opt-out available anywhere in the registration nor in the email. > Rick "rickman" Collins K. C. LeeArticle: 26392
James,
If you look at the XC95108 data sheet, page 2, Figure 2, XC95108
Architecture, it shows 3 IO/GCK lines coming in at the left and going to the
function block/macrocells. It should synthesize correctly for clk1, clk2
and clk3 but not more than. You said "It synthesizes fine with less than 3
'events statments..." I take it that it is giving you an error if you try
to synthesize with clk1, clk2 and clk3? If so, then this is an FPGA Express
error. If you meant "less than or equal to," then you know that you reached
the device limit.
By the way, the following statement:
if (clk1'event and clk1='1') then ... etc.
can be replaced by the following statement to save you some typing:
if rising_edge (clk1) then ... etc.
Good luck.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"James S." <ads@begone.com> wrote in message
news:39e76e1e$0$95121$45beb828@newscene.com...
> Hi,
>
> I'm having trouble using this clk'event in VHDL. I'm using it for a
rising
> edge condition, i.e.
>
> if (clk'event and clk='1') then ... etc.
>
> In my code, I have several different clocks, i.e.
>
> if (clk1'event and clk1='1') then ... etc.
> if (clk2'event and clk2='1') then ... etc.
> if (clk3'event and clk3='1') then ... etc.
>
> and so on. The syntax checks OK, but when I synthesize, I get this error:
>
> Error: This use of clock edge specification not supported
>
> It synthesizes fine with less than 3 'events statments like those, but any
> more and I get the error. Is this a device limit? Is there a way around
> it?
>
> I'm using Xilinx Foundation 3.1i software and coding for an XC95108 CPLD.
>
> Thanks for any help,
> James
>
>
>
Article: 26393Jonas Thor <NoSpamthor@sm.luth.seNoSpam> wrote: >Hello! > >I have a follow up question. Do you know of any 3.3V <-> 5V integrated >translaters around? I can do the translation with a few discrete >componentents but I rather use a IC. Any hints??? You can use some TTL non-inverting buffers for this purpose. You need to power the TTL chip with something close to 5V. Check out these chips from National semi: MM54C902 or MM54C904 at http://www.national.com/ds/MM/MM54C901.pdf Muzaffer http://www.dspia.comArticle: 26394
I'm a student doing my final year project. My task is to build a sinusoidal PWM generator on an FPGA to control an induction motor. I have been told I have to digitally compare a sine wave with the triangular modulating wave to produce the PWM. My problem is how to generate the digital values for the sine wave. Someone suggested programming an EEPROM with sine wave values, but this doesn't seem very flexible to me. Can anyone think of a better way of generating the Sine wave (Or anything else helpful?) Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26395
I'm a final year undergraduate doing a project on implementing a PWM circuit on a Xilinx FPGA for driving an induction motor. Somehow I need to be able to generate a digital sine wave to compare with a triangular carrier wave to generate the PWM. Someone suggested programming an EEPROM with a look-up table of Sine values, but this doesn't seem a very flexible way of doing it. Can anyone help, with a reference or anything else? Any suggestions on any other part of the project? Thanks, Andrew F. Bristol Uni. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26396
Workshop on Cryptographic Hardware and Embedded Systems 2001
(CHES 2001)
http://www.chesworkshop.org
Paris - France
May 13 - 16, 2001
First Call for Papers
General Information
The focus of this workshop is on all aspects of cryptographic
hardware and embedded system design. The workshop will be a forum of
new results from the research community as well as from the industry.
Of special interest are contributions that describe new methods for
efficient hardware implementations and high-speed software for
embedded systems, e.g., smart cards, microprocessors, DSPs, etc. We
hope that the workshop will help to fill the gap between the
cryptography research community and the application areas of
cryptography. Consequently, we encourage submission from academia,
industry, and other organizations. All submitted papers will be
reviewed.
This will be the third CHES workshop. The first workshop, CHES '99,
was held at WPI in August of 1999 and was very well received by
academia and industry. There were 170 participants, more than half of
which were from outside the United States. The second workshop, CHES
2000, was also held at WPI in August of 2000 and had an attendance of
180.
The third workshop, CHES 2001, will be held in Paris in May of 2001. The
topics of interest include but are not limited to:
* Computer architectures for public-key cryptosystems
* Computer architectures for secret-key cryptosystems
* Reconfigurable computing and applications in cryptography
* Cryptographic processors and co-processors
* Modular and Galois field arithmetic architectures
* Tamper resistance on the chip and board level
* Smart card attacks and architectures
* Efficient algorithms for embedded processors
* Special-purpose hardware for cryptanalysis
* Fast network encryption
* True and pseudo random number generators
* Cryptography in wireless applications
Instructions for Authors
Authors are invited to submit original papers. The preferred submission form
is by electronic mail to ches@ece.orst.edu. Papers should be formatted in
12pt type and not exceed 12 pages (not including the title page and the
bibliography). The title page should contain the author's name, address
(including email address and an indication of the corresponding author), an
abstract, and a small list of key words. Please submit the paper in
Postscript or PDF. We recommend that you generate the PS or PDF file using
LaTeX, however, MS Word is also acceptable. All submissions will be
refereed.
Only original research contributions will be considered. Submissions must
not substantially duplicate work that any of the authors have published
elsewhere or have submitted in parallel to any other conferences or
workshops that have proceedings.
Important Dates
Submission Deadline: February 15th, 2001.
Acceptance Notification: March 31st, 2001.
Final Version due: April 21st, 2001.
Workshop: May 13th - 16th, 2001.
NOTE: The CHES dates May 13th - 16th are Sunday - Wednesday
succeeding Eurocrypt 2001 which ends on Thursday, May 10th.
Mailing List
If you want to receive emails with subsequent Call for Papers and
registration information, please send a brief mail to ches@ece.orst.edu.
Program Committee
Ross Anderson, Cambridge University, England
Jean-Sebastien Coron, Gemplus, France
Kris Gaj, George Mason University, USA
Jim Goodman, Chrysalis-ITS, Canada
Anwar Hasan, University of Waterloo, Canada
Peter Kornerup, Odense University, Denmark
Bart Preneel, Katholieke Universiteit Leuven, Belgium
Jean-Jacques Quisquater, Universite Catholique de Louvain, Belgium
Christoph Ruland, University of Siegen, Germany
Erkay Savas, cv cryptovision, Germany
Joseph Silverman, Brown University and NTRU Cryptosystems, Inc., USA
Jacques Stern, Ecole Normale Superieure, France
Colin Walter, Computation Department - UMIST, U.K.
Michael Wiener, Entrust Technologies, Canada
Organizational Committee
All correspondence and/or questions should be directed to either of the
Organizational Committee Members:
Cetin Kaya Koc
(Publications Chair)
Dept. of Electrical & Computer Engineering
Oregon State University
Corvallis, Oregon 97331, USA
Phone: +1 541 737 4853
Fax: +1 541 737 8377
Email: Koc@ece.orst.edu
David Naccache
(Program Chair and Local Organization)
Gemplus Card International
34 Rue Guynemer
92447 Issy les Moulineaux Cedex, FRANCE
Phone: +33 1 46 48 20 11
Fax: +33 1 46 48 20 04
Email: David.Naccache@gemplus.com
Christof Paar
(Publicity Chair)
Dept. of Electrical & Computer Engineering
Worcester Polytechnic Institute
Worcester, MA 01609, USA
Phone: +1 508 831 5061
Fax: +1 508 831 5491
Email: christof@ece.wpi.edu
Workshop Proceedings
The post-proceedings will be published in Springer-Verlag's Lecture Notes
in Computer Science (LNCS) series. Notice that in order to be included
in the proceedings, the authors of an accepted paper must guarantee to
present their contribution at the workshop.
Article: 26397Jonas Thor wrote: > Hello! > > I have a follow up question. Do you know of any 3.3V <-> 5V integrated > translaters around? I can do the translation with a few discrete > componentents but I rather use a IC. Any hints??? > > / Jonas > The best way is to use parts generically called ``QuickSwitch'' from the company that first made them [now owned by IDT]. These are basically a bunch of pass transistors that have the characteristic that the resistance increases as the voltage on the driving size approaches the device's VCC. In effect they clamp the output side to about VCC - 0.7. For our 3.3V conversion we power the 5V parts from a 3.9V supply. You can now get 3.3V versions which we are about to use in the same way to get LVTTL <-> SSTL2 conversion. These parts have the huge advantage that they add almost no delay - about 250ps or so - in the transition range of 0 -> 3.0V where Ron stays at about 10R. The best place to look for this stuff is probably Pericom's web site.Article: 26398
Anyone know if the Xilinx Virtex/Spartan II DLL's will work with Spread Spectrum input clocks ?? -- StuartArticle: 26399
In article <Pine.OSF.4.21.0010140556330.26553-100000@ece.wpi.edu>, Christof Paar <christof@ece.wpi.edu> wrote: > The focus of this workshop is on all aspects of cryptographic > hardware and embedded system design. The workshop will be a forum of > new results from the research community as well as from the industry. > Of special interest are contributions that describe new methods for > efficient hardware implementations and high-speed software for > embedded systems, e.g., smart cards, microprocessors, DSPs, etc. We > hope that the workshop will help to fill the gap between the > cryptography research community and the application areas of > cryptography. Consequently, we encourage submission from academia, > industry, and other organizations. All submitted papers will be > reviewed. Would a paper on a block cipher geared towards low end microcontrollers be suited for this conference? Tom Sent via Deja.com http://www.deja.com/ Before you buy.
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