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Two possibilities:
1) Make sure that you have requested "fast I/Os" in the global logic
synthesis options
1) Preset flops can't be merged into the I/Os in Flex devices. Use
either no reset at all or a clear.
martin@gubbins.demon.co.uk wrote:
> I've been banging my head against the Max+Plus2 fitter all day. I
> can't get some of my I/O's to meet a 7.5ns tco - which I have
> specified in the ACF file. It would appear that the routing delay
> from my mux to my output is too long. No problem I'll stick another
> DFF on the output of the mux to break the route into two.
>
> What does the fitter do? Slap the extra FF right next to the mux
> output FF in the same LAB. Neatly using the extremely fast local-LAB
> interconnect, but still having the same long route to the pin that I
> was trying to avoid!
>
> Aaargh! Anyone got any ideas on how to make the fitter do something
> sensible?
>
> The device is a 10KE100EBC356-1, MP2 v 9.6, using the Quartus fitter
> if it makes any odds...
>
> Any help greatly appreciated!
>
> Cheers,
> Martin
> Martin Thompson
> martin@gubbins.demon.co.uk
> http://www.gubbins.demon.co.uk/
--
Ken McElvain, CTO
Synplicity Inc.
(408)215-6060
Article: 23951On Mon, 17 Jul 2000 12:54:36, Keith Wootten <Keith@wootten.demon.co.uk> wrote: > Hi > > My present XCS40XL design takes about 25 minutes from editing to .bit > file generation. I'm using a 200MHz Pentium Pro with 64MB RAM and > Windoze 95. I wanna know how you're getting it so low! My design will take upwards of an hour on a PIII-650 and then another hour or with the "re-entrant router". I had to strip the design down to the bare-bones to get it to route at all. My DC setup stuff, much of the design, I had to do in shift-registers because it wouldn't route otherwise. BTW, 3.1i improved things considerbly, though it still take hours (and it is very unpredictable). > What sort of ballpark speed improvement could I get by using a faster PC > and/or more RAM? Has anyone run the same design on different machines? With 2.1i I found that it was CPU limited, at least with 256K or greater memory. The processing times scaled pretty lineraly between a 333MHz PII and a 650MHz PIII. I was rather surprised actually. > I need to balance run time improvements against the hassle of upgrading > my PC. Understood. I run my other design tools on my antique PII-333 (or on my laptop - depending) and have the PIII-650 sitting there to do PnR (it's the host for the target of the design, so it's not being used at the time). A super-fast system doesn't do a lot for Synplicity, in fact I've used my P5-120 laptop without too much agrivation, but a fast machine is critical for the Xilinx PnR tools. It's worth it to transfer files between two machines, even over a sneraker-net. ---- KeithArticle: 23952
Nick Young wrote in message ... >I am new to FPGA's and want to learn how to use them. This includes >designing, simulation and implementation. Can anyone tell me of a good >introduction/tutorial on the topic, (on-line if possible). >I am new to FPGA's and want to learn how to use them. This includes >designing, simulation and implementation. Can anyone tell me of a good >introduction/tutorial on the topic, (on-line if possible). Hi Nick, Burch Electronic Designs have some low cost kits that may be of interest for the implementation part of your learning. The kits are intended for real-world prototyping and for quickly trying out ideas in the lab with a basic and easy to use starting platform. However, they are also great starting platforms for student projects. We have Xilinx, Altera, Atmel, Actel and Lucent kits. Prices range from US$66 to US$89. Check out the kits at www.BurchED.com.au The Altera kit is popular for students, basically because the Altera Max+PlusII Baseline software, which works great with the kit, is freely downloadable from the Altera website. See a picture and specs of the BED-ALTERA-BASE+ kit at http://www.burched.com.au/bedalterabase.html We have also written a free "jumpstart guide" for using the Altera tools at http://www.burched.com.au/downloads.html I must also mention that if you are looking for a learning platform that already has things like an external micro, memory, peripheral connectors, 7 segment / LED displays etc. already on the board, then the BurchED kits are less appropriate that some other kits on the market. However, with the BurchED kits, you can always add the LEDs, switches, and peripheral connectors that you need. That's the idea - only add what you need for your application / prototype. Best regards Tony Burch www.BurchED.com.auArticle: 23953
Hi,
How do I have to connect the peripherial components to the FPGA in order to
correctly download the .bit file with the parrallel cabel III.
My error message is:
Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan
chain test failed at bit position '2' on instance
'<project_name>(Device1)'.
Check that the cable, system and device JTAG TAP connections are
correct,....
Where can I get information about configuring the clocks in the options
menue of the Foundation 2.i?
I'm using a XCS40.
thanks Andreas
Article: 23954Hi Ken, I'm posting from Deja at work as I haven't got 'proper' Usenet access from here! I have ticked the fast I/O option, and the pins are cleared at reset.... but the pins are bidirectional (I knew I'd missed something important out!) and the fitter is using the IOC for the input reg (presumably to meet the tsu time). Thanks for the suggestions though! Cheers, Martin In article <39739BC8.3D541A06@synplicity.com>, Ken McElvain <ken@synplicity.com> wrote: > Two possibilities: > 1) Make sure that you have requested "fast I/Os" in the global logic > synthesis options > 1) Preset flops can't be merged into the I/Os in Flex devices. Use > either no reset at all or a clear. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23955
Hi Ken, I'm posting from Deja at work as I haven't got 'proper' Usenet access from here! I have ticked the fast I/O option, and the pins are cleared at reset.... but the pins are bidirectional (I knew I'd missed something important out!) and the fitter is using the IOC for the input reg (presumably to meet the tsu time). Thanks for the suggestions though! Cheers, Martin In article <39739BC8.3D541A06@synplicity.com>, Ken McElvain <ken@synplicity.com> wrote: > Two possibilities: > 1) Make sure that you have requested "fast I/Os" in the global logic > synthesis options > 1) Preset flops can't be merged into the I/Os in Flex devices. Use > either no reset at all or a clear. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23956
PRELIMINARY SCHEDULE
CHES 2000
-------------------------------------------------------
Workshop on Cryptographic Hardware and Embedded Systems
Worcester Polytechnic Institute
Worcester, Massachusetts, August 17-18, 2000
http://ece.wpi.edu/Research/crypt/ches
for registration information, check CHES web site above
-------------------------------------------------------
=============== WEDNESDAY, AUGUST 16th ==============
5:00 - 10:00 pm REGISTRATION AND RECEPTION
Atwater Kent Building, WPI
(Shuttle Service will be provided between WPI and the Crowne Plaza Hotel)
=============== THURSDAY, AUGUST 17th ===============
7:00 - 8:45 am REGISTRATION AND CONTINENTAL BREAKFAST
Atwater Kent Building, WPI
(Shuttle Service will be provided between WPI and the Crowne Plaza Hotel)
8:45 - 9:15 am WELCOME
Welcome by Jack Carney (Provost, WPI)
Introductory remarks by Cetin Koc and Christof Paar
9:15 - 9:55 am INVITED TALK
Alfred Menezes, University of Waterloo, Canada
Elliptic curve cryptography in constrained environments.
9:55 - 10:55 am IMPLEMENTATION OF ELLIPTIC CURVE CRYPTOSYSTEMS
S. Okada, N. Torii, K. Ito, and M. Takenaka.
Implementation of elliptic curve cryptographic coprocessor over GF(2^m) on FPGA.
G. Orlando and C. Paar.
A high-performance reconfigurable elliptic curve processor for GF(2^m).
J. W. Chung, S. S. Gyoo, and L. P. Joong.
Fast implementation of elliptic curve defined over GF(p^m) on CalmRISC with
MAC2424 coprocessor.
10:55 - 11:15 am BREAK
11:15 - 12:35 pm POWER AND TIMING ANALYSIS ATTACKS
A. Shamir.
Protecting smart cards from passive power analysis with detached power supplies.
R. Mayer-Sommer.
Smartly analyzing the simplicity and the power of simple power analysis on
Smartcards.
M. A. Hasan.
Power analysis attacks and algorithmic approaches to their countermeasures for
Koblitz curve cryptosystems.
W. Schindler.
A timing attack against RSA with the Chinese Remainder Theorem.
12:35 - 2:00 pm LUNCH
2:00 - 3:20 pm HARDWARE IMPLEMENTATION OF BLOCK CIPHERS
A. Dandalis, V. K. Prasanna, and J. D. P. Rolim.
A comparative study of performance of AES final candidates using FPGAs.
C. Patterson.
A dynamic FPGA implementation of the Serpent Block Cipher.
S. Trimberger, R. Pang, and A. Singh.
A 12 Gbps DES Encryptor/Decryptor core in an FPGA.
H. Leitold, W. Mayerwieser, U. Payer, K. C. Posch, R. Posch, and J.
Wolkerstorfer.
A 155 Mbps triple-DES network encryptor.
3:20 - 3:40 pm BREAK
3:40 - 5:00 pm HARDWARE ARCHITECTURES
J. Goodman and A. Chandrakasan.
An energy efficient reconfigurable public-key cryptography processor
architecture.
J. Groszschaedl.
High speed RSA hardware based on dynamic true single phase clocked logic.
C. Walter.
Data integrity in hardware for modular arithmetic.
T. Kato, S. Ito, J. Anzai, and N. Matsuzaki.
A design for modular exponentiation coprocessor in mobile telecommunication
terminals.
6:00 - 9:00 pm BANQUET
=============== FRIDAY, AUGUST 18TH ==============
8:00 - 9:00 am REGISTRATION AND CONTINENTAL BREAKFAST
Atwater Kent Building, WPI
(Shuttle Service will be provided between WPI and the Crowne Plaza Hotel)
9:00 - 9:40 am INVITED TALK
David Naccache, Gemplus, France.
How to explain side channel leakage to your kids.
9:40 - 10:40 am POWER ANALYSIS ATTACKS
J.-S. Coron and L. Goubin.
On Boolean and arithmetic masking against differential power analysis.
T. S. Messerges.
Using second-order power analysis to attack DPA resistant software.
C. Clavier, J.-S. Coron, and N. Dabbous.
Differential power analysis in the presence of hardware countermeasures.
10:40 - 11:00 am BREAK
11:00 - 12:00 pm ARITHMETIC ARCHITECTURES
H. Wu.
Montgomery multiplier and squarer in GF(2^m).
E. Savas, A. F. Tenca, and C. K. Koc.
A scalable and unified multiplier architecture for finite fields GF(p) and
GF(2^m).
G. Hachez and J.-J. Quisquater.
Montgomery exponentiation with no final subtraction: Improved results.
12:00 - 1:30 pm LUNCH
1:30 - 2:10 pm PHYSICAL SECURITY AND CRYPTANLYSIS
S. H. Weingart.
Physical security devices for computer subsystems: A survey of attacks and
defenses.
T. Pornin and J. Stern.
Software-Hardware Trade-offs: application to A5/1 Cryptanalysis.
2:10 - 2:50 pm NEW SCHEMES AND ALGORITHMS
J. Hoffstein and J. Silverman.
MiniPASS: Authentication and digital signatures in a constrained environment.
M. Joye, P. Paillier, and S. Vaudenay.
Efficient generation of prime numbers.
Article: 23957
>>>> Don Husby wrote:
Don> This is way off topic.
Don> I'm thinking it's time to leave my cushy science job in Chicago and
Don> move to the West Coast. The scariest aspect of this is the nightmare
Don> stories I've heard about the difficulties of finding a place to live
Don> in Silicon Valley and the Bay area. Is it really that bad? Are there
Don> areas that are better/worse than others? Will I be spending hours
Don> per day in my car trying to get to work?
>>>>> "B" == B Joshua Rosen <bjrosen@polybus.com> writes:
B> You may want to consider the East coast instead. Massachusetts is
B> booming, there are wall to wall startups and the big companies like
B> Sun, Cisco, Lucent are all building huge facilities. The housing is
B> expensive compared to anywhere except Silicon Valley, by Valley
B> standards its cheap, you should be able to buy a decent house for
B> $350, there are million dollar houses but at least they are
B> 5000sq/feet and have a couple of acres of land, in Silicon Valley a
B> million dollars gets you a phone booth. The commutes are reasonable,
B> the Chinese food isn't as good as the Valley but the Italian food is
B> better.
I would second this. I was raised in the Chicago suburbs for the first 22
years of my life. I moved to 'Silicon Valley East' a little over 5 years
ago. Actually I wanted to make a small plug for living in southern New
Hampshire. There are _many_ startups both here and in the north of Boston
area that are _struggling_ to find EE's and software guys. I know we at
VAutomation certainly are!
Nashua,NH was twice picked as Money magazine's best city in the US. It's
funny to listen to local folks talk about how expensive property is getting
because it's all relative. Nice 3-4 bedroom homes in the Nashua area run
between $150K and $175K. What does that buy in the Bay area, a toilet?!
Cross the MA border, though, and it gets more difficult to find something
_that_ low. Even so, they're still less than the Bay area.
If anyone would like to crunch HDL code on FPGA's with us, give me a
call.... please! In 25 words or less: VHDL, ModelSim, Leonardo & Design
Compiler, Xilinx Virtex, processor and interface core development, a great
group of engineers, and now stock shares in ARC. Fun stuff!
--
Scott Bilik VAutomation Inc.
http://www.vautomation.com 402 Amherst St #100
(603) 882-2282 x24 Nashua NH 03063
Article: 23958Hi Martin... To meet timing in that situation, I explicitly place both input and output DFFs. Place the output DFF in the IOB and the input DFF in the nearest cell. The setup time is actually shorter in this case (due to the bonus input delay on the IOBs). I generally lock down all I/O flipflops, because our system is re-configurable, yet must always meet the same external timing. This way I can just worry about register-register timing. Eric martinthompson@my-deja.com wrote in message <8l11je$tsc$1@nnrp2.deja.com>... >Hi Ken, >I'm posting from Deja at work as I haven't >got 'proper' Usenet access from here! > >I have ticked the fast I/O option, and the pins >are cleared at reset.... but >the pins are bidirectional (I knew I'd missed >something important out!) and the fitter is using >the IOC for the input reg (presumably to meet the >tsu time). > >Thanks for the suggestions though! > >Cheers, >Martin >In article <39739BC8.3D541A06@synplicity.com>, > Ken McElvain <ken@synplicity.com> wrote: >> Two possibilities: >> 1) Make sure that you have requested "fast >I/Os" in the global logic >> synthesis options >> 1) Preset flops can't be merged into the >I/Os in Flex devices. Use >> either no reset at all or a clear. >> > > >Sent via Deja.com http://www.deja.com/ >Before you buy.Article: 23959
Bonjour, I can't read the "manufacturer/ID code" of a xilinx 17s05lvc prom. I power up the prom with Vcc=Vpp= 5.0v then I put ce and oe high and apply 12.25V at Vpp then 2 pulses on clk then 5.0V at Vpp then clk=1 to enter in programming mode. I put oe low and pulse 4600 clk then oe high then ce low and I read : 0011 0110 0111 1111 in place of 1100 1001 1000 0111 = C987 C9 for xilinx manufacturer ID, 8 for S05XL prom 7 for the algo code. What's wrong ? Merci de vos reponses. lino.de.martin@claranet.frArticle: 23960
Late breaking news... turn off the quartus fitter if you want to make DFF location assignments. <sigh> Eric Pearson Eric Pearson wrote in message ... >Hi Martin... > >To meet timing in that situation, I explicitly place both input and output >DFFs. >Place the output DFF in the IOB and the input DFF in the nearest cell. The >setup time >is actually shorter in this case (due to the bonus input delay on the IOBs). > >I generally lock down all I/O flipflops, because our system is >re-configurable, yet must always meet the same external timing. This way I >can just worry about register-register timing. > >Eric > > >martinthompson@my-deja.com wrote in message <8l11je$tsc$1@nnrp2.deja.com>... >>Hi Ken, >>I'm posting from Deja at work as I haven't >>got 'proper' Usenet access from here! >> >>I have ticked the fast I/O option, and the pins >>are cleared at reset.... but >>the pins are bidirectional (I knew I'd missed >>something important out!) and the fitter is using >>the IOC for the input reg (presumably to meet the >>tsu time). >> >>Thanks for the suggestions though! >> >>Cheers, >>Martin >>In article <39739BC8.3D541A06@synplicity.com>, >> Ken McElvain <ken@synplicity.com> wrote: >>> Two possibilities: >>> 1) Make sure that you have requested "fast >>I/Os" in the global logic >>> synthesis options >>> 1) Preset flops can't be merged into the >>I/Os in Flex devices. Use >>> either no reset at all or a clear. >>> >> >> >>Sent via Deja.com http://www.deja.com/ >>Before you buy. > >Article: 23961
Bonjour, I see a tiny programmer at http://www.mvd-fpga.com/ lino.de.martin@claranet.comArticle: 23962
Hmm, I was hoping to avoid turning off the Quartus fitter, as it takes about three times as long to fit. Ho hum! Thanks for the suggestion, I'll give it a try. Cheers, Martin In article <DAZc5.22241$227.416217@nnrp1.uunet.ca>, "Eric Pearson" <ecp@focus-systems.nospam.on.ca> wrote: > Late breaking news... > > turn off the quartus fitter if you want to make DFF location assignments. > > <sigh> > > Eric Pearson > > Eric Pearson wrote in message ... > >Hi Martin... > > > >To meet timing in that situation, I explicitly place both input and output > >DFFs. > >Place the output DFF in the IOB and the input DFF in the nearest cell. The > >setup time > >is actually shorter in this case (due to the bonus input delay on the > IOBs). > > > >I generally lock down all I/O flipflops, because our system is > >re-configurable, yet must always meet the same external timing. This way I > >can just worry about register-register timing. > > > >Eric > > > > > >martinthompson@my-deja.com wrote in message > <8l11je$tsc$1@nnrp2.deja.com>... > >>Hi Ken, > >>I'm posting from Deja at work as I haven't > >>got 'proper' Usenet access from here! > >> > >>I have ticked the fast I/O option, and the pins > >>are cleared at reset.... but > >>the pins are bidirectional (I knew I'd missed > >>something important out!) and the fitter is using > >>the IOC for the input reg (presumably to meet the > >>tsu time). > >> > >>Thanks for the suggestions though! > >> > >>Cheers, > >>Martin > >>In article <39739BC8.3D541A06@synplicity.com>, > >> Ken McElvain <ken@synplicity.com> wrote: > >>> Two possibilities: > >>> 1) Make sure that you have requested "fast > >>I/Os" in the global logic > >>> synthesis options > >>> 1) Preset flops can't be merged into the > >>I/Os in Flex devices. Use > >>> either no reset at all or a clear. > >>> > >> > >> > >>Sent via Deja.com http://www.deja.com/ > >>Before you buy. > > > > > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23963
--------------D737631738975EBB9988E6E0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Alan wrote: > In article <3969D673.573FE3B5@voila.fr>, christelle <van-den- > broucke@voila.fr> writes > >Hi all, > > > >Is there anyone using Quartus? > >I've heard that there are lots of problems with this tool... > > > > In my experience, don't bother with a UNIX ported version (Ultra 60 - > 700Mbytes RAM) - it's the only program that I've known to core dump on a > regular basis :( > > Quartus appears to run well on a 900MHz PC with 1 Gbyte of RAM. Anything > less and again I have found it to be painfully slow and, more serious, > prone to various unexplained error messages/crashes. > > I'm currently attempting to fit a 400k gate equivalent design with 380 > I/O pins into the APEX 20KE600 device. It appears have gone in and met > timing but it will be a two/three weeks before I can establish if the > post fitting simulations work as expected. Hi, You're probably referring to the fact that post-layout (timing) simulation takes for ages, because of the backannotated (SDF) delays, and all associated timing-checks.... ;-) Trying using (static) timing analysis instead (Quartus Timing Analyzer), to verify the TIMING requirements of your design. No testbench and/or vectors needed for this, and 100% coverage of all timing paths (not just what you believe to be critical....) If you don't trust the functionality anymore after fitting/optimization by Quartus, export a VHDL/Verilog netlist, and simulate without backannotating timing. Best regards, Jaap > > -- > Alan > mailto:news4me@amacleod.clara.co.uk --------------D737631738975EBB9988E6E0 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>Alan wrote: <blockquote TYPE=CITE>In article <3969D673.573FE3B5@voila.fr>, christelle <van-den- <br>broucke@voila.fr> writes <br>>Hi all, <br>> <br>>Is there anyone using Quartus? <br>>I've heard that there are lots of problems with this tool... <br>> <p>In my experience, don't bother with a UNIX ported version (Ultra 60 - <br>700Mbytes RAM) - it's the only program that I've known to core dump on a <br>regular basis :( <p>Quartus appears to run well on a 900MHz PC with 1 Gbyte of RAM. Anything <br>less and again I have found it to be painfully slow and, more serious, <br>prone to various unexplained error messages/crashes. <p>I'm currently attempting to fit a 400k gate equivalent design with 380 <br>I/O pins into the APEX 20KE600 device. It appears have gone in and met <br>timing but it will be a two/three weeks before I can establish if the <br>post fitting simulations work as expected.</blockquote> Hi, <p>You're probably referring to the fact that post-layout (timing) <u>simulation</u> takes for ages, because <br>of the backannotated (SDF) delays, and all associated timing-checks.... ;-) <br>Trying using (static) timing <u>analysis</u> instead (Quartus Timing Analyzer), to verify the TIMING requirements of your design. No testbench and/or vectors needed for this, and 100% coverage of all timing paths (not just what <br>you believe to be critical....) <br>If you don't trust the <u>functionality</u> anymore after fitting/optimization by Quartus, export a <br>VHDL/Verilog netlist, and <u>simulate without</u> backannotating timing. <p>Best regards, <p>Jaap <br> <br> <blockquote TYPE=CITE> <br>-- <br>Alan <br><a href="mailto:news4me@amacleod.clara.co.uk">mailto:news4me@amacleod.clara.co.uk</a></blockquote> </html> --------------D737631738975EBB9988E6E0--Article: 23964
I just wanted to give ya'll a heads up that the massive 104 page DAC'00 Trip
Report is up on http://www.DeepChip.com for viewing. It's a collective
report based on 113 survey responses and/or individual DAC trip reports (it
consists of quotes from those 113 engineers.) Enjoy.
- John Cooley
-----------------------------------------------------------------------------
__)) "Glass ceilings? Name ANY ex-goat farmer who's made management!"
/_ oo
(_ \ Holliston Poor Farm - John Cooley
%// \" Holliston, MA 01746-6222 part time Sheep & ex-Goat Farmer
%%% $ jcooley@world.std.com full time contract ASIC & FPGA Designer
Article: 23965In article <bq6ums8i08fove3ebmjsuh8e2engqvgqlb@4ax.com>, Muzaffer Kal <muzaffer@kal.st> wrote: >you can always use two blocks of memory and while one side writes to >one of the blocks, the other side reads the other block. When both >sides are done, you switch the blocks. Usually call a ping-pong memory. >Of course this assumes consumer >is faster than producer. As long as you have enough bandwidth, true >multi-port access is almost never needed. (In fact I can't think of >any case where true multi-port access would be needed, any ideas ?) Sure. Register files in CPUs where you need to fetch multiple operands every cycle. Even more so with architectures that can have multiple function units complete in the same cycle, and there are multiple results that need to be written back to the register file. Buffer memories, where the incomming and/or outgoing data is bursty, and the average data rate of incoming is less than or equal to the outgoing data rate. This situation can preclude a ping-pong topology, unless the buffers are very large. Depends on the statistics. FIFOs are another structure that fairly much mandate a dual-port memory internally. Especially a FIFO that has separate input and output clocks. Philip FreidinArticle: 23966
Does anyone know whether or not there are any PLD-related conferences
scheduled to take place in the US before mid-September? If so, which ones?
Thanks,
EKC
Article: 23967Andreas Wüstefeld wrote in message <8l1045$8ob$16$1@news.t-online.com>... >Hi, > >How do I have to connect the peripherial components to the FPGA in order to >correctly download the .bit file with the parrallel cabel III. >My error message is: > > Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan ... Hi Andreas, I believe that your problem is that you are using the JTAG Programmer, instead of the Hardware Debugger. For an expanded answer see http://www.burched.com.au/jtag.html Best regards Tony Burch www.BurchED.com.auArticle: 23968
Just read your DAC report, John, and it was great. The amount of detail and the "unabridged" nature of the opinions expressed made it the best DAC report I've ever read. Now I'm concerned that you might get sucked into a chief editor's job at one of the industry mags. Keep up the good work. John Cooley <jcooley@world.std.com> wrote in message news:Fxwuw5.AEB@world.std.com... > I just wanted to give ya'll a heads up that the massive 104 page DAC'00 Trip > Report is up on http://www.DeepChip.com for viewing. It's a collective > report based on 113 survey responses and/or individual DAC trip reports (it > consists of quotes from those 113 engineers.) Enjoy. > > - John Cooley > > ---------------------------------------------------------------------------- - > __)) "Glass ceilings? Name ANY ex-goat farmer who's made management!" > /_ oo > (_ \ Holliston Poor Farm - John Cooley > %// \" Holliston, MA 01746-6222 part time Sheep & ex-Goat Farmer > %%% $ jcooley@world.std.com full time contract ASIC & FPGA DesignerArticle: 23969
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Have a look at the optimagic webside.
CPLD, FPGA: The Programmable Logic Jump Station
EKC wrote:
> Does anyone know whether or not there are any PLD-related conferences
> scheduled to take place in the US before mid-September? If so, which ones?
>
> Thanks,
>
> EKC
--
---------------------------------------------------------------------------
Harald Simmler Lehrstuhl fuer Informatik V
Universitaet Mannheim
Tel: +49-621-181-2632 ! NEW ! B6, 26
Fax: +49-621-181-2634 ! NEW ! D-68131 Mannheim
eMail: simmler@ti.uni-mannheim.de Germany
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Content-Type: text/html; charset=us-ascii
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Have a look at the optimagic webside.
<br> <a href="http://www.optimagic.com/">CPLD, FPGA: The Programmable
Logic Jump Station</a>
<br>
<p>EKC wrote:
<blockquote TYPE=CITE> Does anyone know whether or not
there are any PLD-related conferences
<br>scheduled to take place in the US before mid-September? If so, which
ones?
<p>Thanks,
<p>EKC</blockquote>
<p>--
<p>---------------------------------------------------------------------------
<br>Harald Simmler
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Article: 23970--------------CFEFC5E74F2E7D73965A5A0A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Have a look at the optimagic webside. CPLD, FPGA: The Programmable Logic Jump Station EKC wrote: > Does anyone know whether or not there are any PLD-related conferences > scheduled to take place in the US before mid-September? If so, which ones? > --------------CFEFC5E74F2E7D73965A5A0A Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Have a look at the optimagic webside. <br> <a href="http://www.optimagic.com/">CPLD, FPGA: The Programmable Logic Jump Station</a> <br> <p>EKC wrote: <blockquote TYPE=CITE> Does anyone know whether or not there are any PLD-related conferences <br>scheduled to take place in the US before mid-September? If so, which ones? <br> </blockquote> </html> --------------CFEFC5E74F2E7D73965A5A0A--Article: 23971
Hi All,
does any one know of a core which has the 8250 with a 16 byte fifo
(Or equivalent) and only uses approx 100 CLB's. I need to place 3 of these
in a XCS30XL with some room to spare.
thanks in advance.
--
David Dart,
email davidd@nulec.com.au
Article: 23972Philip Freidin wrote: > > In article <bq6ums8i08fove3ebmjsuh8e2engqvgqlb@4ax.com>, > Muzaffer Kal <muzaffer@kal.st> wrote: > >you can always use two blocks of memory and while one side writes to > >one of the blocks, the other side reads the other block. When both > >sides are done, you switch the blocks. > > Usually call a ping-pong memory. > > >Of course this assumes consumer > >is faster than producer. As long as you have enough bandwidth, true > >multi-port access is almost never needed. (In fact I can't think of > >any case where true multi-port access would be needed, any ideas ?) > > Sure. > > Register files in CPUs where you need to fetch multiple operands > every cycle. Even more so with architectures that can have multiple > function units complete in the same cycle, and there are multiple results > that need to be written back to the register file. > > Buffer memories, where the incomming and/or outgoing data is bursty, and > the average data rate of incoming is less than or equal to the outgoing > data rate. This situation can preclude a ping-pong topology, unless > the buffers are very large. Depends on the statistics. Actually, you can use a ping-pong buffer arrangement as long as you add a "pang" buffer (a third block). This allows you to collect as much as twice the normal data rate while empting the first buffer collected. If you can't meet that requirement, then you will have a problem sizing your buffers for any arrangement. > FIFOs are another structure that fairly much mandate a dual-port > memory internally. Especially a FIFO that has separate input > and output clocks. > > Philip Freidin -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23973
If you think Usenet Newsgroups are helpful, wait until you try Experts-Exchange. It's a great place to ask technical computer questions (software or hardware). It's also a great place to give advice if you know the answers. It's free! If you would, mention that GivenRandy referred you -- I won't get any money, just some extra question points so that I can ask more questions myself. Hope to see you there! http://www.experts-exchange.com/Article: 23974
We've had great success with Xilinx DP RAMs here. The tools are rather good too. Altera still have some catching up to do.
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