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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Or read S.W. Golomb's 1947 (?) book on shift-register generated sequences.
If you can find a copy. If for no other reason than (and here I work from
memory), the limerick in the frontis:
A message of content and clarity
Has gotten to be quite a rarity
To avoid the terror
Of serious error
Use bits of appropriate parity
Not high art, but it's stuck with me for 20 years...
In article <m3bsq0w44y.fsf@cadence.glidepath.org>, Marc D Bumble
<bumble@isd.net> wrote:
>
>For a simple pseudo random number generator implementation for an
>FPGA, see the following references:
>
>@Article{hoogland83,
> author = {A. Hoogland and J. Spaa and B. Selman and A. Compagner},
> title = {A special-purpose processor for the monte carlo simulation
> for ising spin systems},
> journal = {Journal of Computational Physics},
> year = 1983,
> volume = 51,
> pages = {250-260}
>}
>
>@Article{pearson83,
> author = {Robert B Pearson and John L. Richardson and Doug Toussant},
> title = {A Fast Processor for Monte-Carlo Simulation},
> journal = {Journal of Computational Physics},
> year = 1983,
> volume = 51,
> pages = {241-249}
>}
>
>
>>> "Jörg" == Jörg Ritter <ritter@informatik.uni-halle.de> writes:
>
> > Hi Ray, I've a more general question concerning the app notes. In
> > those app notes tricky circuits are presented , which fits into a
> > few CLB's. Mostly a schematic describes the circuit.
>
> > If the circuit isn't available in Coregen/Logiblox what is your
> > favorite way to create a module (as netlist)? Do you implement
> > the design structurally in VHDL, synthesize and floorplan the
> > result manually? Or do you prefer a schematic entry tool, where
> > you can instantiate basic XC4000 elements, e.g. like RAM16x1S?
>
> > Thanks Joerg
>
> >> There are no random sources inherent in the FPGA, although you
> >> could conceivably use the phase difference between the internal
> >> oscillator in the 4Kparts and an external clock. I'd prefer to
> >> use the linear feedback shift register (LFSR) with a long enough
> >> sequence to make it random over a long interval. That can be
> >> done very compactly in the 4K using CLB ram (see the xilinx app
> >> note on LFSRs, I think it is XAPP152).
>
>
Article: 30551Aloha! In short: Has anybody successfully obtained a license key for the version of ModelSim in Xilinx webpack by sending an email to the suggested "cs_1@xilinx.com" email address? Alternatively, does anybody know a proper email address to contact Xilinx about a problem like this? I've searched through their website, but all (what seemes to be suitable) options under "Contact" are based on registration, web forms and so on. Not a single email adress in sight... .-) It's (at least for me) a non-trivial excercise to guess which of them is the proper one. The problem I'm having is this: I downloaded the complete webpack thingy. I moved all these files from my UNIX-system to the Widows system. In Windows I installed the Webpack there. No problems. All of Xilinx own SW worked nicely. But in order to get the ModelSim XE included in the Webpack I needed to get a license. Now, the Windows system does not have a net connection configured. No worries, ModelSim XE generated a textfile instead. I went back to UNIX and email the file to the suggested email address "cs_1@xilinx.com". 3 weeks later and I've yet to see any respone to the email. -- Cheers! Joachim - Alltid i harmonisk svängning --- FairLight ------ FairLight ------ FairLight ------ FairLight --- Joachim Strömbergson ASIC SoC designer, nice to CUTE animals Phone: +46(0)31 - 27 98 47 Web: http://www.ludd.luth.se/~watchman --------------- Spamfodder: regeringen@regeringen.se ---------------Article: 30552
Also, look at http://www.fpgacpu.org (There are a whole bunch in the links section.) http://www.xilinx.com/xapp/xapp213.pdf (Xilinx has a free one.) Hope this helps. -Kent "Keith Jasinski, Jr." <cartracin@nospam.yahoo.com> writes: > http://www.opencores.org > > Good starters to play with > > -- > Keith Jasinski, Jr. > > *The opinions expressed herein are those of the author and not his > employer... > "Jae-cheol Lee" <jchlee@lgic.co.kr> wrote in message > news:KQsB6.2112$2b5.22213@news2.bora.net... > > I've ever heard that there exist free processor cores for FPGAs. > > > > Where can I find one for Xilinx vertex series ? > > > > I think XCV2000E could emulate 4MHz Z80 or 6502 including other > peripherals. > > > > > >Article: 30553
There is no pay (yet) but once we get going income will be generated through advertisements on the site and various other services which we will offer, and there will surely be enough to go around. Brief Overview: TizEK.com is destined to be THE premiere Internet portal for techies and geeks alike. We currently need graphic developers, HTML authors, PHP, CGI/PERL authors, and creative minds. To apply, mail us at developers@tizek.com Thank you, TizEK.comArticle: 30554
Ok this has been a great thread. We just did a demo of Handel-C. It was impressive. But.... we are also in the process of putting together a million gate FPGA design running at 133Mhz. It's VERY difficult to meet timing. Add a layer of abstraction? I don't think so. Will Handel-C replace VHDL? Not in critical designs. Can you imagine the levels of logic a SW eng would end up with? Will it allow more people to design hardware? Yes. In article <9aoga1$qt8$1@taliesin.netcom.net.uk>, compilehr@yahoo.com says... > >Does anyone what the future will be like for Verilog and VHDL ? > >Wil it be replaced by C/C++ platform ? > >It looks like Handel C is taking oof. > >What I am wondering is will DK-1 suite be able to convert the test benches >into a supported >language as well ? For ASIC conversion, that is.. > >http://www.infoconomy.com/pages/search/group18585.adp > >http://isdmag.com/story/OEG20010301S0056 > >http://www.celoxica.com/news/in_the_news.htm > >Article: 30555
Joachim, I have installed the webpack under win95/98 and had no problems with obtaining a modelsim license. After installing modelsim a email was generated to Xilinx and witin 5 minutes i got a email back with the license file attached.. Don't know how this works under Unix???. good luck Ron proveniers Joachim Strömbergson <watchman@ludd.luth.se> schreef in berichtnieuws 3AD9623C.2FE05EEB@ludd.luth.se... > Aloha! > > In short: Has anybody successfully obtained a license key for the > version of ModelSim in Xilinx webpack by sending an email to the > suggested "cs_1@xilinx.com" email address? > > Alternatively, does anybody know a proper email address to contact > Xilinx about a problem like this? I've searched through their website, > but all (what seemes to be suitable) options under "Contact" are based > on registration, web forms and so on. Not a single email adress in > sight... .-) It's (at least for me) a non-trivial excercise to guess > which of them is the proper one. > > The problem I'm having is this: I downloaded the complete webpack > thingy. I moved all these files from my UNIX-system to the Widows > system. In Windows I installed the Webpack there. No problems. > > All of Xilinx own SW worked nicely. But in order to get the ModelSim XE > included in the Webpack I needed to get a license. Now, the Windows > system does not have a net connection configured. No worries, ModelSim > XE generated a textfile instead. I went back to UNIX and email the file > to the suggested email address "cs_1@xilinx.com". 3 weeks later and I've > yet to see any respone to the email. > > -- > Cheers! > Joachim - Alltid i harmonisk svängning > --- FairLight ------ FairLight ------ FairLight ------ FairLight --- > Joachim Strömbergson ASIC SoC designer, nice to CUTE animals > Phone: +46(0)31 - 27 98 47 Web: http://www.ludd.luth.se/~watchman > --------------- Spamfodder: regeringen@regeringen.se ---------------Article: 30556
hi,lan you should go early today, you have to go to college by bus, haven't you? and back by youself! -- Cheny Wu Hardware Design Engineer Interactive Circuits & Systems Ltd. 5430 Canotek Road Gloucester, Ontario, K1J 9G2 Canada Tel: +1-613-749-9241 x 226 Fax: +1-613-749-9461 Web: www.ics-ltd.com E-mail: cheny@ics-ltd.comArticle: 30557
Hello, I would like to design a PCMCIA card. I have been to www.pcmcia.org The spec is very expensive. Is there any online information that would help me design a PCMCIA card? Sincerely DanArticle: 30558
You can do a web search on chips that implement the PC-CARD interface and use their datasheets as a first reference. I once had one of a PC-CARD NIC IC, but I can not find it right now. If I recall correctly it was essentially the ISA protocol but with geographical addressing and an additional device identification standard. CARDBUS is essentially PCI. Kolja Dan wrote: > Hello, > > I would like to design a PCMCIA card. > > I have been to www.pcmcia.org The spec is very expensive. > > Is there any online information that would help me design a PCMCIA card? > > Sincerely > DanArticle: 30559
In article <8n32kt$4ns$1@sunlight.pku.edu.cn>, threehero <threehero@sina.com> writes: >I use VHDL and Synplify to describe and synthesize my design, respectively. >when i designed a state machine, I used the attribute of syn_encoding to >specify the type of state encoding, such as "gray".The number of states in >my >state machine is 20.But when I looked in the log file after synthesis, I >found >my state encoding had been converted to "one-hot" by Synplify automatically. >Why did it do such? I did not need "one-hot". How could i tell it what I >want >the state encoding to be? > >Any suggestions and replies would be very appreciated! > >jianjie > > ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web ----- http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups NewsOne.Net prohibits users from posting spam. If this or other posts made through NewsOne.Net violate posting guidelines, email abuse@newsone.netArticle: 30560
Hi
search for the attribute syn_encoding in your Synplify Help
the following is a copy from my vhdl-file (ok, I use onehot ;-),
their are other codings possible (sequential, gray).
attribute syn_state_machine of currentstate: signal is true;
attribute syn_encoding of currentstate: signal is "safe,onehot";
Look at
"Specifying FSMs with Attributes and Directives"
in your Synplify-Help.
bye norbert
michael.muellerm@med.ge.com wrote:
>
> In article <8n32kt$4ns$1@sunlight.pku.edu.cn>, threehero <threehero@sina.com>
> writes:
> >I use VHDL and Synplify to describe and synthesize my design, respectively.
> >when i designed a state machine, I used the attribute of syn_encoding to
> >specify the type of state encoding, such as "gray".The number of states in
> >my
> >state machine is 20.But when I looked in the log file after synthesis, I
> >found
> >my state encoding had been converted to "one-hot" by Synplify automatically.
> >Why did it do such? I did not need "one-hot". How could i tell it what I
> >want
> >the state encoding to be?
> >
> >Any suggestions and replies would be very appreciated!
> >
> >jianjie
> >
> >
>
> ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web -----
> http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups
> NewsOne.Net prohibits users from posting spam. If this or other posts
> made through NewsOne.Net violate posting guidelines, email abuse@newsone.net
--
---------------------------------------------------------------
Ursula K. LeGuin (Das Wort fuer Welt ist Wald):
Im Grunde war ein Mann nur dann wirklich und vollstaendig ein
Mann, wenn er gerade eine Frau besessen oder einen anderen
Mann getoetet hatte.
---------------------------------------------------------------
Norbert Bierlox / Universitaet Karlsruhe (TH)
Dipl.-math. / Institut fuer Angewandte Mathematik
fon: +49 721 608 8331 / D-76128 Karlsruhe
fax: +49 721 608 8319 / Norbert.Bierlox@ieee.org
---------------------------------------------------------------
Article: 30561Jae-cheol Lee escribió: > > I've ever heard that there exist free processor cores for FPGAs. > > Where can I find one for Xilinx vertex series ? > > I think XCV2000E could emulate 4MHz Z80 or 6502 including other peripherals. Hi Jae-cheol, you may look at: http://www.dte.eis.uva.es/OpenProjects/OpenUP/index.htm for an 8-bit general purpose processor in VHDL (English or Spanish), and http://www.dte.eis.uva.es/OpenProjects/OpenDSP/index.htm for a 16-bit fixed-point DSP processor in Verilog (nowadays in Spaninsh). Enyoy, Santiago (sanpab@eis.uva.es).Article: 30562
Hi I need to finish SPI interface of a DAC -- Max 144. Max 144 are two clock triggerring way: external clock and internal clock In external clock mode I need to generate a 0 for sometime then generate 16 clock pulse with difference frequency with my system clock rate. In internal clock mode, I need to generate a 1 for sometime then receive 16 clock pulse from Max 144. How can I implement those two modes by VHDL? Thanks QianArticle: 30563
I'm interested in encoding and decoding of variable bit-length codewords (as typically used in (de)compression applications) using PLDs. Does anyone have any pointers to information on this subject? Thanks, -- Frode Vatvedt FjeldArticle: 30564
"Ray Andraka" <ray@andraka.com> wrote in message news:3ACF65DF.2A3E482@andraka.com... > XCV1000 (without the E suffix) has 32 block Rams, each is a 4Kbit dual port RAM, > which you can set up as 1,2,4,8 or 16 bits wide by the corresponding depth to > make 4K bits. There is a Xilinx app note which claims selectRAM in the Virtex line can be used to create "larger RAM structures." Does any one have experience setting these up? How about a 40-bit wide, 500 deep RAM? There is clearly enough total space, but how do you set it up? Thanks! Martin > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.comArticle: 30565
The following URL shows some performance data for Huffman encoding.
It is designed to be fast, so it uses a large logarithmic shifter.
Bit serial implementations can be very small.
http://bounty.em.informatik.uni-frankfurt.de/~prak/ss00/projekte/huffman/Huffman.html
CU,
Kolja Sulimma
Frode Vatvedt Fjeld wrote:
> I'm interested in encoding and decoding of variable bit-length
> codewords (as typically used in (de)compression applications) using
> PLDs. Does anyone have any pointers to information on this subject?
>
> Thanks,
> --
> Frode Vatvedt Fjeld
Article: 30566Martin wrote: > > How about a 40-bit wide, 500 deep RAM? There is clearly enough total space, > but > how do you set it up? You just break up the data word into five parallel 8-bit words, and store each in a 512 x 8 BlockRAM with common addressing for all 5 BlockRAMs. Peter Alfke, Xilinx ApplicationsArticle: 30567
On Tue, 17 Apr 2001 10:56:36 -0400, "Martin" <mww3@alumni.cwru.edu> wrote: >There is a Xilinx app note which claims selectRAM in the Virtex line can be >used to >create "larger RAM structures." Does any one have experience setting these >up? > >How about a 40-bit wide, 500 deep RAM? There is clearly enough total space, >but >how do you set it up? My guess is that you'd want to use BlockRAM for this. Anyway, I simply code an array (the depth I need) of std_logic_vector (the width needed) and let synthesis (Synplify) figure out the dirty details. I haven't done anything quite this big yet, but on a SpartanXL I have a 32x32 dual-port array done this way. I'll have some fairly large FIFOs on a Virtex, but we'll use CoreGen for those. Xilinx has a bunch of app notes on their arrays as well. Depending on your toolset you'll likely want to visit their site for help too. ---- KeithArticle: 30568
We just completed a prototype design using an XC95144XL-7TQ144C. This device provides glue logic for three processors, all of which are asynchronous to each other. Included in the design was an 8-bit latch for the address LSB of one of the processors. We found that this latch was being corrupted at the point in time when a group of address lines from one of the other processors transitioned. As a work around, when we changed the LD8 to an FD8 the problem went away. All signals entering the CPLD are glitch free. The CPLD is sitting on a liberally decoupled set of power and ground planes. We have done many high-speed logic designs with Xilinx FPGAs and CPLDs, and we have never experienced a problem like this before. Has anyone else experienced apparent internal noise sensitivity problems like this with XC9500XL CPLDs? =================================== Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 30569
Hi guys, This is not an FPGA item but Ball Grid Arrays are the FPGA in thing and I am sure at least one of you can assist with this question. In the old days of LCC's and extended temperature cycling environments (MIL), large LCC's mounted on normal FR4 PCB's used to suffer from solder cracking due to the difference in thermal expansion difference between the chip and PCB materials - hence polyimide PCB's etc. Today we now have high density CPBA and PBGA packages and I was wondering if these suffer from the same effects when cycled from say -45 to +85C. Are there any special precautions required in the PCB design? Are there any special requirements for using a more "compliant" solder? Does anyone work for a company that has a production facility familiar with these requirements? Perhaps these techniques are well documented somewhere? Thanks Anthony.Article: 30570
XILINX:
Please read this and update the download software:
-----------
Here is the schematic of the xilinx parallel download cable.
http://toolbox.xilinx.com/docsan/3_1i/data/common/hug/chap01/hug01007.htm
It has never been very reliable.
It has been reported that some combinations of cables, mainboards and
parallel board settings did not work.
Also dongles and long cables have been a problem.
For example Answer 7313:
"Parallel cable
You cannot use an extension. You cannot extend the
cable
because the parallel port drivers are not strong
enough. The signals will
attenuate, the data will become corrupted. Note: Make
sure that your
parallel cable is not running through a dongle. There
have been cases
where removing the dongle resolved programming issues."
Well, we had a closer look at it.
The PROGRAM signal is pulled LOW by the download software to initiate a
reconfiguration.
The software then holds the signal HIGH during configuration and than
releases the signal to high impedance.
The PROGRAM signal should remain high at the end of a configuration,
usually hold by a pullup resistor.
Here is what we saw when we had a look at the PROGRAM signal (top) and
its output enable (bottom)
at the end of a configuration. Signals are measured at the parallel
port.
http://bounty.em.informatik.uni-frankfurt.de/~prak/platine/downloadwaves.gif
The download software releases the signal, but simultaneously sets its
value to LOW.
This results in a classical race condition: The output must be reliably
disabled before it starts driving the PROGRAM signal low again.Depending
on the relative strength of the pullup and pulldown transistors in the
parallel port implementation, cable reflection, the buffers used in the
dowload cables, its loads, etc. this might work correctly.
Or it may not.
If the pullup is much weaker than the pulldown (as in the example shown)
there is a problem.
Ever wondered what the 100pF capacitors in the schematic are there for?
They slow the signal down, so that it does not change its value until
the buffer is disabled.
This is a very dirty solution.
Instead the software should first disable the buffer and later change
the value.
Or even better: Do not change the value at all. Just disable the buffer.
Kolja Sulimma
Article: 30571
Hi Ray !
I tried to implement the multiplier using plain partial product addition,
as you proposed.
The problem is that my implementation is pretty far from your predictions.
Instead of 20 X 4.5
CLBs, it has quite irregular structure taking 242 slices in Virtex-E. I've
noticed that the
main problem is that my code uses few columns to generate partial product.
PAR just doesn't
understand that it could squeze all that in one column. Have tried to trace
all signals in
FPGA Editor, but I still don't quite understand why is it implemented such a
way. Here's the
code i'm using for generating partial products :
PP1_PROC:process(a, b8)
variable b0 : std_logic_vector(WORD downto 0);
variable b1 : std_logic_vector(WORD downto 0);
variable prod0 : std_logic_vector(WORD downto 0);
variable prod1 : std_logic_vector(WORD downto 0);
begin
b0 := (others => b8(0));
b1 := (others => b8(1));
prod0 := ('0' & a) and b0;
prod1 := (a & '0') and b1;
if b8(0) = '1' then
pp_p1 <= ('0' & prod0) + ('0' & prod1);
else
pp_p1 <= '0' & prod1;
end if;
end process PP1_PROC;
Partial products are further added using three adders. I've also tried :
...
if b8(0) = '1' then
pp_p1 <= ('0' & (('0' & a) and b0)) + ('0' & ((a & '0') and b1));
else
pp_p1 <= '0' & ((a & '0') and b1);
end if;
...
which gave me almost the same thing. I'm using FPGA Express. Have tried
experimenting with turning operator sharing ON/OFF, but not much difference.
In simulation everything works perfectly.
Could anyone give me a hint what am i doing wrong ?
Kind regards,
Domagoj Babic
domagoj(et)rasip.fer.hr
Ray Andraka <ray@andraka.com> wrote in message
news:3ACA94DD.FE1F3D2B@andraka.com...
> For the multiplication, you might refer to my multiplication in FPGAs page
on my
> website. Since you have 4 clocks to do the multiplication in, I'd use an
8x32
> multiplier which performs 8x32 partial products and then sum those four
partials
> in a scaling accumulator. The 8x32 multiplier is made up of an adder tree
(3
> adders) that add 4 2x32 partial products together. The 2x32 partial
products
> are one slice per pari of bits (see the 2xn bit virtex construction under
> computed partial products on the web page). The multiplier will occupy a
4.5w
> by about 20h CLB area, height depending on how many output bits you keep.
>
> There is also some text on there as to why you don't want to use a wallace
tree
> in an FPGA.
>
> For the divider, you state that latency is not an issue. You could use a
> restoring or non-restoring division algorithm, which I think can be done
in a
> single column of 33 clbs. as you alluded, you can also use the multiplier
to
> reduce the number of cycles.
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
Article: 30572Hi Helen, "Helen Long" <madisonfff@usa.net> schrieb im Newsbeitrag news:9bhgie$ccc$1@news.doit.wisc.edu... > How can I implement those two modes by VHDL? > I'd define the Pin as INOUT and use an FSM to switch through the states. If You have to clock the Pin by the FPGA, just assign '0' and '1' in the states, generating the clock signal. On the other hand, if you have to drive '1' for some Systemclock cycles and accept the clock of the MAX itself, drive the '1' by assigning it and then assign an 'Z' to write an TriState and assign the Pin to an internal signal simultaneously to read the level at the Pin. (e.g. MAX_CLK<='Z' and EXT_CLK<=MAX_CLK) assuming the external Pin is MAX_CLK and EXT_CLK is the internal signal. HTH, CarlhermannArticle: 30573
Hello. I am interested in some tried and true methods to do divide a square wave of a given frequency by an integer n -- the duty cycle in this case does not have to be 50% but 50% solutions are interesting too. In multiple designs I did, using Altera parts, I took an LPM_COUNTER, configured it to count down, decoded when output was == 0, and had that synchronously load the counter. The data (into the counter) was (desired divisor rate -1), and my decoded output was also my output. My approach to the design ends up using a counter + subtractor to count down, and a decoder/multiple AND gates to "detect" when the count value has been reached. However the Altera simulator results show there is a decent amount of skew between the clock rising edge and my output rising edge(6 ns for a fast CPLD). I was looking for something that might work for both CPLDs and FPGAs, but obviously one could make clever use of look-up tables and such. The solution doesn't have to be specific to either Xilinx or Altera, but I was looking for a "digital" solution, so no PLLs or DPLLs. Thanks, VR.Article: 30574
VR schrieb: > > Hello. > > The solution doesn't have to be specific to either Xilinx or Altera, but I > was looking for a "digital" solution, so no PLLs or DPLLs. Use a clock of twice the desired maximum frequency and use two parallel counters (ok, the first one is just a toggle FF ;-) Now your skew is down to pin2pin delay variations (somewhere 200ps or less I think) -- MFG Falk
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