Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
The fully parallel xilinx 16x16 multiplier core can fit in a 16hx8w CLB area, and will run at 100MHz (10ns) in a virtex-4 without modification (slowest speed grade). This is a fully pipelined multiplier, 4 clocks deep. With some layout modifications, it can be made a little faster. If you don't need all 32 bits out, you can also rearrange it so that it is not as tall. YOu can get 3 into a V50 w/o mods. W/ fairly minor layout mods you can get 6 into a V150, and maybe a V100. These are generated by the xilinx core generator. If you double the time allowed, per multiply, you can either use one multiplier to do two of the multiplications or cut the size of the multiplier using a scaling accumulator (see my webpage on multipliers). That scales with the number clocks available per required product. If this is for a sum of products, youmight also look at distributed arithmetic. Alex Sherstuk wrote: > > Dear colleagues, > > What is your experience: what size of VIRTEX (SPARTAN-2) chip is needed > to implement something like 8 multipliers 16*16 bits, 10 ns per multiply? > 100 ns per multiply? > > Are there any multipliers in standard XILINX library for Virtex? If not, > where they are? > > Thanks, > Alex Sherstuk > sherstuk@iname.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28926
Where I can download, the free, beta Leap-Forge compiler? Forge - LEAP_CD-1.19.2.5.tar Thak you: Tibor Szolnoki Sent via Deja.com http://www.deja.com/Article: 28927
Ray, I haven't got any experience doing Floorplanning but I think it is important for high-speed design. I have looked at your datasheet (smpte_data.pdf). You used Xilinx M1.5. Last year, a customer of mine was using M1.5 to route a design I described earlier - 75% CLB on a xc40150xv, with 2 clocks (50MHz and 12.5MHz). They discovered that the compiler will report no timing errors, but the hardware verification fails. When they upgrade to version 3.1, the same design cannot be routed completely. It seems that xilinx 3.1 is "stricter", but it is consistent with the hardware. Have you encountered the same problem before? Regards, LC Ray Andraka <ray@andraka.com> wrote in message news:3A758E17.D8D215F2@andraka.com... > FLoorplanning and designing to the architecture will let yo do much better. > I've > done a large number of 4000 and derivative designs that are more than 85% full > and yet > run at several times the 10-20MHz clock you are citing. For example, my HDTV > descrambler > core is guaranteed to run at 75 MHz in any of the 4000XV parts. In the small > parts, it fills > most of the device. The data sheet for that design is available on my website. >Article: 28928
Peter, I am sorry to hear about your bad experiences with certain Lithium batteries. We should perhaps contact consumer-product giants, like Casio and Seiko. I cannot believe they would tolerate a significant percentage of fast-discharging batteries. My ( very limited ) personal experience is that watches with lithium batteries last over 10 years, so does my old Pentax camera. But even the best battery can easily be discharged by a dirty pc-board, or by some sweaty fingerprints... Peter ( the other one ) Alfke, Xilinx Applications ============================================= Peter wrote: > >But: There is a self-discharge mechanism that is the real limitation. > >Good 3-V Lithium batteries have a shelf life of 15 years or more. > > This is a much bigger issue than it first appears. I have designed a > number of very low power products powered by lithium watch-type cells, > did a lot of evaluations of different cells, and it was amazing to > find how bad some cells were. One make (European) had a shelf life > consistently of about 1 year (to <20% capacity), the best Japanese > makes were probably >10 years, but "bad batches" happen right across > the board. > > I would be very unhappy relying on a shelf life of 10-15 years for a > critical application, e.g. where loss of battery power would make a > product *permanently* (i.e. even if the battery is replaced) > non-functional. All you need is a bad batch of cells and maybe 5 years > later you get a whole lot of extremely unhappy customers... > > Peter. > -- > Return address is invalid to help stop junk mail. > E-mail replies to zX80@digiYserve.com but remove the X and the Y. > Please do NOT copy usenet posts to email - it is NOT necessary.Article: 28929
Hello, I need to build a 'clocking system' who will generated 5 clocks signals with a single master clock. I've attached a pic, who will explain what i would like to do. Rising and falling time must not exceed 20nS at the output of Q0 to Q4 (see the pic), I think that the best way to built it is with GAL, but im not very familliar with them. IF anyone can help me to 'build' the code, it'll be appreciated. I can easily do it with uControleur ( PIC ) but the rise and fall time aren't fast enought. If you need more infos, feel free to ask. Regards, Marc S_mythicbird@hotmail.com PS: remove S_ for reply PS1: the less IC is better and in DIP version.Article: 28930
FPGA Design Engineer Duties & Responsibilities Responsible for implementing high speed FPGA designs for our test instrument products. Skills & Qualifications BSEE with at least 3 years experience, some in Xilinx or Altera FPGA's. Candidate must demonstrate proficiency with VHDL coding, simulation, and synthesis skills. Product experience in the datacom or telecom network protocols is a plus. This is a full-time, permanent position. If you are looking for a contract assignment, please do not reply to this ad. StingRay Systems offers a lucrative referral fee to those individuals who refer qualified technical candidates. If this ad is a fit for someone you know, please send their resume and contact information. If StingRay Systems places anyone you refer, we will pay you a generous referral fee as our way of saying, "Thank You." Please submit QUALIFIED resumes to: Amy Vaughn Technical Recruiter amy@stingraysys.comArticle: 28931
In article <3A6F99C7.F391BE72@xilinx.com>, Austin Lesea <austin.lesea@xilinx.com> wrote: (snip) > > The Panasonic battery website is excellent > http://www.panasonic.com/industrial_oem/battery/battery_home.htm > as well as > http://data.energizer.com/batteryinfo/buttons/primary_batteries.htm > http://www.sony-media.com/en/energy/products/primary.html > http://www.rayovac.com/products/index.shtml > > and many more, > (snip) Over the years, we have used Tadiran lithiums. Our experience with Tadiran batteries has been great. They have never caused us any trouble. Even at high ambient temperatures they have an excellent shelf life. The 1/2AA and AA can be ordered with leads so that they can be soldered down. IMHO, memory retention batteries should not be socketed. I just grabbed a dust-covered PCB that has not had power applied to it in at least six years. The Tadiran battery on it still reads 3.69V. http://www.tadiranbat.com/ -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/Article: 28932
I have not seen any problems with the timing analyzer in that regard. If you have all your paths properly constrained and you pass timing analysis, then the design will also meet static timing. There are many things that will cause a design to not work in the hardware, including incomplete timing specification leading to missed timing targets, incomplete functional simulation, and unforseen timing scenarios. The place and route algorithm has been modified over time, with the one in 3.1 being significantly different than the one in 1.5. The 3.1 router is faster, and for lower effort settings gives up sooner than the older PAR did. For floorplanned designs, I have not had many problems going to newer releases, and the new releases generally fix bugs that were annoying in older releases. Kang Liat Chuan wrote: > > Ray, > > I haven't got any experience doing Floorplanning but I think it is important > for high-speed design. > > I have looked at your datasheet (smpte_data.pdf). You used Xilinx M1.5. Last > year, a customer of mine was using M1.5 to route a design I described > earlier - 75% CLB on a xc40150xv, with 2 clocks (50MHz and 12.5MHz). They > discovered that the compiler will report no timing errors, but the hardware > verification fails. When they upgrade to version 3.1, the same design cannot > be routed completely. It seems that xilinx 3.1 is "stricter", but it is > consistent with the hardware. Have you encountered the same problem before? > > Regards, > LC > > Ray Andraka <ray@andraka.com> wrote in message > news:3A758E17.D8D215F2@andraka.com... > > FLoorplanning and designing to the architecture will let yo do much > better. > > I've > > done a large number of 4000 and derivative designs that are more than 85% > full > > and yet > > run at several times the 10-20MHz clock you are citing. For example, my > HDTV > > descrambler > > core is guaranteed to run at 75 MHz in any of the 4000XV parts. In the > small > > parts, it fills > > most of the device. The data sheet for that design is available on my > website. > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28933
Rick Filipkiewicz <rick@algor.co.uk> wrote:
: EZTag died off some time ago & has been replaced by a thing called the ``JTAG
: Programmer'' which can be downloaded as part of the free WebPack tools. It
: can handle all the XC95K devices [as well as being able to load those FPGAs
: that are JTAG loadable] and generate SVF files.
Yes, I've tried that program also. But when selecting Create SVF file from
the Output pull-down menu, the program only seems to generate a short svf
file, like:
//SVF File Created 2001/01/29 08:16:56
//JedecChain;
// FileRevision(JESDxxA);
// P ActionCode(cfg)
// Device
// MfrCode(049)
// PartName(XC95144XL)
// Path("D:\Temp\")
// File("design.jed")
// ;
//ChainEnd;
..and in svf format //-marks comment out the remainder of the line. So the
svf file generated by JTAG Programmer only contains a few rows of comments!
So how do I attach a jedec file to this svf file in order to program
a chip with a third-party boundary scan tool (which uses svf file format)?
Thanks in advance,
Mikko Heikkerö
mheikker@cc.hut.fi
--
Article: 28934Ray Andraka wrote: > I have not seen any problems with the timing analyzer in that regard. If you > have all your paths properly constrained and you pass timing analysis, then the > design will also meet static timing. There are many things that will cause a > design to not work in the hardware, including incomplete timing specification > leading to missed timing targets, incomplete functional simulation, and > unforseen timing scenarios. > > The place and route algorithm has been modified over time, with the one in 3.1 > being significantly different than the one in 1.5. The 3.1 router is faster, > and for lower effort settings gives up sooner than the older PAR did. For > floorplanned designs, I have not had many problems going to newer releases, and > the new releases generally fix bugs that were annoying in older releases. I have observed that PAR performance has not been improved dramatically on a %50-used XC40150XV device, when upgrading from M1.5 to M2.1i. I have not used M3.1i for XV devices. My opinion is that PAR is actually a kind of script which loads corresponding engine according to the technology from the installation directory (may be *.nph files?) and runs the tool with that engine. So, IMHO, PAR exec is technology-independent tool. The point is which DLL files or intermediate files it loads for run. Since the devices like XV are not under research any more, eg. datasheets are not updated, speed files updates have been more rarely than before, then we can say that corresponding PAR algorithm engines are not often optimized, in the same way. That's maybe why we would not see any significiant improve when switching between versions of Xilinx. UtkuArticle: 28935
Thank for your answering but in the Xilinx Answer Database I found that: "If using the Express HDL compiler, Express will automatically infer the STARTUP block for 4K/5K families if there is a common reset signal connected to all of the registers in the design." Is this the tool do you refer to? I have synthetized my vhdl code with the Synopsys tools (FPGA analyzer), is this a problem to use the set/reset global line without modifing the code?Article: 28936
noelia wrote: > Thank for your answering but in the > Xilinx Answer Database I found that: > "If using the Express HDL compiler, Express will automatically infer th= e STARTUP block for 4K/5K families if > there is a common reset signal connected to all of the registers in the= design." > Is this the tool do you refer to? > I have synthetized my vhdl code with > the Synopsys tools (FPGA analyzer), > is this a problem to use the set/reset global line without modifing the= code? Hi, the fpga-compiler also infer the startup block, too, if all ff's uses the= same set/reset signal. ciao J=F6rgArticle: 28937
Hello everybody, I just played around with a Spartan 2 demo board. One nice feature of Spartan2 / Virtex is the DLL, which can create 4 clock phases and even double the input clock. Unfortunately, the minimum input frequency is 25 MHz (according to the datasheet). But in our company we are doing lots of PDH/SDH stuff, where frequencies like 19.44 MHz and 16.384 MHz are very common. So I tried to feed the DLL with such "low" frequencies and it worked ;-))) down to 13.2 MHz. I know that this limit will change with temperature and piece to piece variations, but 13.2 is way lower than 25 MHz. I wil check out the temperature dependence in a few days. So my question. Are there some additional / inofficial informations regarding the DLLs?? -- MFG FalkArticle: 28938
I would use a 22V10. It has enough counter flip-flops and enough decoding logic ( AND-OR) to do the job, and it is fast and cheap, and available from many sources. Peter Alfke, Xilinx Marc wrote: > Hello, > > I need to build a 'clocking system' who will generated 5 > clocks signals with a single master clock. I've attached a pic, > who will explain what i would like to do. Rising and falling time > must not exceed 20nS at the output of Q0 to Q4 (see the pic), I think > that the best way to built it is with GAL, but im not very familliar > with them. IF anyone can help me to 'build' the code, it'll be > appreciated. I can easily do it with uControleur ( PIC ) but the rise > and fall time aren't fast enought. If you need more infos, feel > free to ask. > > Regards, > Marc > S_mythicbird@hotmail.com > > PS: remove S_ for reply > PS1: the less IC is better and in DIP version.Article: 28939
I screwed up the link it is http://www.signal-lsp.com not isp Sorry. As for how much it costs, I haven't asked but it looks like a neat toy. "Chuck Woodring" <woodringCT@nuwc.npt.navy.mil> wrote in message news:2001Jan26.123821.338@npt.nuwc.navy.mil... > try http://www.signal-isp.com they have a dspchip, a virtex chip and a > microcontroller all on a pci board. > >Article: 28940
noelia wrote: > > Thank for your answering but in the > Xilinx Answer Database I found that: > "If using the Express HDL compiler, Express will automatically infer the STARTUP block for 4K/5K families if > there is a common reset signal connected to all of the registers in the design." > Is this the tool do you refer to? I refer to the synthesis tool. > I have synthetized my vhdl code with > the Synopsys tools (FPGA analyzer), That would be FPGA Express. > is this a problem to use the set/reset global line without modifing the code? Again, you must make sure that the same reset signal is used to reset ALL of the flops in the design. That's what my other post said, and that's what the Xilinx Answer says. --aArticle: 28941
Austin Lesea wrote: > > Juan, > > Yes. That is what we use in the lab. The config bank Vcco is set to 3.3 > Vdc (per the spec sheet). > > Austin Austin, how long does it take? It was taking me > 4 minutes (from memory) to programme a spartan II 200 as opposed to ~ 20 seconds with a parallel cable. Nial.Article: 28942
check out www.systemC.org Jan Kindt <szolnoki@my-deja.com> schreef in bericht news:952cgt$jkf$1@nnrp1.deja.com... > Where I can get any C2VHDL freeware, trial, or time limited compiler? > (ArtBuilder,SystemC, etc..) > > Thank you, > Tibor Szolnoki > szoszo9@freemail.hu > > > Sent via Deja.com > http://www.deja.com/Article: 28943
http://www.xilinx.com/forge/forge.htm This page details the Forge product, the Lavalogic acquisition, and has a link to join the LEAP program. thanks, david. szoszo9@freemail.hu wrote: > Where I can download, the free, beta Leap-Forge compiler? > > Forge - LEAP_CD-1.19.2.5.tar > > Thak you: > Tibor Szolnoki > > Sent via Deja.com > http://www.deja.com/Article: 28944
the link is broken!! In article <ah6c6.14773$t3.3374499@typhoon.ne.mediaone.net>, pratipm@hotmail.com (Pratip Mukherjee) wrote: > A near fit would be http://technology.celoxica.com/boards/boards_001.asp > > In article <94qcnq$d46$1@nnrp1.deja.com>, jimmy75@my-deja.com wrote: > > > >> None of our boards will fit this particular application. A board > >> with a PCI bus interace is needed for the high-speed transfers > >> between the FPGA board memory and the PC running the desktop > >> publishing app. All our boards interface through the > >> parallel port which is too slow for this type of application. > > > >Yep. We need a PCI board for our purpose preferably with a DMA > >controller and a Xilinx Virtex chip(s) and lots of memory. If only we > >could make one on our own! > >I had a look on the web and didn't find all these features altogether > >in one board. We were hoping that somebody out there could help us. > > > >-- Jim > > > > > >Sent via Deja.com > >http://www.deja.com/ > Sent via Deja.com http://www.deja.com/Article: 28945
erika_uk@my-deja.com wrote: > > the link is broken!! > In article <ah6c6.14773$t3.3374499@typhoon.ne.mediaone.net>, > pratipm@hotmail.com (Pratip Mukherjee) wrote: > > A near fit would be > http://technology.celoxica.com/boards/boards_001.asp http://www.celoxica.com/products/boards/index.htm The RC1000PP is the board in question. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 28946
Falk Brunner <Falk.Brunner@gmx.de> writes: Very interesting. We had some problems with the DLL in a Virtex-E at 26 MHz, the DLL seems to unlock from time to time, may be jitter was an issue. We decided not to use it, because there was no real need in our application. However it worked fine at 60 MHz, it was no problem to achive 4x 60 MHz = 240 MHz. -- Chris Falk Brunner <Falk.Brunner@gmx.de> writes: > Hello everybody, > > I just played around with a Spartan 2 demo board. One nice feature of > Spartan2 / Virtex is the DLL, which can create 4 clock phases and even > double the input clock. Unfortunately, the minimum input frequency is 25 > MHz (according to the datasheet). But in our company we are doing lots > of PDH/SDH stuff, where frequencies like 19.44 MHz and 16.384 MHz are > very common. So I tried to feed the DLL with such "low" frequencies and > it worked ;-))) down to 13.2 MHz. I know that this limit will change > with temperature and piece to piece variations, but 13.2 is way lower > than 25 MHz. I wil check out the temperature dependence in a few days. > So my question. Are there some additional / inofficial informations > regarding the DLLs?? > > -- > MFG > FalkArticle: 28947
Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.parmita.com/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Your suggestions to make this FAQ more informative are welcome. Rajesh Bawankule (Also Visit Chip-Guru : http://www.chip-guru.com/ ) Sent via Deja.com http://www.deja.com/Article: 28948
Nial, Pretty short time for a 2V40 (~30 seconds). Little longer for a 2V1000 (~7 minutes). Don't even think about anything larger. A 2V6000 is ~30 minutes. At the serial port rate, it is pretty easy to figure out. The 2V6000 is ~20 million bits. For the smaller devices, the old Multilinx cable is OK. For anything larger, get the newer updated programming cable. Austin Nial Stewart wrote: > Austin Lesea wrote: > > > > Juan, > > > > Yes. That is what we use in the lab. The config bank Vcco is set to 3.3 > > Vdc (per the spec sheet). > > > > Austin > > Austin, how long does it take? > > It was taking me > 4 minutes (from memory) to programme a > spartan II 200 as opposed to ~ 20 seconds with a parallel > cable. > > Nial.Article: 28949
Hello, I want to run a 500-750MHz 12 bit bus into a Virtex II fpga. The driver is lvpecl with open emmiter outputs so it needs to be pulled down externally as well as terminated. Normally lvpecl lines are terminated with 50 Ohm resistors tied to Vccio-2V at the load which provides the pull down and impedance termination. For my application this would require 24 resistors under the FG456 fpga package and I would have to create the Vccio-2V voltage as well. Another alternative is to put 360 Ohm pulldown resistors at the 24 lvpecl drivers and then use just one 100 Ohm differential terminating resistor for each diff pair at the fpga receiver. Does anyone know if there is a better way to do this in the Virtex II? I saw that they now have Digitally Controlled Impedance, DCI, but XAPP253 says it cannot be used with any differential signalling. Should I bag the differential signalling and use one of the DCI standards at this speed? I have another application where the driver is lvds. Is it possible to do away with the external 100 Ohm termination resistors in that situation? Thanks for any advice. -- Pete Dudley Sandia Labs Albuquerque, NM padudle@sandia.gov
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z