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strshn99@my-deja.com writes: > I have a newbie question to ask you. What kind of Revision control > tools do you use when you are working on a design? Any recommendation > as to which is better? I use CVS for my VHDL source files.Article: 28476
Hello :
Now i have a question.At presently,i use the following tools to finish my design:
(1):synthesis---Synplify Pro6.13/Fpga Express5.4.
(2):P&R---------xilinx3.1
(3):simulation--modelsim5.4.
when i synthesis my design by Synplify Pro6.13,it generates *.edif netlist.Then,i use it and the constrains generated in xilinx to P&R in Xilinx.But it reports a lot of errors about the constrains.
In fact the constrains are right. Then i synthesis my design by Fpga Express3.5 .I find the netlist generated by Fpga Express than 200k by Synplify Pro6.13.Finally,i use this netlist to P&R in xilinx.it is OK.
Is the netlist generated by Fpga Express 3.5 and Synplify Pro6.13
different?
Why?
Thanks.
Article: 28477If you liked "The Art of Electronics" you'll love the brand new book "Industrial Electronics for Engineers, Chemists and Technicians: With Optional Lab Experiments." It provides quick, specific solutions for electronics issues like feedback oscillation, ground loops, impedance mismatch, noise pickup, and optimization of PID controllers. Written by a Ph.D. from Bell Labs, this very practical reference/self study guide will help you troubleshoot common problems with electronic equipment in the lab, the factory and even at home (for the serious hobbyist). For a complete description, including the table of contents, visit: http://www.williamandrew.com/titles/1467.html -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 28478
In article <3A5F3377.C9728B47@xilinx.com>, Austin Lesea <austin.lesea@xilinx.com> writes: > Spec sheet = contract. App note = we will support it just like the spec sheet. > A email from a Xilinx engineer is a written document, so it also must be treated > as a statement of 'suitablity for use' ... ie we would have to supply chips that > do what was said. Thus, my caution. Anything else, well, have fun. Many thanks. > But remember the comments about the possibility of a hidden voltage regulator, > and temperature compensation? Maybe the margin gained isn't all that much. That's the part that I was fishing for but wasn't smart enough to think of. Thanks again. [Why does the world keep getting more complicated?] -- These are my opinions, not necessarily my employers. I hate spam.Article: 28479
On Sun, 14 Jan 2001 17:34:42 -0800, chsw <chen.songwei@mail.zte.com.cn> wrote: hello, if you use synplify a bus in your top entity like data : out std_logic_vector ( 7 downto 0); is generateted in the edif netlist as data(7) .... data(0). With fpga express the bus ist described as data<7> ... data<0>. Therefore this difference is important for your constraint file for the xilinx tool. example xilinx.ucf: with synplify: NET data(7) LOC =P10; ... NET data(0) LOC =P17; with fpga express NET data<7> LOC = P10; ... NET data<0> LOC = P17; thats one difference i found out ! >Hello : > Now i have a question.At presently,i use the following tools to finish my design: > (1):synthesis---Synplify Pro6.13/Fpga Express5.4. > (2):P&R---------xilinx3.1 > (3):simulation--modelsim5.4. > when i synthesis my design by Synplify Pro6.13,it generates *.edif netlist.Then,i use it and the constrains generated in xilinx to P&R in Xilinx.But it reports a lot of errors about the constrains. >In fact the constrains are right. Then i synthesis my design by Fpga Express3.5 .I find the netlist generated by Fpga Express than 200k by Synplify Pro6.13.Finally,i use this netlist to P&R in xilinx.it is OK. > Is the netlist generated by Fpga Express 3.5 and Synplify Pro6.13 >different? > Why? > Thanks. --------------------------------- Arnd Sluiter Design Engineer Center for Sensor Systems (ZESS) University of Siegen Paul-Bonatz-Str. 9-11 57068 Siegen Germany Fon: ++49271/ 740-2465 Fax.: ++49271/ 740-2336 e-mail: sluiter@zess.uni-siegen.de ---------------------------------Article: 28480
<pineji@my-deja.com> a écrit dans le message : 93t0n1$s6u$1@nnrp1.deja.com... > In article <93n68n$c8v$1@s1.read.news.oleane.net>, > "Le Mer Michel" <michel.lemer@sta.fr> wrote: > > Hi > > The exact message is : > > # ** Warning: */APEX20k_ASYNCH_MEM SETUP High VIOLATION ON WADDR(1) > WITH > > RESPECT TO WE; > > # Expected := 2.06 ns; Observed := 1.41 ns; At : 49989.401 ns > > # Time: 49989401 ps Iteration: 4 Instance: > > /test/i1/i1_ai3_ai2_ai1_alpm_ram_dp_component_asram_asegment_a0_a_a4_a > /apexm > > em > > # ** Warning: */APEX20k_ASYNCH_MEM SETUP Low VIOLATION ON WADDR(0) > WITH > > RESPECT TO WE; > > # Expected := 2.06 ns; Observed := 1.41 ns; At : 49989.401 ns > > # Time: 49989401 ps Iteration: 4 Instance: > > /test/i1/i1_ai3_ai2_ai1_alpm_ram_dp_component_asram_asegment_a0_a_a4_a > /apexm > > em > > .... > > > > Michel Le Mer. > > > > S.K. Sharma <sanjay.kumar.sharma@philips.com> a écrit dans le > message : > > 93hoat$r9c$1@porthos.nl.uu.net... > > > Hi Michel, > > > Could you post the exact error message! > > > Thanks > > > Sanjay > > > > > > -- > > > Sanjay Kumar Sharma > > > ASIC Design Engineer > > > Philips Semiconductors > > > Eindhoven, The Netherlands > > > "Le Mer Michel" <michel.lemer@sta.fr> wrote in message > > > news:93c9gj$kk4$1@s1.read.news.oleane.net... > > > > Hello > > > > > > > > I have a strange message about APEX20K_ timing violation during > > simulation > > > > despite I use the APEX 20KE family and that all the frequencies > are met > > > > according to Quartus. > > > > > > > > Any suggestions? > > > > > > > > Thanks > > > > -- > > > > Michel Le Mer immeuble Cerium > > > > STA 12, square du Chene Germain > > > > 02 23 20 04 72 35510 Cesson-Sevigne > > > > > > > > > > > > > > > > > > > > > > With the small amount of information provided I'd venture to guess > that you are using the built in SRAM in an asynchronous fashion. The > static timing check should have yielded an error but did not either > because a generated clock was not properly described to Quartus or the > tool may just be incapable of detecting this error for this > configuration. I would suggest using the SRAM in its synchonous > configuration and generating the control signals for the synchronous > SRAM with the same clock as the SRAM. > > Josh > -- > Altera FPGA Consulting- Not ACAP Affiliated > > > Sent via Deja.com > http://www.deja.com/ Hi I use a synchronous RAM and all the signals are synchronous. The source code is generated with the Quartus Megawizard. The source code is below. As you can see, everything is registered. Michel Le Mer. -- megafunction wizard: %LPM_RAM_DP% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_ram_dp -- ============================================================ -- File Name: position_ram.vhd -- Megafunction Name(s): -- lpm_ram_dp -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- ************************************************************ --Copyright (C) 1991-2000 Altera Corporation --Any megafunction design, and related net list (encrypted or decrypted), --support information, device programming or simulation file, and any other --associated documentation or information provided by Altera or a partner --under Altera's Megafunction Partnership Program may be used only to --program PLD devices (but not masked PLD devices) from Altera. Any other --use of such megafunction design, net list, support information, device --programming or simulation file, or any other related documentation or --information is prohibited for any other purpose, including, but not --limited to modification, reverse engineering, de-compiling, or use with --any other silicon devices, unless such use is explicitly licensed under --a separate agreement with Altera or a megafunction partner. Title to --the intellectual property, including patents, copyrights, trademarks, --trade secrets, or maskworks, embodied in any such megafunction design, --net list, support information, device programming or simulation file, or --any other related documentation or information provided by Altera or a --megafunction partner, remains with Altera, the megafunction partner, or --their respective licensors. No other licenses, including any licenses --needed under any third party's intellectual property, are provided herein. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY LPM; USE LPM.lpm_components.all; ENTITY position_ram IS PORT ( data : IN STD_LOGIC_VECTOR (6 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0); wren : IN STD_LOGIC := '1'; clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END position_ram; ARCHITECTURE SYN OF position_ram IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); COMPONENT lpm_ram_dp GENERIC ( lpm_width : NATURAL; lpm_widthad : NATURAL; lpm_indata : STRING; lpm_wraddress_control : STRING; lpm_rdaddress_control : STRING; lpm_outdata : STRING; lpm_file : STRING; lpm_hint : STRING ); PORT ( rdclock : IN STD_LOGIC ; wren : IN STD_LOGIC ; wrclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); data : IN STD_LOGIC_VECTOR (6 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(6 DOWNTO 0); lpm_ram_dp_component : lpm_ram_dp GENERIC MAP ( lpm_width => 7, lpm_widthad => 5, lpm_indata => "REGISTERED", lpm_wraddress_control => "REGISTERED", lpm_rdaddress_control => "REGISTERED", lpm_outdata => "REGISTERED", lpm_file => "D:/My_designs/LS_modulateur/horloge/src/position_ram.hex", lpm_hint => "USE_EAB=ON" ) PORT MAP ( rdclock => clock, wren => wren, wrclock => clock, data => data, rdaddress => rdaddress, wraddress => wraddress, q => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: WidthData NUMERIC "7" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" -- Retrieval info: PRIVATE: Clock NUMERIC "0" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: PRIVATE: REGdata NUMERIC "1" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" -- Retrieval info: PRIVATE: REGrren NUMERIC "1" -- Retrieval info: PRIVATE: REGq NUMERIC "1" -- Retrieval info: PRIVATE: enable NUMERIC "0" -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRq NUMERIC "0" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "D:\My_designs\LS_modulateur\horloge\src\position_ram.hex" -- Retrieval info: PRIVATE: UseLCs NUMERIC "0" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" -- Retrieval info: CONSTANT: LPM_WIDTHAD NUMERIC "5" -- Retrieval info: CONSTANT: LPM_INDATA STRING "REGISTERED" -- Retrieval info: CONSTANT: LPM_WRADDRESS_CONTROL STRING "REGISTERED" -- Retrieval info: CONSTANT: LPM_RDADDRESS_CONTROL STRING "REGISTERED" -- Retrieval info: CONSTANT: LPM_OUTDATA STRING "REGISTERED" -- Retrieval info: CONSTANT: LPM_FILE STRING "D:/My_designs/LS_modulateur/horloge/src/position_ram.hex" -- Retrieval info: CONSTANT: LPM_HINT STRING "USE_EAB=ON" -- Retrieval info: USED_PORT: data 0 0 7 0 INPUT NODEFVAL data[6..0] -- Retrieval info: USED_PORT: q 0 0 7 0 OUTPUT NODEFVAL q[6..0] -- Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0] -- Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL rdaddress[4..0] -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: CONNECT: @data 0 0 7 0 data 0 0 7 0 -- Retrieval info: CONNECT: q 0 0 7 0 @q 0 0 7 0 -- Retrieval info: CONNECT: @wraddress 0 0 5 0 wraddress 0 0 5 0 -- Retrieval info: CONNECT: @rdaddress 0 0 5 0 rdaddress 0 0 5 0 -- Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: @wrclock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @rdclock 0 0 0 0 clock 0 0 0 0Article: 28481
Hello: when i synthesis my design by synplify ,it seems that the fifo of the design are not synthesis from the report generated by xilinx P&R .In it,the fifo of my design is generated by Xilinx CORE Generator tool.when it is synthesised by synplify , how it is instantiated? thanksArticle: 28482
Hi! I am looking for a prototyping board with a great Virtex FPGA. This board should have PCI communication, RAM modules and interfacing software. Thanks a lot, -- Juan University of Extremadura. SpainArticle: 28483
<ppetener@my-deja.com> skrev i meddelandet = news:93shhl$gtd$1@nnrp1.deja.com... : Hi, :=20 : When importing a netlist (edif) from FPGA Compiler : II with ATMEL 6.0 (as a design) I get this : message: :=20 : "Unable to create instance ... of AML064 from : ATMEL - master not found" :=20 : looking inside the edif netlist file, I see the : following: : (edif ATA66Host : (edifVersion 2 0 0) Typically you ask this question to fpga@atmel.com --=20 Best Regards Ulf at atmel dot com These comment are intended to be my own personal view and may or may not be shared by my Employer Atmel Sweden.Article: 28484
In comp.lang.vhdl Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: > strshn99@my-deja.com writes: >> I have a newbie question to ask you. What kind of Revision control >> tools do you use when you are working on a design? Any recommendation >> as to which is better? > I use CVS for my VHDL source files. We use ClearCase from Rational at my work. Works well. Handles binary files better than CVS. Hamish PS Hi Allan. -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 28485
Hi, take a look at www.silicon-software.com and www.isytec.de. If these products doesn't fit your needs you can search the collection of vendors at www.optimagic.com. ciao J=F6rg > Hi! > > I am looking for a prototyping board with a great Virtex FPGA. This > board should have PCI communication, RAM modules and interfacing > software. > > Thanks a lot, > > -- Juan > University of Extremadura. SpainArticle: 28486
This is a multi-part message in MIME format. --------------9F129D1B9BBEC9E660062175 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Alex, I would recommend that you download the latest version of JTAG Programmer. This is available on the web under WebPACK. This will give you 3.1SP6 version. I have seen these problems before with early versions of the s/w. One issue to be cautious of is if you are holding the PROG line of the FPGA low, this will hold the TAP of the V300 in RESET, thus breaking the JTAG chain. Dave Alex Rast wrote: > We are running into a diabolic JTAG failure with an XC95144XL-CS144 part. Just > to give you the environment, the programming PC is a Windows NT 4.0, SP4 > machine running Xilinx's Foundation 2.1i, SP6 software (a big POS, but that is > another story) We are using the MultiLINX cable for programming (because our > hardware also has an XCV300 in it). I configured the cable for serial port, > 38,400 baud. The XC95144 chip sits on a card that plugs into the motherboard > where our JTAG header is going. In any case, when I go to download a > config into the chip, the JTAG prog S/W comes back with a message > "...boundary-scan chain test failed at bit position '7' on instance > '9500bas(Device1)'..." > > I have checked our device boards, made sure we're getting power to the CPLD, > verified that the JTAG signal pins connect to the board carrying the XC95144, > swapped boards, changed baud rates on the cable, and done pretty much > everything Xlinx recommends in their appnotes on debugging JTAG problems, as > well as as much testing of our own hardware as I can. > > If you look at the output of the cable with a scope, none of the JTAG lines > ever see data on them. I'm suspicious we may have a bad cable, but are there > other possibilities? Is there some oddball software incompatibility? Strange > idisyncracies in the XC95144? > > Please reply to both e-mail addresses below. > > Alex Rast > arast@inficom.com > arast@qwest.net --------------9F129D1B9BBEC9E660062175 Content-Type: text/x-vcard; charset=us-ascii; name="dhawke.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for David Hawke Content-Disposition: attachment; filename="dhawke.vcf" begin:vcard n:Hawke;David Hawke tel;cell:(+44) 778 875 5002 tel;work:(+44) 870 7350 517 x-mozilla-html:TRUE org:<br><img src="http://www.xilinx.com/images/smvirtex.gif" alt="Xilinx"> version:2.1 email;internet:dhawke@xilinx.com title:XILINX Field Applications Engineer adr;quoted-printable:;;Xilinx Northern Europe=0D=0ABenchmark House;203 Brooklands road;Weybridge;; x-mozilla-cpt:;2672 fn:David Hawke end:vcard --------------9F129D1B9BBEC9E660062175--Article: 28487
I'm experiencing problems when trying to compile a design (vhdl) into a user work library rather than the default work library. I get unbound component warnings, which suggests that the compiler can't see the user libraries. As an experiment I compiled the whole design into the default work library (subsequently had to change all vhdl user library references in the code) which works!. Has anybody had similar problems? or know where I'm going wrong? Lee -- Lee Weston, Philips Semiconductors, CS-DM Southampton, SO15 0DJ, UK mailto:lee.weston@philips.com seri:weston@ukpsshp1 phone: +44 (0) 23 80316471 fax +44 (0) 23 80316303Article: 28488
That's possible but CVS is for free (http://www.cvshome.org) Jan Vermaete, Alcatel Bell Space NV Hamish Moffatt VK3SB wrote: > > In comp.lang.vhdl Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: > > strshn99@my-deja.com writes: > >> I have a newbie question to ask you. What kind of Revision control > >> tools do you use when you are working on a design? Any recommendation > >> as to which is better? > > > I use CVS for my VHDL source files. > > We use ClearCase from Rational at my work. Works well. > Handles binary files better than CVS. > > Hamish > > PS Hi Allan. > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 28489
Hi I use a Spartan device, and some thing is wrong when programming it. I know that I can check on an out pin for a check sum. This check sum tells me when the fpga is right programed. But whitch pin do I have to check on? Thankful for help BL Sent via Deja.com http://www.deja.com/Article: 28490
Hello, Xilinx Virtex-II has now been officially announced. Check out the press release: http://www.xilinx.com/prs_rls/vtx2ship.htm and the Virtex-II Handbook: http://www.xilinx.com/products/virtex/handbook/index.htm Some highlights are: - digitally controlled impedances for input and output pins - new resources for clock management and clock synthesis - digital spread spectrum clocking - encrypted bitstreams - dedicated multipliers Go and see for yourself! Regards, Rune BaeverrudArticle: 28491
Hi, Does the tool handle it well ? --Erika In article <979567585.218715@news2.cybercity.dk>, "Rune Baeverrud" <fpga@no.spam.iname.com> wrote: > Hello, > > Xilinx Virtex-II has now been officially announced. > > Check out the press release: > http://www.xilinx.com/prs_rls/vtx2ship.htm > > and the Virtex-II Handbook: > http://www.xilinx.com/products/virtex/handbook/index.htm > > Some highlights are: > - digitally controlled impedances for input and output pins > - new resources for clock management and clock synthesis > - digital spread spectrum clocking > - encrypted bitstreams > - dedicated multipliers > > Go and see for yourself! > > Regards, > Rune Baeverrud > > Sent via Deja.com http://www.deja.com/Article: 28492
Erika, The new features are very well supported. We have been pushing designs by the thousands through the tools since last year to (hopefully) remove as many bugs as humanly possible. I think our software team has done a superb job supporting all of the new features. And how would I know? I manage the FPGA Lab team, who's task it is to test every single feature (characterization and verification). Additionally our product test team also uses our own software (as well as everyone else here). Enjoy, Austin erika_uk@my-deja.com wrote: > Hi, > > Does the tool handle it well ? > > --Erika > In article <979567585.218715@news2.cybercity.dk>, > "Rune Baeverrud" <fpga@no.spam.iname.com> wrote: > > Hello, > > > > Xilinx Virtex-II has now been officially announced. > > > > Check out the press release: > > http://www.xilinx.com/prs_rls/vtx2ship.htm > > > > and the Virtex-II Handbook: > > http://www.xilinx.com/products/virtex/handbook/index.htm > > > > Some highlights are: > > - digitally controlled impedances for input and output pins > > - new resources for clock management and clock synthesis > > - digital spread spectrum clocking > > - encrypted bitstreams > > - dedicated multipliers > > > > Go and see for yourself! > > > > Regards, > > Rune Baeverrud > > > > > > Sent via Deja.com > http://www.deja.com/Article: 28493
THere are a number of them out there now. Go to www.optimagic.com for a fairly comprehensive list of boards. Juan Antonio Gómez Pulido wrote: > > Hi! > > I am looking for a prototyping board with a great Virtex FPGA. This > board should have PCI communication, RAM modules and interfacing > software. > > Thanks a lot, > > -- Juan > University of Extremadura. Spain -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28494
It shouldn't be being synthesized by synplicity. Synplicity should be instantiating it as a black box. The edif netlist has to be in your design directory when you get into the xilinx tools so that they can elaborate that netlist. chsw wrote: > > Hello: > when i synthesis my design by synplify ,it seems that the fifo of the design are not synthesis from the report generated by xilinx P&R .In it,the fifo of my design is generated by Xilinx CORE Generator tool.when it is synthesised by synplify , how it is instantiated? > thanks -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28495
erika_uk@my-deja.com wrote: > > Hi, > > Does the tool handle it well ? Like any other new architecture, I suspect it will take a while for the tools to catch up to the new silicon. In the past, it has taken about a year after the introduction of the silicon before the tools were close to ready for prime time. Macro libraries lag even further behind. In the case of Virtex, I didn't start recommending them for customers until a little over a year ago...because of tools issues. > > --Erika > In article <979567585.218715@news2.cybercity.dk>, > "Rune Baeverrud" <fpga@no.spam.iname.com> wrote: > > Hello, > > > > Xilinx Virtex-II has now been officially announced. > > > > Check out the press release: > > http://www.xilinx.com/prs_rls/vtx2ship.htm > > > > and the Virtex-II Handbook: > > http://www.xilinx.com/products/virtex/handbook/index.htm > > > > Some highlights are: > > - digitally controlled impedances for input and output pins > > - new resources for clock management and clock synthesis > > - digital spread spectrum clocking > > - encrypted bitstreams > > - dedicated multipliers > > > > Go and see for yourself! > > > > Regards, > > Rune Baeverrud > > > > > > Sent via Deja.com > http://www.deja.com/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28496
me i'll ask, why grey counter and not a simple binary ? In article <3A60E39B.B6CDBAF@earthlink.net>, lenihan3weNOSPAM@earthlink.net wrote: > This sounds convenient, but the problem remains .... if a normal binary up > counter looks like this: > > always @(posedge clk) count <= count +1; > > and we want the synthesis tool to turn this into a grey code counter for us: > > always @(posedge clk) count <= count +1 /* synthesis counter = grey */ ; > > .... then there's going to be a big discrepency between RTL & gate- level > simulation results, if our simulator checks the counter! > > > > > What I'd like to see (and I think I suggested this to the Synplicity > > guys) is an attribute or something in the synthesis tool that lets you > > select gray-code or binary-code counters. > > > > That would be useful. > > > > -- a > > ---------------------------- > > Andy Peters > > Sr. Electrical Engineer > > National Optical Astronomy Observatory > > 950 N Cherry Ave > > Tucson, AZ 85719 > > apeters (at) n o a o [dot] e d u > > -- > ============================== > William Lenihan > lenihan3weNOSPAM@earthlink.net > .... remove "NOSPAM" when replying > ============================== > > Sent via Deja.com http://www.deja.com/Article: 28497
Good Question: In a Grey counter, only one bit changes on any count. So when you run two Grey counters asynchronously ( like the address counters in an asynchronous FIFO) you can compare the two counters reliably, even during the transition, because there will never be a "far-out" code. You cannot do that with a binary counter, e.g. when it changes from 7 to 8. During that transition, you might accidentally read any possible 4-bit code. Peter Alfke ===================== erika_uk@my-deja.com wrote: > me i'll ask, why grey counter and not a simple binary ? > > In article <3A60E39B.B6CDBAF@earthlink.net>, > lenihan3weNOSPAM@earthlink.net wrote: > > This sounds convenient, but the problem remains .... if a normal > binary up > > counter looks like this: > > > > always @(posedge clk) count <= count +1; > > > > and we want the synthesis tool to turn this into a grey code counter > for us: > > > > always @(posedge clk) count <= count +1 /* synthesis counter = grey > */ ; > > > > .... then there's going to be a big discrepency between RTL & gate- > level > > simulation results, if our simulator checks the counter! > > > > > > > > What I'd like to see (and I think I suggested this to the Synplicity > > > guys) is an attribute or something in the synthesis tool that lets > you > > > select gray-code or binary-code counters. > > > > > > That would be useful. > > > > > > -- a > > > ---------------------------- > > > Andy Peters > > > Sr. Electrical Engineer > > > National Optical Astronomy Observatory > > > 950 N Cherry Ave > > > Tucson, AZ 85719 > > > apeters (at) n o a o [dot] e d u > > > > -- > > ============================== > > William Lenihan > > lenihan3weNOSPAM@earthlink.net > > .... remove "NOSPAM" when replying > > ============================== > > > > > > Sent via Deja.com > http://www.deja.com/Article: 28498
Ray, this may be the rare case where your long ( and distinguished ! ) experience misleads you. In the 13 years I have been at Xilinx, I have never seen us as well prepared for the introduction of a new family, as we are today with Virtex-II. We have had software since last October, silicon since late November, and have been testing it furiously ever since. We finished writing a 536-page Virtex-II Handbook in December, and shipped many thousands of printed copies in early January. We have had extensive training for our FAEs last fall, and we are putting together the slides for a public seminar right now. Highest on my list of exciting features is the Digitally Controlled Impedance, which effectively puts the series termination resistor right into the output driver, or the parallel termination right into the input buffer ( all optionally of course). It will be a gods-end for people putting >500-pin packages on a pc-board, not having to bother with resistor packs... Hundreds of 18 x 18 multipliers (<4ns) are nice, as are 16 global clocks in all devices, each with an input mux that can glitch-free select between two sources. Ripple carry delay is 45 ps per bit, a 24-bit synchronous counter runs at 300 MHz, etc. Exciting stuff. As I mentioned,earlier, I am working on a 1 GHz frequency counter, on a 200 MHz asynchronous FIFO, and on metastability testing. Sorry for the blatant propaganda. Got carried away by my enthusiasm. I had been impatiently waiting for the Ides of January, for a long time ! Peter Alfke, Xilinx Applications ===================================== Ray Andraka wrote: > erika_uk@my-deja.com wrote: > > > > Hi, > > > > Does the tool handle it well ? > > Like any other new architecture, I suspect it will take a while > for the tools to catch up to the new silicon. In the past, > it has taken about a year after the introduction of the > silicon before the tools were close to ready for prime time. > Macro libraries lag even further behind. In the case of Virtex, > I didn't start recommending them for customers until a little > over a year ago...because of tools issues. > > > > > --Erika > > In article <979567585.218715@news2.cybercity.dk>, > > "Rune Baeverrud" <fpga@no.spam.iname.com> wrote: > > > Hello, > > > > > > Xilinx Virtex-II has now been officially announced. > > > > > > Check out the press release: > > > http://www.xilinx.com/prs_rls/vtx2ship.htm > > > > > > and the Virtex-II Handbook: > > > http://www.xilinx.com/products/virtex/handbook/index.htm > > > > > > Some highlights are: > > > - digitally controlled impedances for input and output pins > > > - new resources for clock management and clock synthesis > > > - digital spread spectrum clocking > > > - encrypted bitstreams > > > - dedicated multipliers > > > > > > Go and see for yourself! > > > > > > Regards, > > > Rune Baeverrud > > > > > > > > > > Sent via Deja.com > > http://www.deja.com/ > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.comArticle: 28499
Juan, A list of Prototyping Platforms is also maintained on the xilinx.com site: http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protoboards_page (http://www.xilinx.com -> Products -> Devices -> Virtex Series -> Demo Boards) thanks, david. Juan Antonio Gómez Pulido wrote: > Hi! > > I am looking for a prototyping board with a great Virtex FPGA. This > board should have PCI communication, RAM modules and interfacing > software. > > Thanks a lot, > > -- Juan > University of Extremadura. Spain
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