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Yuri G Tregubov <ytregubov@my-deja.com> wrote in <93uk2f$3ou$1@nnrp1.deja.com>: >Has anybody ported Altera Jam player to the >SHARC platform ? What are the main pitfalls? I haven't ported Jam (I do use it on a PC) but I have ported 80186 code. I can tell you that the main issue is the 8/32 bit difference in chars and code that expects that chars are one byte wide. In particular, look out for code that expects that casting to (char) will reduce a 32 bit value to 8 bits. For this I've defined a macro MASK_TO_8_BITS(v) which, for byte-like processors, just does a cast to char and, for the SHARC (with 32-bit chars), performs a mask with 0xFF.Article: 28501
<eml@riverside-machines.com.NOSPAM> wrote in message news:3a5f7a06.46595328@news.dial.pipex.com... > This is exactly what a parallel factorisation is. Assume you've got 8 > serial data bits going into a 4-bit LFSR. When you put in the 1st bit, > you get 4 equations for the next state of the LFSR. Iterate 7 more > times, for the remaining data bits, using the new values of the LFSR, > and the last set of 4 equations is the result; these define the value > of each bit of the LFSR after an entire byte is shifted in. You'll > find that there are lots of common terms, and you can factorise them > out. Eventually, you'll end up with lots of XORs, to give you a > parallel implementation of the CRC. The TAXI app note covers it all if > you can find it. > > Evan I will continue searching for the elusive app note... Sounds like just the thing I need. Regards, JamieArticle: 28502
strshn99@my-deja.com writes:
> I have a newbie question to ask you. What kind of Revision control
> tools do you use when you are working on a design? Any recommendation
> as to which is better?
I've used SCCS, RCS and CVS. Earlier (when disk-space was expensive) I
had only source files under revision control. Now I check in all files
which can't be easily generated in reasonable time. I tag RTL files,
its equivalent netlist, as well as SVF and MCS files for production to
know what was generated from a set of source files.
CVS is free (so is RCS) and can operate in server mode. I've used this
(together with ssh) to work on design located 10,000 miles away.
It's also smart to include the revision numbers for the various RTL
files in the simulation dump files. Most of my source files have
something like this:
// synopsys translate_off
reg [639:0] RCS_ID;
initial
begin RCS_ID = "$Id: icrc.v,v 2.7 2000/07/06 09:12:42 pegu Exp $"; end
// synopsys translate_on
Then you can observe the source revision numbers in signalscan or
whatever your favorite waveform tool is.
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 28503Jamie Sanderson wrote: > > <eml@riverside-machines.com.NOSPAM> wrote in message > news:3a5f7a06.46595328@news.dial.pipex.com... > > This is exactly what a parallel factorisation is. Assume you've got 8 > > serial data bits going into a 4-bit LFSR. When you put in the 1st bit, > > you get 4 equations for the next state of the LFSR. Iterate 7 more > > times, for the remaining data bits, using the new values of the LFSR, > > and the last set of 4 equations is the result; these define the value > > of each bit of the LFSR after an entire byte is shifted in. You'll > > find that there are lots of common terms, and you can factorise them > > out. Eventually, you'll end up with lots of XORs, to give you a > > parallel implementation of the CRC. The TAXI app note covers it all if > > you can find it. > > > > Evan > > I will continue searching for the elusive app note... Sounds like just the > thing I need. > > Regards, > Jamie There is no reason that I can think of that the TAXI chip would have anything to say about this topic, although there might be something about generating and checking CRCs in either the SCC manual or the Ethernet chip manuals (it definitely appears in chapter 11 of the Motorola McMOS Handbook, published in 1974, as well as possibly the original Ethernet (DIX) specifications). An alta-vista on '+CRC +polynomial +remainder' turns up a large number of references on the basic CRC techniques (needed as a precursor to emls' description), some of them being: http://www.cl.cam.ac.uk/Research/SRG/bluebook/21/crc/crc.html http://users.originet.com.br/martinnorris/crcjava.html http://ftp.rad.com/networks/1994/err_con/crc_how.htm There are probably a lot more down this same vein. Once these techniques are understood, the algorithm that Gray uses is constructed by performing the one-bit serial technique four times in sequence, as eml is describing above. -- PhilArticle: 28504
Also, the switching noise may be substantially less as only one bit is changing at a time. Peter Alfke wrote: > Good Question: > In a Grey counter, only one bit changes on any count. So when you run two > Grey counters asynchronously ( like the address counters in an asynchronous > FIFO) you can compare the two counters reliably, even during the > transition, because there will never be a "far-out" code. > You cannot do that with a binary counter, e.g. when it changes from 7 to 8. > During that transition, you might accidentally read any possible 4-bit > code. > > Peter Alfke > ===================== > erika_uk@my-deja.com wrote: > > > me i'll ask, why grey counter and not a simple binary ? > > > > In article <3A60E39B.B6CDBAF@earthlink.net>, > > lenihan3weNOSPAM@earthlink.net wrote: > > > This sounds convenient, but the problem remains .... if a normal > > binary up > > > counter looks like this: > > > > > > always @(posedge clk) count <= count +1; > > > > > > and we want the synthesis tool to turn this into a grey code counter > > for us: > > > > > > always @(posedge clk) count <= count +1 /* synthesis counter = grey > > */ ; > > > > > > .... then there's going to be a big discrepency between RTL & gate- > > level > > > simulation results, if our simulator checks the counter! > > > > > > > > > > > What I'd like to see (and I think I suggested this to the Synplicity > > > > guys) is an attribute or something in the synthesis tool that lets > > you > > > > select gray-code or binary-code counters. > > > > > > > > That would be useful. > > > > > > > > -- a > > > > ---------------------------- > > > > Andy Peters > > > > Sr. Electrical Engineer > > > > National Optical Astronomy Observatory > > > > 950 N Cherry Ave > > > > Tucson, AZ 85719 > > > > apeters (at) n o a o [dot] e d u > > > > > > -- > > > ============================== > > > William Lenihan > > > lenihan3weNOSPAM@earthlink.net > > > .... remove "NOSPAM" when replying > > > ============================== > > > > > > > > > > Sent via Deja.com > > http://www.deja.com/Article: 28505
Simon Gornall <simon@unique-id.com> wrote in
<3A6026B5.D66C4E92@unique-id.com>:
>But we are talking about the Alliance tools. Should Xilinx ever
>distribute (hint! hint!) Linux tools, I'd expect them to be in .rpm
>format. I don't mean 'expect' as in "they'd better be", I mean it in the
>sense "most distributors do"
RPM's are definitely desirable if you limit yourself to Red Hat and
derivative distributions. Developers outside the RH world tend to prefer
tarballs as they're more portable. Note that Linux binaries can be used
with FreeBSD and Solaris with suitable compatibility libraries installed.
>Under Linux it's the opposite by convention - you install into
>/opt/<package>/{lib,bin,man,etc...} or /usr/local/<package>/... I think
>the /usr/local... is no longer part of the LFS spec though, I think
>/opt/<package> is the recommended layout now.
/opt is a relatively new thing inherited from Sun. /usr/local is now
reserved strictly for administrator-installed packages, and packages should
not default to using /usr/local. (For example, I use /usr/local/sbin for my
personally-written admin scripts.)
>Two "absolutely safe" methods come to mind for supporting linux:
> o Xilinx could install their own versions of the shared libs
> they use, and use LD_LIBRARY_PATH as above, or
> o They could link the programs statically.
The latter is preferable. If a specific library is needed, static binding
will trim off the unneeded parts. Further, if an app spawns a system
process, you don't want a custom LD_LIBRARY_PATH passed through to the
child process, causing it to use the wrong library.
Article: 28506Peter Alfke wrote: > <snip> > Highest on my list of exciting features is the Digitally Controlled > Impedance, which effectively puts the series termination resistor > right into the output driver, or the parallel termination right into > the input buffer ( all optionally of course). It will be a gods-end > for people putting >500-pin packages on a pc-board, not having to > bother with resistor packs... Just getting my head around this feature. The notes show a block of 8, sharing a pair of RefUP and RefDown bias resistors. So, what is the Static ( DC ) power component when using this feature ? - jgArticle: 28507
Hello people, just came by to inform you about this site. It's a very good and advanced site related to the seminconductor industry, maybe it might be interesting for you to check it out.. :) http://www.datasheetlocator.com/nl Greetings, CharlieArticle: 28508
Apologies to all, there was a bug in the code previously posted.
There goes my reputation, shot to pieces!
Sadly, netscape translates TAB characters to spaces, and messes up the columnation...
- fixed a bug in the most significant bit-pair
- parameterised the counter width
- mapped the reset/init function to look up table logic, rather than async clear/preset
If anyone wants the MAX+2 source code file and/or simulation file, drop me an email and
I'll email it out to you. Posting binaries on this newsgroup is a no-no.
-- Bob Elkind, eteam@aracnet.com
========= START OF CODE ===========================
constant last = 4; -- specify the counter width in bit-pairs (i.e. if last == 4, then counter is 8 bits wide)
-- this parameter can just as easily be passed from the subroutine "call"
SUBDESIGN grey8
%
REVISED -- MSBs aware, so that most-significant bit-pair
counts on every "carry in".
8-bit grey code counter, generalised to be extensible.
structure is a unidirectional ripple carry, similar
to conventional binary counter.
counter is up *only*, not bidirectional.
Bob Elkind, eteam@aracnet.com
%
(
clock : INPUT; -- main clock
enable : input=vcc; -- clock enable (or count enable) (or could use the cry[0] term)
reset : input=gnd; -- reset the puppy, default is off
out[(last*2-1)..0] : output; -- outputs
)
variable
up[last..1] : srffe;
temp[last..1][1..0] : node;
cry[last..0] : node;
cnt[last..1][1..0] : dffe;
begin
up[].clk = clock;
up[].ena = enable;
cnt[][].clk = clock;
cnt[][].ena = enable;
cry[0] = vcc; -- carry in to LSB is always asserted
%
The grey counter is segmented into bit pairs.
For each bit-pair, there are 4 count values, and 2 direction-of-count
values, hence 8 states.
Sequence is:
value direction carry out
0 up 0
1 up 0
3 up 0
2 up 1
2 down 0
3 down 0
1 down 0
0 down 1
This is sequence is implemented as a case statement or state machine,
for each of the bit-pair segments.
Also note that a "carry out" from the bit-pair to the next more significant
bit-pair occurs on the same "states" which produce count direction changes.
%
FOR i IN 1 to last GENERATE
case cnt[i][] is
when 0 =>
if up[i] or (i == last) then
-- if up[i] then
temp[i][] = 1;
else
temp[i][] = 0;
end if;
when 1 =>
if up[i] then
temp[i][] = 3;
else
temp[i][] = 0;
end if;
when 2 =>
if up[i] and (i != last) then
-- if up[i] then
temp[i][] = 2;
else
temp[i][] = 3;
end if;
when 3 =>
if up[i] then
temp[i][] = 2;
else
temp[i][] = 1;
end if;
end case;
if cry[i-1] then -- if carry in, then update count and maybe assert carry out
cnt[i][].d = temp[i][] and !reset;
up[i].s = (cnt[i][]==0) or reset; -- change direction to up
up[i].r = (cnt[i][]==2) and !reset; -- change direction to down
cry[i] = !cnt[i][0] and (cnt[i][1]==up[i]) and !reset; -- carry out from this bit-pair
else
cnt[i][].d = cnt[i][] and !reset; -- no carry in, so no count
up[i].s = reset;
up[i].r = gnd;
cry[i] = gnd;
end if;
out[(i*2-1)..(i*2-2)] = cnt[i][]; -- map bit-pairs of counter to function outputs
END GENERATE;
end;
Article: 28509Hi Peter, Can you please let me know if there's an option to allow the multipliers to be clocked? The picture in the datasheet makes it look like the multiplier is a purely combinatorial function of the inputs. The timing information supports this. I am concerned that the relatively slow clock to output delay of the block rams coupled with the multiplier delay will limit the clock speed to about 100MHz in filter applications. Thanks, Allan. Peter Alfke wrote: > > Ray, this may be the rare case where your long ( and distinguished ! > ) experience misleads you. > In the 13 years I have been at Xilinx, I have never seen us as well > prepared for the introduction of a new family, as we are today with > Virtex-II. > We have had software since last October, silicon since late > November, and have been testing it furiously ever since. We finished > writing a 536-page Virtex-II Handbook in December, and shipped many > thousands of printed copies in early January. We have had extensive > training for our FAEs last fall, and we are putting together the > slides for a public seminar right now. > Highest on my list of exciting features is the Digitally Controlled > Impedance, which effectively puts the series termination resistor > right into the output driver, or the parallel termination right into > the input buffer ( all optionally of course). It will be a gods-end > for people putting >500-pin packages on a pc-board, not having to > bother with resistor packs... > Hundreds of 18 x 18 multipliers (<4ns) are nice, as are 16 global > clocks in all devices, each with an input mux that can glitch-free > select between two sources. Ripple carry delay is 45 ps per bit, a > 24-bit synchronous counter runs at 300 MHz, etc. > Exciting stuff. As I mentioned,earlier, I am working on a 1 GHz > frequency counter, on a 200 MHz asynchronous FIFO, and on > metastability testing. > > Sorry for the blatant propaganda. Got carried away by my enthusiasm. > > I had been impatiently waiting for the Ides of January, for a long > time ! > > Peter Alfke, Xilinx Applications > ===================================== > Ray Andraka wrote: > > > erika_uk@my-deja.com wrote: > > > > > > Hi, > > > > > > Does the tool handle it well ? > > > > Like any other new architecture, I suspect it will take a while > > for the tools to catch up to the new silicon. In the past, > > it has taken about a year after the introduction of the > > silicon before the tools were close to ready for prime time. > > Macro libraries lag even further behind. In the case of Virtex, > > I didn't start recommending them for customers until a little > > over a year ago...because of tools issues. > > > > > > > > --Erika > > > In article <979567585.218715@news2.cybercity.dk>, > > > "Rune Baeverrud" <fpga@no.spam.iname.com> wrote: > > > > Hello, > > > > > > > > Xilinx Virtex-II has now been officially announced. > > > > > > > > Check out the press release: > > > > http://www.xilinx.com/prs_rls/vtx2ship.htm > > > > > > > > and the Virtex-II Handbook: > > > > http://www.xilinx.com/products/virtex/handbook/index.htm > > > > > > > > Some highlights are: > > > > - digitally controlled impedances for input and output pins > > > > - new resources for clock management and clock synthesis > > > > - digital spread spectrum clocking > > > > - encrypted bitstreams > > > > - dedicated multipliers > > > > > > > > Go and see for yourself! > > > > > > > > Regards, > > > > Rune Baeverrud > > > > > > > > > > > > > > Sent via Deja.com > > > http://www.deja.com/ > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.comArticle: 28510
One pair of reference resistors serves a whole bank, i.e. half a device edge, i.e. between 20 and 150 pins, depending on the package. The analog control circuit inside the chip pulls the resistors to a common point. Which means, these two resistors in series effectively span Vcc to ground. So 50 + 50 Ohm = 100 Ohm, equals 25 mA @2.5 V = 63 mW per bank or half-edge. Peter Alfke Jim Granville wrote: > > Just getting my head around this feature. > > The notes show a block of 8, sharing a pair of RefUP and RefDown > bias resistors. > So, what is the Static ( DC ) power component when > using this feature ? > > - jgArticle: 28511
Jim, The power dissipated in the reference resitors is less than Vcco/2 squared, divided by the resistance value, times 2. It is sampled in time, and is not ON continuously. This less than 100 mW peak for each bank. I will make the actual meaasurements soon, but I think the time ratio is ~1/4, so all told it is closer to 25 mW per bank. Then power is only dissipated in each IOB based on what the equivalent resistors would have done anyway outside the package. It is real power, so it is taken into account in the SSO table (DCI numbers are smaller than non-DCI not due to SSO, but due to added power and current in the supply wires), and also accounted for in the power calculator spreadsheet. Some IO standards are real power hogs (for example SSTL3_II. both transmitting and receiving) so they number of these may be limited due to the power dissipation. Yet, there would be 5 of these SSTL3_II per power ground pin pair in a BF957 package, with 10 power ground pin pairs in a bank, so that would allow for 50*8, or 400 of these power hungry IO's using DCI. Now, you still have to consider the dissipation of all that heat, and the power estimator will hand that to you. All told, the box still gets just as hot as before (plus ~8*25 mW for the reference resistors), but the resistors are gone. Enjoy, Austin Jim Granville wrote: > Peter Alfke wrote: > > > <snip> > > Highest on my list of exciting features is the Digitally Controlled > > Impedance, which effectively puts the series termination resistor > > right into the output driver, or the parallel termination right into > > the input buffer ( all optionally of course). It will be a gods-end > > for people putting >500-pin packages on a pc-board, not having to > > bother with resistor packs... > > Just getting my head around this feature. > > The notes show a block of 8, sharing a pair of RefUP and RefDown > bias resistors. > So, what is the Static ( DC ) power component when > using this feature ? > > - jgArticle: 28512
On Mon, 15 Jan 2001 10:14:39 -0800, Peter Alfke <peter.alfke@xilinx.com> wrote: >Highest on my list of exciting features is the Digitally Controlled >Impedance, which effectively puts the series termination resistor >right into the output driver, or the parallel termination right into >the input buffer ( all optionally of course). It will be a gods-end >for people putting >500-pin packages on a pc-board, not having to >bother with resistor packs... This will be extremely useful. One question, Peter: some ASIC vendors have been offering this feature for a while, but some implementations are problematic. Is the Virtex II impedance update mechanism asynchronous to the user's clock? If so, is there a guarantee that the impedance can't glitch (say, the way a D/A might) at a critical moment? Thanks, Bob PerlmanArticle: 28513
Theoretically correct, but in reality it depends on the complexity of the Grey-control logic. In the design I am touting, there is actually a binary counter enclosed. Bye-bye power saving. Peter Alfke Theron Hicks wrote: > Also, the switching noise may be substantially less as only one bit is changing > at a time. >Article: 28514
Hello: is the cpu(x86 or PowerPc or 8051) ASIC?,how is it be manufactured? Does it use the (vhdl/verilog) ? thanksArticle: 28515
[Re: ClearCase] In comp.lang.vhdl Jan Vermaete <maetej@nospam.rsd.bel.alcatel.be> wrote: > That's possible but CVS is for free (http://www.cvshome.org) Sure, but ClearCase is much better. For one thing, because it has a custom virtual file system on the client (MVFS -- multi version file system) it can do a lot of things which CVS can't do. It's integrated quite well into NT, as well as Unix. I guess it's expensive. We started using it for FPGA designs within the last year. We already had it because our software engineers have been using it for several years. I doubt we would have bought it especially for FPGA work. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 28516
Hi I agree with Eric, you should first read some background stuff before writing the article! On the other hand, here are some clues for you questions: * logical design/verification only takes the logical equations, symbols into account like "and" or "or" but also "adders" or "muxes" . It doesn't include timing (and related problems), process spread, process parameters. It is (nearly) process independent. RTL-design is a commom example. * Physical design/verification tries to simulate/build an as accurate model as possible of the design. It is much slower and process dependant. It is mostly generated out of an logical design. Gate-level design is a common example. * Probably you'll find much better and compleet describtions in VHDL-study-books. Did you look on the internet too unther "vhdl-course"? Kind regards ---------------------------------------------------------------- Johan Van Dyck Johan.Van.Dyck@philips.com VLSI Design Engineer Philips Leuven (Belgium) Johan.Van.Dyck@philips.com ---------------------------------------------------------------- <strshn99@my-deja.com> wrote in message news:93sumd$qp0$1@nnrp1.deja.com... > Dear Gurus, > > I am trying to write up a little article for our college little > newspaper but I am sort of a newbie at VHDL and FPGA. So I would like > you gurus to explain to me: > 1) what these terms means. > 2) what are the tools used to do these kind of things. > > The terms are: > > a) Logical Design > b) Physical Design > c) Logical Verification > d) Physical Verification > > thanks very much > > > Sent via Deja.com > http://www.deja.com/ >Article: 28517
hello, what's negative borrow ? (it's not for a homework, we are on holidays ;-)) Sent via Deja.com http://www.deja.com/Article: 28518
Hello: i want to know what tools(including design input/synthesis/simulation/P&R/Verifying .etc) are used in designing ASIC/FPGA. can you introuduce for me ? thanksArticle: 28519
I use the Virtex-based Celoxica RC1000-PP board for applications work. It pretty much meets your specification; PCI communication, 4xRAM modules, simple interfacing software. http://technology.celoxica.com/boards/boards_001.asp Henry Styles, Imperial College, LondonArticle: 28520
Hi all I am trying to implement a design but ngdbuild finds an error in the ucf, although it's generated with the constraints editor. Error message: ERROR:NgdHelpers:33 - Invalid UCF/NCF file entry value "" detected on line 45, offset 246, while reading UCF file "bonito.ucf". The line that causes the problem: TIMEGRP "Protocol" = FFS( "copier_cout(41)" "copier_cout(42)" "copier_cout(43)" "cpu_out(41)" "cpu_out(42)" "cpu_out(43)" "dram_out(41)" "dram_out(42)" "iosys_cout(41)" "iosys_cout(42)" "pcicache_out(41)" "pcicache_out(42)" "pcicache_out(43)" ); If I remove the "", I get another error message: ERROR:NgdHelpers:676 - Processing TIMEGRP definition "Protocol= FFS(copier_cout(41) copier_cout(42) copier_cout(43) cpu_out(41) cpu_out(42) cpu_out(43) dram_out(41) dram_out(42) iosys_cout(41) iosys_cout(42) pcicache_out(41) pcicache_out(42) pcicache_out(43)) " from UCF file: Encountered bad token "eof" while parsing group name "FFS(copier_cout(41)". I am using Foundation 2.1i (the synthesis was done with Leonardo Spectrum) If anyone has a clue... -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 28521
Andy Peters writes: >> Andy Peters writes: >> > ModelSim and Synplify both use dongles (which I vastly prefer over >> > that FlexLM bogosity) but the Mac ain't got a parallel port so I'm SOL >> > there. >> >> And even if the MAC did have a parallel port... >> >> I vastly prefer FlexLM because there is some hope of it working in an >> emulator. In my experience dongle reading code does seriously weird >> things to your parallel port, and doesn't work in an emulator. > Yeah, but if FlexLM is keyed to your ethernet MAC (not Macintosh!) > address and you want to, say, do some work at home, you're hosed. OTOH if you run it in an emulator, you get to choose the reported MAC addess :-) > Here's my thought on all this: choose the software, and buy whatever OS > and machine it runs on, rather than buying (or downloading) an OS and > installing it on a particular machine and using hacks and such in an > effort to get the software to work on it. That's all very well if you're only using one package. > Yes, I'd like ModelSim PE and the Xilinx tools and Synplify to all run > on Linux. But my job is to design FPGAs, and if that requires running > NT, so be it. Yes, I will tell the vendors that I prefer Linux. Yes, I > will demand that the Linux versions of the tools cost the same as the NT > versions. No, I will not frustrate myself trying to get software > written for one OS to run on another. My job is to design FPGAs too, and talk to them. This requires that I run: Linux, NT, Solaris. Unfortunately the Solaris box isn't as fast as the Linux box, and the NT box is far slower. Getting access to a 3rd computer to run NT was a pain and took several months. "You've already got two computers". (The computer cost more than the software that runs on it after all). -- JamieArticle: 28522
strshn99 writes: > I have a newbie question to ask you. What kind of Revision control > tools do you use when you are working on a design? Any recommendation > as to which is better? We use CVS over ssh for our source files (VHDL, Handel-C, Perl, C), makefiles etc. and no version control for the generated files. -- JamieArticle: 28523
NokioGL writes: > just came by to inform you about this site. It's a very good and > advanced site related to the seminconductor industry, maybe it might > be interesting for you to check it out.. :) > http://www.datasheetlocator.com/nl I looked up Altera and it said (to paraphrase) "click on this button to go to Altera's datasheet page". I clicked, nothing happened. Shame, I was hoping for a fully indexed search engine. -- JamieArticle: 28524
Nicolas Matringe wrote: > Hi all > I am trying to implement a design but ngdbuild finds an error in the > ucf, although it's generated with the constraints editor. > > Error message: > ERROR:NgdHelpers:33 - Invalid UCF/NCF file entry value "" detected on > line 45, offset 246, while reading UCF file "bonito.ucf". > > The line that causes the problem: > TIMEGRP "Protocol" = FFS( "copier_cout(41)" "copier_cout(42)" > "copier_cout(43)" "cpu_out(41)" "cpu_out(42)" "cpu_out(43)" > "dram_out(41)" "dram_out(42)" "iosys_cout(41)" "iosys_cout(42)" > "pcicache_out(41)" "pcicache_out(42)" "pcicache_out(43)" ); > > If I remove the "", I get another error message: > ERROR:NgdHelpers:676 - Processing TIMEGRP definition "Protocol= > FFS(copier_cout(41) copier_cout(42) copier_cout(43) cpu_out(41) > cpu_out(42) cpu_out(43) dram_out(41) dram_out(42) iosys_cout(41) > iosys_cout(42) pcicache_out(41) pcicache_out(42) pcicache_out(43)) " > from UCF file: Encountered bad token "eof" while parsing group name > "FFS(copier_cout(41)". > > I am using Foundation 2.1i (the synthesis was done with Leonardo > Spectrum) > > If anyone has a clue... > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 10-12 Avenue de Verdun > Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE > Fax +33 1 46 52 53 01 http://www.IPricot.com/ Are the lines separated by newline characters? Maybe Ngdbuild UCF parser might not handle newline characters. Can it be the case? Utku
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