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Hi Marcel, Which Dual port BlockRAM component did you instantiate in VHDL code? If you don't use the correct component name, the synthesis tool may not find it in the library. Different configurations of Dual port BlockRAM components are described at http://toolbox.xilinx.com/docsan/3_1i/data/common/lib/chap09/lib09036.htm You can also check the Unisim library for all valid VHDL component declarations. The synthesis tools also error out if there is a port mismatch or if port mapping is not done properly. -Vikram Xilinx Applications Marcel Melters wrote: > Hi, > I'm currently working on a VHDL design running in a Virtex-50E chip. > I need a Dual-ported RAM in this design, but I'm having trouble > instantiating a Block-RAM for this. > I'm using Exemplar Leonardo. I am aware that there is an application > note explaining how to instantiate a SINGLE-port RAM as Block-RAM, > but when I try and modify this to a dual-port setup, the synthesizer > simply > refuses to use the block-ram. > I guess I'm missing something here, but can anyone shed some light on > this ? > Any help is much appreciated. > > =============================================================== > Ing. Marcel Melters Philips Medical Systems > Hardware engineer Veenpluis 6 > MR-backend room QR-2352 5684 PC Best > mailto: marcel.melters@philips.com P.O. box 10000 > phone +31 40 27 63266 5680 DA Best > fax +31 40 27 63771 The Netherlands > =============================================================== > ... deadlines? I like deadlines ... > I like the "whoosh" sound they make when they rush past ... > Douglas Adams, author of T.H.H.G.T.T.G.Article: 27876
Hi I was thinking about setup violation in real world (not simulation). If the setup time is not respected, the simulation result will be an 'X' on the output of the FF, but in the real world, will it be "either 0 or 1, can't say", or can it be an intermediate, metastable value? As long as it's 0 or 1, I don't mind -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 00 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 27877
Hi Marcel, Sounds like you are trying to infer a dual port block ram rather than using an instantiated component. Can Examplar Leonardo infer DPBrams i.e. are they supported..... If so does Exemplar require that your HDL description of the ram follow a specific template in order to infer this component. Alternativly: If DPBrams are not supported ... you can instantiate the actual component(s) directly from the unsims library as suggested by Vikram... Use coregen to generate the DPBRAM you need and instantiate that in your code Hope this helps Colm. Marcel Melters wrote: > Hi, > I'm currently working on a VHDL design running in a Virtex-50E chip. > I need a Dual-ported RAM in this design, but I'm having trouble > instantiating a Block-RAM for this. > I'm using Exemplar Leonardo. I am aware that there is an application > note explaining how to instantiate a SINGLE-port RAM as Block-RAM, > but when I try and modify this to a dual-port setup, the synthesizer > simply > refuses to use the block-ram. > I guess I'm missing something here, but can anyone shed some light on > this ? > Any help is much appreciated. > > =============================================================== > Ing. Marcel Melters Philips Medical Systems > Hardware engineer Veenpluis 6 > MR-backend room QR-2352 5684 PC Best > mailto: marcel.melters@philips.com P.O. box 10000 > phone +31 40 27 63266 5680 DA Best > fax +31 40 27 63771 The Netherlands > =============================================================== > ... deadlines? I like deadlines ... > I like the "whoosh" sound they make when they rush past ... > Douglas Adams, author of T.H.H.G.T.T.G.Article: 27878
Hi, I want to program Altera and Xilinx FPGAs with JTAG Technologies PLDPROG Tools. According JTAG Technologies there should be no problems. Nevertheless I have terrible experience with this. I now want to ask you, if you can confirm my experience or if you have had more luck. I should describe this in my diploma thesis. So I would welcome your comments. The following can be seen as an experience report. Best regards, Franz ============================================== Altera MAX EPM7256S -------------------------- *) JAM Altera generates JAM/STAPL 2.0. JTAG Technologies only supports JAM 1.0 and 1.1. For the Altera MAX family this is ok. MAX+PLUS II can generate SVF too. Thus we donīt depend on JAM. But the Altera Quartus software for the Altera APEX 20K only supports JAM. This could lead to a problem in future. *) SVF I had to insert //!ACTION statements and to correct a revision number in the SVF file manually. I have no idea how to catch the revision number problem without help of the manufacturer. Xilinx XC4028XL ------------------- *) SVF The SVF support for the Xilinx 40xx is broken. JTAG Tech. claims that these devices are not fully JTAG complaint which make the SVF useless. *) RBT RBT should work. Couldnīt check it due a missing license key. But they have an error in their ddf31.jcs file. The prom size was wrong. According to JTAG Tech. this mistake was made due to an incorrect Xilinx datasheet. As conclusion it can be said that nothing worked as originally promised. Do you have the same experience? -- Institut fuer Hochenergiephysik Nikolsdorfer Gasse 18 1050 Wien Austria Tel: (+43-1)5447328/50Article: 27879
Hi Colm,
you are absolutely correct, I'm trying to INFER dual port block RAM.
This should result in a more "portable" code, which does not depend on
the target device (Virtex 50E at the moment).
There is a mention in the LeonardoSpectrum Synthesis and Technology
Manual, v2000.1, of a VHDL example of a Block RAM.
Unfortunately, this example only deals with a Single-port RAM.
Every modification I tried to convert this to a dual-port RAM failed so far.
If all else fails, I will have to instantiate, using coregen, as you
suggested.
Thank you for your suggestions,
Marcel.
Colm Clancy wrote:
> Hi Marcel,
>
> Sounds like you are trying to infer a dual port block ram rather than
> using an instantiated component.
>
> Can Examplar Leonardo infer DPBrams i.e. are they supported..... If so
> does Exemplar require that your HDL description of the ram follow a
> specific template in order to infer this component.
>
> Alternativly: If DPBrams are not supported ...
>
> you can instantiate the actual component(s) directly from the unsims
> library as suggested by Vikram...
> Use coregen to generate the DPBRAM you need and instantiate that in your
> code
>
> Hope this helps
>
> Colm.
> =============================================================
Ing. Marcel Melters Philips Medical Systems
Hardware engineer Veenpluis 6
MR-backend room QR-2155 5684 PC Best
mailto: marcel.melters@philips.com P.O. box 10000
phone +31 40 27 63266 5680 DA Best
fax +31 40 27 63771 The Netherlands
===============================================================
... deadlines? I like deadlines ...
I like the "whoosh" sound they make when they rush past ...
Douglas Adams, author of T.H.H.G.T.T.G.
Article: 27880
Hi Franz,
Franz Hollerer wrote:
> I want to program Altera and Xilinx FPGAs with JTAG Technologies
> PLDPROG Tools. According JTAG Technologies there should be
> no problems. Nevertheless I have terrible experience with this.
I have programmed a few Xilinx CPLDs & PROMs and also Lattice ispGAL devices
using PLDprog, no FPGAs unfortunately (although I tried with a Virtex
device, but its DONE bit in a certain status register didn't go up).
In general, I use the SVF support for Xilinx CPLDs, even if I am trying to
program a CPLD, a FPGA or even a PROM. JTAG Tech's SVF support does not
really recognize whether it is programming a CPLD or something else, it just
"executes" the SVF, regardless of the data. To program an unsupported device
(for example, a PROM), use a "UNDEFINED" device type in your .PRG file.
Thus, for your XC4K devices, you could use JTAGprogrammer (from Xilinx) to
generate the SVF file, just like I use it to generate SVF files for the
XC18V00 PROM. Then modify the SVF file (if needed) and use it with PLDprog.
Also, I tend to play with the TCK frequency to improve programming results.
Since SVF timings are generally given assuming a 1MHz TCK, I tend to set
this specific frequency as the TCK value. This way, I can usually program
devices without the need to add //! WAIT xxx USEC; statements.
I have noted that the SVF files produced by Xilinx's JTAGprogrammer are
sometimes containing information that prevents the programming from
completing. For example, I often get better results by changing:
// Loading device 'PROM(Device1)' with 'bypass' instruction.
SIR 8 TDI (ff) SMASK (ff) TDO (01) MASK (e3) ;
into:
// Loading device 'PROM(Device1)' with 'bypass' instruction.
SIR 8 TDI (ff) SMASK (ff) ;
and I remove the IDCODE instruction below:
// Loading device 'PROM(Device1)' with 'idcode' instruction.
SIR 8 TDI (fe) SMASK (ff) ;
SDR 32 TDI (ffffffff) SMASK (ffffffff) TDO (05003093) MASK (fffdffff) ;
which usually appears at the beginning of the SVF file. Why it works, I
don't know.
Hope these tricks will help,
Étienne.
--
______ ______
*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
* / /_/_ / / /\ \ \ CAE Electronics Ltd. *
*/_____//_/_/**\_\_\*************************************************
Article: 27881eml@riverside-machines.com.NOSPAM wrote: > > On Tue, 12 Dec 2000 14:37:30 +0000, Nial Stewart <nials@sqf.hp.com> > wrote: > > >Michael Boehnel wrote: > >> > >> I use Synplify PRO 6.1 in conjunction with Foundation 3.1i. When I > >> synthesize Synplicity's VHDL Tutorial on the Virtex50 with the described > >> timing constraints I get the expected maximum frequency of 85MHz. When I > >> place and route the design with Xilinx design manager I only get > >> 68.2MHz. Where comes this difference from? Are the estimations of > >> Synplify that bad? I can't believe it. > > ^^^^^^^^^^^^^^^^^^ > > > >Why not? In the latest big FPGAs the delays are dominated by > >routing delays, not logic delays, so the synthesis tool > >has no direct information about the biggest factor affecting > >the speed of a design. > > > >The synthesis tools have to work with rules of thumb that have > >been empirically derived, so 20% out isn't too bad. > > > >Nial. > > I had this argument with a Sprectrum rep last year. I asked why the > timing estimates could be up to 50% out, and he got annoyed. He > started on about how clever their statistical load models were, and > said the results were 'accurate'. I couldn't be bothered to provide > any test cases to demonstrate the obvious, and that was the end of the > conversation. In a presentation a couple of months ago the Examplar rep admitted that their timing estimates are no better than cleverly derived rules of thumb and couldn't really be relied on for any sort of final design speed estimation. Of course they'll be much better in the next revision of the tools! Maybe the difference between an American salesman and a British one? Nial.Article: 27882
If you violate the set-up time requirement, the flip-flop will usually work fine and respond in time with either a 1 or a 0, and you obviously don't care which one. Sometimes, when your D input changes right within the fractional-picosecond window where the master latch stops looking at the D input, the flip-flop goes metastable. That does not mean that the output goes to a half-voltage. It means that the flip-flop has a hard time deciding what to do, and will take a while to make up its mind. That means an output change that is later than the specified clock-to-Q delay. For the probability of such a delay, see teh Xilinx App Note XAPP094. It is "only" this timing uncertainty that is the curse of metastability. The 1-or-0 uncertainty is obviously acceptable. The Florida election fiasco is a perfect example of metastability. Just because the result was so very close, the "mechanism" (or lack thereof) caused a >4 week delay before deciding on one of the two choices. But let's not get into politics... Peter Alfke, Xilinx Applications ============================================ Nicolas Matringe wrote: > Hi > I was thinking about setup violation in real world (not simulation). > If the setup time is not respected, the simulation result will be an 'X' > on the output of the FF, but in the real world, will it be "either 0 or > 1, can't say", or can it be an intermediate, metastable value? > As long as it's 0 or 1, I don't mind > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 10-12 Avenue de Verdun > Tel +33 1 46 52 53 00 F-92250 LA GARENNE-COLOMBES - FRANCE > Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 27883
Peter Alfke wrote: > > If you violate the set-up time requirement, the flip-flop will > usually work fine and respond in time with either a 1 or a 0, > and you obviously don't care which one. Right. > Sometimes, when your D input changes right within the > fractional-picosecond window where the master latch stops > looking at the D input, the flip-flop goes metastable. It means > that the flip-flop has a hard time deciding what to do, and will > take a while to make up its mind. That means an output change > that is later than the specified clock-to-Q delay. > The Florida election fiasco is a perfect example of > metastability. Just because the result was so very close, the > "mechanism" (or lack thereof) caused a >4 week delay before > deciding on one of the two choices. I hope my FFs make up their "minds" faster, I only have 30 ns... Thanks a lot -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 00 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 27884
Can anyone give me the "best" way to implement a _fast_ counter in a SpartanXL design? I need a 16 bit counter with enable and reset.clock on negative edge preferred but not critical. I don't need the output to be synchronous because I am counting to measure pulse width so I can wait for the final result to ripple through to the output. The _only_ factor of importance is _speed_. Should I use logiBLOX or should I write my owm or should I forcibly implement it using some unknown (to me) tool? I need to get up to 204.8MHz toggle frequency. The output in counts will be latched after the pulse is completed and the resulting count values will be passed through a tri-state output of some sort. Thanks, Theron J. HicksArticle: 27885
On Tue, 28 Nov 2000 22:51:32 -0500, rickman <spamgoeshere4@yahoo.com> wrote: >will produce an equivalent circuit in the FPGA. Some people think that >adding the reset to every FF in your code will create a long signal that >snakes through the design. But this signal is replaced by the GSR net in >the FPGA. The GSR net is what puts all the FFs in a defined state when It depends on what you allow your synthesizer to do. Per the recommendations in Xilinx Answer #6713 at http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=6713 I allowed Leonardo to not use the GSR for my explicit reset net (I believe it was the default for Spartan2/Virtex). When I targeted the same design to a 4028, I let it use the GSR. Basically, they're claiming that using the GSR on a Virtex results in slower reset than letting it use a high-fan out net. DanArticle: 27886
Tesisti DSPLab wrote: > > Hallo, > > we are implementing single-process applications > and we find the following error: > > The net "clr" has more than one driver (FPGA-CHECK-5) > > Xilinx Help has not this entry in its database: is that > possible? Yup. There's a lot of things that aren't in the database. > The portion of the VHDL file that gives this problem follows: It's not in the code you posted. The error message is quite explicit: there's more than one driver for the net "clr" so you must look through your code to find out what's actually driving clr. It might help to simulate your code first. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27887
Ramanathan wrote: > > Hi, > > what is meant by a Test Bench? A test bench is HDL code that is meant to exercise and verify your design. See Janick Bergeron's book, "Writing Testbenches -- Functional Verification of HDL Models" for some excellent information. Well worth the $98 Fatbrain.com charged for it. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27888
V Ram wrote:
>
> Hello.
>
> I am using FPGA Express 3.0 to synthesize some VHDL. I have segmented my
> design into multiple blocks (entity&arch pair) each of which resides in a
> separate VHDL file.
>
> If I used ModelSIM to simulate, I can make a "top-level" file and
> instantiate "components" which are really the modules I designed. I use a
> package to describe the modules and a custom library to hold the modules
> and then in the top-level I use the library/components and tie it all
> together with signals.
>
> However, I cannot get FPGA Express to understand this, even if I create a
> components library that matches my name and compile the smaller parts into
> this library. Any suggestions? Any easier way to do a top-level file where
> I simply connect blocks together? (Graphically)?
I'll bet a six-pack of Bass Ale that you're not putting component
declarations in your code. For instance, in your top level, say you
have lower-level modules foo and bar. VHDL lets you do the following
direct instantiation:
architecture toplevel of mychip is
begin
u1 : entity work.foo
port map (...);
u2 : entity work.bar
port map (...);
However, FPGA Express is brain-dead and requires you to declare the
components before you instantiate them:
architecture toplevel_fpgaexpress of mychip is
component foo is
port (...);
end component foo;
component bar is
port (...);
end component bar;
begin
u1 : foo
port map (...);
u2 : bar
port map (...);
hope this helps.
-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u
"It is better to be silent and thought a fool,
than to send an e-mail to the entire company
and remove all doubt."
Article: 27889Saqib wrote: > > Hi! > Any body knows some good sites providing basic information regarding > the adaptive filter theory..? Buy two books instead: "Adaptive Signal Processing" by Widrow and Stearns. (Fatbrain: http://www1.fatbrain.com/asp/bookinfo/bookinfo.asp?theisbn=0130040290&vm=) "Adaptive Filter Theory" by Haykin (Fatbrain: http://www1.fatbrain.com/asp/bookinfo/bookinfo.asp?theisbn=013322760X&vm=) -- ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27890
Eric Smith wrote: > > kolja@prowokulta.org writes: > > I am wondering if it really is a good managment decision to sell > > 100K Parts to one customer instead fo selling 100 Parts each to 1K > > customers. > > Xilinx will loose big customers to gate array manufactures and small > > customers to Altera. > > There's a lot less overhead to selling 100K parts to a single customer. > Taking a short term view (which is all most businesses do any more), > a single big customer is clearly better than a lot of small ones. There's a parable somewhere about putting all of one's eggs into a single basket. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27891
Dear all, I have two external clocks connected to the Altera FPGA (20K200E). One clock is running at 50 MHz and the other one is running at 25 MHz. The 25 MHz clock is generated from the 50 MHz clock using an external frequency divider chip. The problem is that the two clocks have a certain skew in the range of -1.5/+0.5 ns. How can I specify this situation in the Altera Quartus tool ? I want that paths going from CLK25 domain to CLK25 domain are constrained to 40 ns, paths going from CLK50 to CLK50 are constained to 20 ns, paths going from CLK25 to CLK50 are constrained to 18.5 ns, paths going from CLK50 to CLK25 are constrained to 19.5 ns. Thanks in advance for your helpful advice ! Regards, Martin Heimlicher, Supercomputing Systems AG, SwitzerlandArticle: 27892
Dear all, I have the following situation with a Altera 20K200E FPGA: One external data bus is running at 25 MHz. Internally, I am using a frequency doubled clock at 50 MHz to sample these signals. How do I specify in the Altera Quartus tool that it can allow two cycles time for all paths starting at these external data bus pins and going to all internal registers ? I find that multicycle timing constraints can only be applied to individual register instances and not to the complete design. This is disasterous since the instance names change from one synthesis run to the next. Is there a better way ? Thanks a lot in advance, Martin Heimlicher, Supercomputing Systems AG, SwitzerlandArticle: 27893
Dear all, This is a very basic and general FPGA question: How do I assure that an externally supplied reset signal connected to some sort of GSR (global set/reset) net releases all registers simultaneously (in the same clock cycle) and reliably (no metastability) ? Do I need to synchronize the external reset signal through one or two registers before feeding it to the GSR net ? If yes, what do I do in the case of multiple clocks in a design ? Can I use the GSR net only to reset registers clocked by one clock and using other routing ressources to reset registers clocked by the other clocks ? If I am worrying to much about this issue: How do FPGAs circumvent these problems ? Regards, Martin Heimlicher, Supercomputing Systems AG, SwitzerlandArticle: 27894
Andy Peters wrote: > Eric Smith wrote: > > > > kolja@prowokulta.org writes: > > > I am wondering if it really is a good managment decision to sell > > > 100K Parts to one customer instead fo selling 100 Parts each to 1K > > > customers. > > > Xilinx will loose big customers to gate array manufactures and small > > > customers to Altera. > > > > There's a lot less overhead to selling 100K parts to a single customer. > > Taking a short term view (which is all most businesses do any more), > > a single big customer is clearly better than a lot of small ones. > > There's a parable somewhere about putting all of one's eggs into a > single basket. > Every now and again I go unicorn hunting & check out the lead times among the distis on Spartan2. Current score min/max = 22weeks/allocation (*) so I'm sticking for the moment with the lightning quick 6-8 week delivery times of the smaller VirtexE devices. (*) It is an outstanding conjecture that ``allocation'' is mathematically equivalent to the result of 1/0. As it stands this is probably not true but after allowing for the event horizon surrounding large corporations and the influence of nearby orbiting accountants it probably is.Article: 27895
On Wed, 13 Dec 2000 22:13:37 +0100, "Martin Heimlicher" <heimlicher@scs.ch> wrote: >This is a very basic and general FPGA question: I don't think this is a basic question... and I am pretty sure that you will get better answear that I can provide. >How do I assure that an externally supplied reset signal connected to some >sort of GSR (global set/reset) net releases all registers simultaneously (in >the same clock cycle) and reliably (no metastability) ? If you are using a XC4000 (or any other FPGA as far as I know) you have to know that the GSR net have a maximum but not a minimum delay. This means that you will have a skew on the reset signal and that you can not trust that the GSR signal is released within the setup/hold time of any flipflop. This can be fixed by adding a synchronous reset to FFs that nees a reset (like FSM FFs). >Do I need to synchronize the external reset signal through one or two >registers before feeding it to the GSR net ? I don't think that this is you problem. Not all registers need to be reset. Forget the data path, just reset the (control registers) FSM that controls the data path. Make sure that the reset signal is released synchronusly with th release of the GSr net. >If yes, what do I do in the case of multiple clocks in a design ? Can I use >the GSR net only to reset registers clocked by one clock and using other >routing ressources to reset registers clocked by the other clocks ? > >If I am worrying to much about this issue: How do FPGAs circumvent these >problems ? > >Regards, > Martin Heimlicher, Supercomputing Systems AG, Switzerland >Article: 27896
--------------675CEB63CE113539AC28CA37 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Theron, you can easily achieve twice that speed. I did that 2 years ago when designing a 400-MHz frequency counter, as described in XCell http://www.xilinx.com/xcell/xl32/xl32_47.pdf That counter had to be decimal, which makes things a bit more complicated. In your case, just stay away from global clocks. Route the input clock signal to the clock input of a single CLB flip-flop ( best placed on the left edge of the device.) Make it toggle, using a tight feedback loop (<2ns) Then use this Q as a clock for the next CLB, configured as a 2-bit counter, since the two flip-flops have a common clock. Use the highest Q as clock for the nect CLB, etc. That gives you a ripple counter with the best possible input resolution ( yes, and an awful ripple delay.) 400 MHz should be no problem. Use a small housekeeping state machine to enable/disable the counter through the asynchronous ( or synchronous) clear of the front-end flip-flop, and some time later clear all bits prior to the next count cycle. Itmay be heresy to a computer designer, but it works beautifully. Peter Alfke, Xilinx Applications ======================================= Theron Hicks wrote: > Can anyone give me the "best" way to implement a _fast_ counter in a > SpartanXL design? I need a 16 bit counter with enable and reset.clock > on negative edge preferred but not critical. I don't need the output to > be synchronous because I am counting to measure pulse width so I can > wait for the final result to ripple through to the output. The _only_ > factor of importance is _speed_. Should I use logiBLOX or should I > write my owm or should I forcibly implement it using some unknown (to > me) tool? I need to get up to 204.8MHz toggle frequency. The output in > counts will be latched after the pulse is completed and the resulting > count values will be passed through a tri-state output of some sort. > > Thanks, > Theron J. Hicks --------------675CEB63CE113539AC28CA37 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Theron, <br>you can easily achieve twice that speed. I did that 2 years ago when designing a 400-MHz frequency counter, as described in XCell <br><u><A HREF="http://www.xilinx.com/xcell/xl32/xl32_47.pdf">http://www.xilinx.com/xcell/xl32/xl32_47.pdf</A></u> <p>That counter had to be decimal, which makes things a bit more complicated. <p>In your case, just stay away from global clocks. Route the input clock signal to the clock input of a single CLB flip-flop ( best placed on the left edge of the device.) Make it toggle, using a tight feedback loop (<2ns) <br>Then use this Q as a clock for the next CLB, configured as a 2-bit counter, since the two flip-flops have a common clock. Use the highest Q as clock for the nect CLB, etc. <br>That gives you a ripple counter with the best possible input resolution ( yes, and an awful ripple delay.) <br>400 MHz should be no problem. <br>Use a small housekeeping state machine to enable/disable the counter through the asynchronous ( or synchronous) clear of the front-end flip-flop, and some time later clear all bits prior to the next count cycle. <p>Itmay be heresy to a computer designer, but it works beautifully. <p>Peter Alfke, Xilinx Applications <br>======================================= <br>Theron Hicks wrote: <blockquote TYPE=CITE>Can anyone give me the "best" way to implement a _fast_ counter in a <br>SpartanXL design? I need a 16 bit counter with enable and reset.clock <br>on negative edge preferred but not critical. I don't need the output to <br>be synchronous because I am counting to measure pulse width so I can <br>wait for the final result to ripple through to the output. The _only_ <br>factor of importance is _speed_. Should I use logiBLOX or should I <br>write my owm or should I forcibly implement it using some unknown (to <br>me) tool? I need to get up to 204.8MHz toggle frequency. The output in <br>counts will be latched after the pulse is completed and the resulting <br>count values will be passed through a tri-state output of some sort. <p>Thanks, <br>Theron J. Hicks</blockquote> </html> --------------675CEB63CE113539AC28CA37--Article: 27897
Hi, Marcel. This doesn't exactly answer the question you're asking, but maybe it will help anyways. I've using FPGA Express, which, as everyone knows, doesn't support inferring DPRAMs. but I'm in the same situation where I don't really want to instantiate the BlockRAMs directly, because I don't want change everything if the target device changes. My solution: I have an entity called "DualPortRam", that has generics for DataWidth, AddressWidth, and whatever else I felt I might need. I have an architecture for this entity called "XilinxBlockRam" that instantiates the unisim blockRAM components directly. If I ever need to change target devices, I will have to change my code, of course, maybe doing a "Altera" architecture for the entity. And then, of course, guarantee that the function of the Alter implementation is the same as the xilinx implementation. This has the following advantages: * not having to change upper-level blocks if my target device changes. * Allowing me complete control over how the blockRAMs are implemented. * Lets me use synthesizers that don't support inferring dual-port RAM. * I can also do a "LutRam" architecture that uses the SelectRAM (LUTs) instead of the BlockRAMs. I hope this helps. -Kent Marcel Melters <marcel.melters@philips.com> writes: > Hi Colm, > > you are absolutely correct, I'm trying to INFER dual port block RAM. > This should result in a more "portable" code, which does not depend on > the target device (Virtex 50E at the moment). > There is a mention in the LeonardoSpectrum Synthesis and Technology > Manual, v2000.1, of a VHDL example of a Block RAM. > Unfortunately, this example only deals with a Single-port RAM. > Every modification I tried to convert this to a dual-port RAM failed so far. > > If all else fails, I will have to instantiate, using coregen, as you > suggested. > Thank you for your suggestions, > > Marcel.Article: 27898
eml@riverside-machines.com.NOSPAM wrote: > This probably means that the current generation of FPGA physical > synthesis tools are worthless. The good news is that Virtex-II routing > should be much more predictable, so the situation should get better. Better routing might help, but routing isn't the problem, placement is. If the routing was exactly predictable (say some constant time per distance) if the placement isn't known, the delay can not be known. Giving the tool information as to physical placement improves the estimates of the design performance, more so for large designs than small designs. A "physical synthesis" tool generates both an improved netlist and stable names for area constraints, which allows for improved speed. BTW, is there any other member of "the current generation of FPGA physical synthesis tools" than Amplify? -- Phil HaysArticle: 27899
I had a similar problem a while back when evaluating Leonardo; it
wouldn't infer a DP RAM, but instead implemented it in a bunch of FFs. I
found that this DP RAM design was inferred correctly (sync wr, async
rd):
entity sync_embedded_RAM is
generic
(
data_width: integer;
adrs_width: integer
);
port
(
clock: in std_ulogic;
write_en: in std_ulogic;
wr_adrs: in unsigned(adrs_width-1 downto 0);
data_in: in std_ulogic_vector(data_width-1 downto 0);
rd_adrs: in unsigned(adrs_width-1 downto 0);
data_out: out std_ulogic_vector(data_width-1 downto 0)
);
end sync_embedded_RAM;
architecture synth of sync_embedded_RAM is
type mem_type is array (2**adrs_width downto 0) of
std_ulogic_vector(data_width - 1 downto
0) ;
signal mem: mem_type ;
begin
mem_wr_p: process(clock)
begin
if rising_edge(clock) then
if write_en = '1' then
mem(conv_integer(wr_adrs)) <= data_in;
end if;
end if;
end process;
mem_rd_p: process(mem, rd_adrs)
begin
data_out <= mem(conv_integer(rd_adrs));
end process;
end synth;
Marcel Melters wrote:
>
> Hi,
> I'm currently working on a VHDL design running in a Virtex-50E chip.
> I need a Dual-ported RAM in this design, but I'm having trouble
> instantiating a Block-RAM for this.
> I'm using Exemplar Leonardo. I am aware that there is an application
> note explaining how to instantiate a SINGLE-port RAM as Block-RAM,
> but when I try and modify this to a dual-port setup, the synthesizer
> simply
> refuses to use the block-ram.
> I guess I'm missing something here, but can anyone shed some light on
> this ?
> Any help is much appreciated.
>
> ===============================================================
> Ing. Marcel Melters Philips Medical Systems
> Hardware engineer Veenpluis 6
> MR-backend room QR-2352 5684 PC Best
> mailto: marcel.melters@philips.com P.O. box 10000
> phone +31 40 27 63266 5680 DA Best
> fax +31 40 27 63771 The Netherlands
> ===============================================================
> ... deadlines? I like deadlines ...
> I like the "whoosh" sound they make when they rush past ...
> Douglas Adams, author of T.H.H.G.T.T.G.
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