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hey, <..> If no signal is connected to the BX input, it is pulled high. Then by passing this high through a configurable buffer/invertor, you can get a 0 or 1. <..> how can i control the use of BX?.can i direct the tool to get 0 or 1 from what you said above ? --Erika Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27726
OK - I'll have a look. Thanks for your help. "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3A26ABAA.265F59EF@algor.co.uk... > > > Tim Gordon wrote: > > > I'm using Synopsys FCII for Virtex synthesis. When I instantiate macros > > listed in the Xilinx Unified Libraries, synthesis fails with a link error. > > I've found XNFs for 3000 and 5200 macros amongst the files installed, but > > not for Virtex. Can anyone tell me how to resolve this problem? > > Somehow you need to mark these as ``to be filled in later'' i.e by the Xilinx > back end tools that implement these instantiations as real bits of silicon. > The traditional way is to include a VHDL/Verilog black-box ``stubs'' library > in your synthesis. This consists of a bunch of modules that have only the > ports defined and some sort of ``synthesis stops here'' marker - generally > some variant of the phrase ``black box''. You'll need to look at the FCII > documenation to find out how to do this, not the Xilinx docs. > >Article: 27727
Hi all; I can remember awhile back when one used to estimate that the delay in an FPGA circuit was 50% routing and 50% logic. As the logic speed has improved much more than routing, this ratio has changed. I was wondering what people consider the current rule of thumb to be. On the design I'm currently working on, our worst nets have approximately 70% routing and 30% logic delay. It's a Virtex-E 1000 with about 60% of the slices and 80% of the block RAM used. Does this sound reasonable? Or would it suggest to you that the routing is overly stressed. Speaking of which, how does one get a usage report on the routing? Cheers, JamieArticle: 27728
Hi there, I'm trying hard to get running the FIFOs scfifo and dcfifo from the lpm library. The compiler quit's with the following message (and sometimes some more): ERROR....: Undefined evaluated function "Family_Has_Dualport_EAB" in expression ERROR....: Undefined evaluated function "Family_Is_Known" in expression WARNING....: Megafunction scfifo does not recognize the current device family [FLEX10]- ensure that you are using the newest version of the megafunction. (this is what I get when compiling the scfifo alone) I'm working with MAX PLUS II 9.01 As a device I'm using a FLEX10K10 that doesn't support dualport RAM. The proper component is assigned in the project options and I have already tried to use the library from MAX PLUS II 9.40, in order to have a newer lpm code. Nothing yielded any success. Did anybody encounter similar problems or is it just me and my installation? I'm greatfull for any hint JonasArticle: 27729
John, Thanks a lot, this information is exactly what I needed. Rotem. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27730
On Tue, 5 Dec 2000 09:53:26 -0500, "Jamie Sanderson" <jamie@nortelnetworks.com> wrote: >I was wondering what people consider the current rule of thumb to be. On the >design I'm currently working on, our worst nets have approximately 70% >routing and 30% logic delay. It's a Virtex-E 1000 with about 60% of the >slices and 80% of the block RAM used. I was talking to an Amplify support engineer at Synplify and he told me that this is similar to numbers they see all the time. He also told me that Amplify does a good job in these cases :-) Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 27731
In article <XrXW5.35660$II2.3256145@newsread2.prod.itd.earthlink.net>, "Chuck Woodring" <woodringfam@earthlink.net> wrote: (snip usual OrCAD complaints) > To get to the point - Is anyone out there using ORCAD Epress. If so we > should start our own email support group or something. (snip) There is an OrCAD forum hosted by OrCAD, including a section on Express: http://knowledge.orcad.com/~exchange We use OrCAD, and Express 9.1. We only use Express if forced to by a customer. We use it with schematic entry only, not VHDL. Even with schematic entry only, there are errors in some of the macros. I would hope that the Synplicity software (which we have received but have not yet installed) would allow decent VHDL entry. I would hesitate to mix this with OrCAD schematic entry. OrCAD Cpature is great for PCB schematics, but it is a minefield for PLD schematics. We like to use Viewdraw and Viewsim for CPLD and FPGA entry and simulation. I am told that you can also mix in HDL modules (as EDIF netlists), but I have not tried it. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27732
erika_uk@my-deja.com wrote: > how can i control the use of BX?.can i direct the tool to get 0 or 1 > from what you said above ? The mainstream tools will/should infer the use of this structure. If you need total control and would enjoy messing with CLB resources like this, the only tool that works at this level is JBits. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 27733
I am dealing with an FPGA board vendor that doesn't feel it is necessary to do gate level simulations. Problem is, with their board models, one cannot do gate level simulations as the Pads for the chip start off in an unknown state and aren't set via the GSR - which pretty much ruins the simulation in a hurry. My question is - what do y'all feel about: 1) The importance of at least being able to run a gate level simulation if you wanted to 2) The wisdom of running gate level simulations on FPGA's in general Obviously I am trolling for a little input to take back to the board vendor, but I am interested in other's experience. The biggest reason I have for doing gate level simulations is as another sanity check when the simulation works and the chip doesn't. I have had a problem with this vendor because a particular driver function did not work - I could have discovered that a lot sooner had I been able to prove that the gate-level backannotated timing simulation worked. Cheers, Gary spivey AT rincon.comArticle: 27734
kolja@prowokulta.org writes: > I am wondering if it really is a good managment decision to sell > 100K Parts to one customer instead fo selling 100 Parts each to 1K > customers. > Xilinx will loose big customers to gate array manufactures and small > customers to Altera. There's a lot less overhead to selling 100K parts to a single customer. Taking a short term view (which is all most businesses do any more), a single big customer is clearly better than a lot of small ones.Article: 27735
Hi, I am wanting to use a CPLD to configure a Spartan II FPGA in slave serial mode from 32 bit wide ROM. This seems simple on the face of it - pulse /PROGRAM low, wait for /INIT to go high, and then simply read in a word at a time and shift the bits out syncronised to a clock. While reading a Xilinx application note (XAPP098 - The Low-Cost, Efficient Serial Configuration of Spartan FPGAs) I noticed that this refers to having to wait for a period between 55us and 275us after /INIT goes high before starting to drive the data through on the CCLK input. This time delay seems excessively long, especially when I hope to clock the data in at about 2MHz, and it is undocumented in the Spartan II or Spartan/XL datasheets. Does anyone know if and why this would be required? I was hoping to use quite a small CPLD for the configuration device, but the need for this extra delay may push me up to a larger one. When the Spartan II is configured it will be a CPU, and the ROM will also be interfaced to it, hence the Spartan II and the CPLD are both going to need to be able to claim access to the ROM. Most of the time this is alright, because the CPLD will only access the ROM after /PROGRAM has been pulled low and the Global Tri-State will be held on the Spartan II, and likewise the CPLD can tri-state it's outputs when it has finished configuring the Spartan II. The only place I can see a problem is during the startup sequence. Do I have to present valid data bits while clocking the startup sequence? If so there is a chance the CPLD may need to read from the ROM after the Global Tri-State has been released. Will the DONE signal always go high before GTS, GSR and GWE are released? How many clocks do I need to present after DONE has gone high to complete the startup? Can I simply leave the CCLK going after the Spartan II comes alive? Any answers or thoughts on these questions would be greatly appreciated. Thanks, Dean Armstrong The University of Waikato.Article: 27736
Hi Gary, This is a discussion often visited in this forum. To look at a previous thread, check out the following link: http://www.sigda.acm.org/Archives/CollectedInformation/NewsgroupHighlights/may95/Summary-Static_timing_vs_Timing_Simulation.txt Tim Gary Spivey wrote: > I am dealing with an FPGA board vendor that doesn't feel it is necessary to > do gate level simulations. Problem is, with their board models, one cannot > do gate level simulations as the Pads for the chip start off in an unknown > state and aren't set via the GSR - which pretty much ruins the simulation > in a hurry. > > My question is - what do y'all feel about: > > 1) The importance of at least being able to run a gate level simulation if > you wanted to > > 2) The wisdom of running gate level simulations on FPGA's in general > > Obviously I am trolling for a little input to take back to the board vendor, > but I am interested in other's experience. The biggest reason I have for > doing gate level simulations is as another sanity check when the simulation > works and the chip doesn't. I have had a problem with this vendor because a > particular driver function did not work - I could have discovered that a lot > sooner had I been able to prove that the gate-level backannotated timing > simulation worked. > > Cheers, > Gary > spivey AT rincon.comArticle: 27737
Dean- Here are your answers: >Do I have to present valid data bits while clocking the startup >sequence? No- the bitstream contains dummy bits (all 1's) to make sure that clocks are given. It's the clocks that count, not the data. >Will the DONE signal always go high before GTS, GSR and GWE >are released? By default, yes. However, you can change when these things happen by messing around with certain bitgen options (XAPP138 has details of these options, and the startup sequence). The default should work fine for you. >How many clocks do I need to present after DONE has gone high >to complete the startup? This depends on the bitgen options. If you are using the default, at least 4. >Can I simply leave the CCLK going after the >Spartan II comes alive? Yes. Hope this helps, MikeArticle: 27738
There is another issue. The Virtex XCV200 IS available, it's just at an absurd price of $280 when the Spartan II XC2S200 is $45. That's just plain silly.Article: 27739
Oh, yeah, about the waiting after INIT thing. The Spartan-II architecture is much different than the Spartan or Spartan-XL architecture, given it's a derivative of the Virtex architecture, and not the 4000 like Spartan and Spartan-XL. You don't need to wait a set amount of time after INIT goes high. Once INIT goes high, you can start pumping data at the part with no latency. If you check out Figure 12 in the datasheet, it should a delay from INIT high to CCLK, but this is only for CCLK *output*, meaning Master Serial configuration. If you are using Slave Serial or Slave Parallel, there is no required latency. MikeArticle: 27740
Sorry, I forgot the titleArticle: 27741
In article <qhn1eapsbz.fsf@ruckus.brouhaha.com>, Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: > kolja@prowokulta.org writes: > There's a lot less overhead to selling 100K parts to a single > customer. > Taking a short term view (which is all most businesses do any more), > a single big customer is clearly better than a lot of small ones. That's why they charge twice the price to small customers, isn't it? Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27742
kolja@prowokulta.org wrote: > In article <qhn1eapsbz.fsf@ruckus.brouhaha.com>, > Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: > > kolja@prowokulta.org writes: > > There's a lot less overhead to selling 100K parts to a single > > customer. > > Taking a short term view (which is all most businesses do any more), > > a single big customer is clearly better than a lot of small ones. > > That's why they charge twice the price to small customers, isn't it? > > Sent via Deja.com http://www.deja.com/ > Before you buy. No, its to make sure that small customers don't turn into big ones & overload the direct sales channels.Article: 27743
gazit@my-deja.com wrote: > In article <90gj7t$2ivb$1@noao.edu>, > Andy Peters <"apeters <"@> n o a o [.] e d u> wrote: > > gazit@my-deja.com wrote: > > > > > > Hi, > > > I am working on a new design , using XCV400-BG560. > > > How can I find out (except looking at the Pin-out symbol diagram) > > > which > > > I/O pin belongs to each of the banks ? > > > > The data sheet for the part will tell you. > > No it doesn't (as far as I could see); > The only way to extract which I/O pin belongs to each of the banks from > the data sheet is to observe its relative location in the BG560 PIN > Function Diagram. > > > > Is there a source for Orcad symbols for Virtex family parts or do I > > > need to generate my own ?. > > > > I always generate my own FPGA symbols. Instead of one big block with > > 560 pins, I break the symbol up into multiple logical symbols (SDRAM > > controller, local interface, clocks/reset/power, test points, etc.) > > It's much easier to read. > > I agree, but it is always easier to start from existing symbol and > modify it to your needs instead of starting from scratch. > > > There's another way: Write a simple piece of Verolog/VHDL that exactly fills the device, run it through to place&route, use some Perl to extract what you need from the .pad & .par report files.Article: 27744
Gary Spivey wrote: > I am dealing with an FPGA board vendor that doesn't feel it is necessary to > do gate level simulations. Problem is, with their board models, one cannot > do gate level simulations as the Pads for the chip start off in an unknown > state and aren't set via the GSR - which pretty much ruins the simulation > in a hurry. > > My question is - what do y'all feel about: > > 1) The importance of at least being able to run a gate level simulation if > you wanted to > Without question. The answer to (2) says why. > > 2) The wisdom of running gate level simulations on FPGA's in general > I always run at least one on each design as, at the very minimum, its the only known way of finding bugs in the FPGA place & route tools. Anything else is just blind faith.Article: 27745
Hi! Any body knows some good sites providing basic information regarding the adaptive filter theory..? -- --saqib yaqub-- Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27746
Jonas Weiss <jweiss@kontronmedical.ch> wrote in <3A2D0260.37A10FFF@kontronmedical.ch>: >ERROR....: Undefined evaluated function "Family_Has_Dualport_EAB" in >expression As a device I'm using a FLEX10K10 that doesn't support >dualport RAM. Sounds like the desired macro requires dualport RAM, and you're trying to use a component that doesn't have it. If you want to use that function, you need a part that's provides the necessary building blocks. >WARNING....: Megafunction scfifo does not recognize the current device >family [FLEX10]- ensure that you are using the newest version of the >megafunction. So maybe you can't use a FLEX10. (Not familiar with the architecture, myself.) Maybe you need a part from a different family.Article: 27747
Greg Neff wrote: > > In article <XrXW5.35660$II2.3256145@newsread2.prod.itd.earthlink.net>, > "Chuck Woodring" <woodringfam@earthlink.net> wrote: > (snip usual OrCAD complaints) > > To get to the point - Is anyone out there using ORCAD Epress. If > so we > > should start our own email support group or something. > (snip) > > OrCAD Cpature is great for PCB schematics, but it is a minefield for > PLD schematics. I would second that vote. I had a *very* bad runin with Orcad a couple of years ago with a version 7 of the Express tools. I learned a very important lesson there. Now I *always* verify tools before I shell out a penny for them. If they won't let me trial run them through a small project, I don't bother with them. Xilinx has *free* synthesis tools available on their web site. I have used them a bit, but I have not gotten to the point of testing a chip yet. Good luck, if you stick with Orcad, I think you are going to need it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX URL http://www.arius.comArticle: 27748
you need to use the 'aglobal.inc' that is in maxplus2 9.4. This file defines the macros that you mention and that were undefined with maxplus2 9.01 JeanArticle: 27749
Thanks, unfortunately I'll have to use the FLEX10K as I'm working on an existing design. What is confusing me, is that 'Help' on these 'Megafunctions' says that it would support FLEX10 devices generally and even others that don't have dual port ram neither. ...I'm not very fancy building my own FIFO. Any suggestions? Thanks Jonas
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