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Dave Feustel wrote: > I am attempting to install the Xilinx Foundation Software eval package > On Windows 2000 Pro. When I enter the required registration id, the setup program > displays a message saying that this software won't install with any other Xilinx > software installed. Unfortunately the error message includes absolutely no > information as to which other software package (or where it is on the disk) > that the setup program finds offensive > . > I have checked the start programs menu, the top level C directory and the > registry and I can find no sign of any software identified as from Xilinx. > > There is installed on this machine some software licenced from Atmel. > There also is something from Mentor Graphics installed. > > Does anyone have any idea what software it is that the Xilinx setup program > is complaining about? > > Thanks, > > Dave Feustel > Fort Wayne, Indiana In theory you can install 3.3i with various other Xilinx packages (there's a solution record somewhere in the answers database). I think this restriction is purely for the eval version. What I did was to copy my 2.1i & WebPACK installations somewhere else and then uninstall them. The 3.3i eval installs fine & I can still get to the other stuff, at least from the command line, by setting the ``XILINX'' env variable to point to whichever toolset I want to use. [It helps to have Cygwin installed and use the ``bash'' shell]. However this was on NT-SP6a.Article: 33376
Hi, ALTERA Prototyping Boards are also available @ ElCamino, just try www.elca.de :-) CU, Carlhermann SchlehausArticle: 33377
Hi all, I tried out Synopsys FPGA Express (free from altera for the pc) and found the editor to be really awful. Surely they'd have syntax highlighting in this day and age? The error messages and pdf based help system are really not something i'd describe in a public place<g> I couldn't try Leonardo Spectrum until i get an old network card with NIC. Will it work without a network connected? (using win2k) Whats Leonardo like compared to spectrum for the editor and help system? -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33378
Hi Dave,
I always created my own new projects and never used the existing
ones. From your post I understand the following:
> !islow .all
>
> !ishigh .pct=100%
>
> !prep
>
> Reading "C:\SILOS3\EXAMPLES\exam2.ss1"
> Highest level modules (that have been auto-instantiated):
> test_bench
> 11 total devices.
> !fsim
>
I think lines starting with "!" are commands for Silos and "fsim" is the
command to start their fault simulator. If so this isn't what I would do as
a first step in using Silos III as a simulator. Perhaps this exam2 project
is intended for that purpose. If you are interested in just using Silos as a
verilog simulator try creating your own project.
HTH,
Srini
--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India
Article: 33379In article <9n9rlto9b7opav9lvd7tqntcb0g8jg3o5n@4ax.com>, gregeneff@yahoo.com says... > On Mon, 23 Jul 2001 10:17:49 +0200, Nicolas Matringe > <nicolas.matringe@IPricot.com> wrote: > > We have incorporated this logic into a few of our test sets. The > biggest problem that we found is that the 74HC125 input buffers are > very sensitive to input noise, producing glitches on the outputs. > Glitches on CLK are bad news. I guess those capacitors on the HC125 > outputs are supposed to be a fix for this, but they would have been > more effective on the inputs. > > We added pairs (series connected) of 74ACT14 Schmitt trigger inverters > in front of the HC125 inputs (DIN, CLK, and TMS_IN). We also added a > 68pf cap to ground on the CLK input at the parallel cable connector. > This circuit has worked flawlessly ever since, even with long cables. > > >Hi > >I've built a Xilinx Parallel cable according to the schematics available > >on Xilinx's site and it doesn't work. When I use the original cable > >everything is fine so my board is OK. I looked at the signals with an > >oscilloscope and everything seems normal (I see TDI, TCK and TMS toggle > >on the board), except that TDO stays high. Any idea? > > > =================================== > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > Should it not be more correct to use HCT instead of HCs? Xilinx in their schematics (038057, from 10 july 1996) uses a HC125, but the signals levels on the printer plug are TTL. -- Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.itArticle: 33380
Hi, I would like to use FPGA to listen the intel FSB bus. Can you please help me with any information on intel FSB bus? If the frequency of FSB bus is 100MHz, Will I be able to manage it using Altera FPGA? Any help would be appreciated.Article: 33382
Speedy Zero Two schrieb: > > Hi Nicolas, > > I have read this thread with interest as I was making a homebrew cable > myself. [...] We made also some cables and for other purpose we also integrated the interface into the board. The only problem we faced with the cables was unsufficient bypassing (cable and/or CPLD) and to large tolerances of Vcc. In programming mode the devices are sensitive concerning power supply. The diodes in the cable should have low drop too. We also hold the distance from the cable to CPLD as short as possible (20 cm). It would be nice to have a little test program, to be able to check the cable with a continous puls train without the need of having the CPLD connected. greetings, bertram -- Bertram Geiger, bgeiger@aon.at HTL Bulme Graz-Goesting - AUSTRIAArticle: 33383
Klaus Falser a écrit : > > Should it not be more correct to use HCT instead of HCs? > Xilinx in their schematics (038057, from 10 july 1996) > uses a HC125, but the signals levels on the printer plug > are TTL. HCT work with a power supply between 4.5 & 5.5V, HC work between 2.0 & 6.0V (and it's recommended no to apply more than Vcc on the inputs) -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 33384
Russell Shaw a écrit : > > Hi all, > > I tried out Synopsys FPGA Express (free from altera for the pc) > and found the editor to be really awful. Surely they'd have syntax > highlighting in this day and age? The error messages and pdf > based help system are really not something i'd describe in a > public place<g> > > I couldn't try Leonardo Spectrum until i get an old network > card with NIC. Will it work without a network connected? (using > win2k) > > Whats Leonardo like compared to spectrum for the editor and > help system? Leonardo is nothing but a synthesis tool, tou won't get an editor with it unless you buy Renoir (packed with Spectrum & ModelSim in FPGAdvantage). Anyway, many people here will recommend you to use Emacs as an editor. It's really powerful (especially for VHDL) -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 33385
Has anybody had any experience running ModelSim on a Windows box (currently Windows98) within the cygwin environment? Currently, I can do all ModelSim functions from a DOS window, but from within cygwin, I appear to be having trouble with vish. Basically, I can vsim, but I can't get any gui to come up if the app is started within the cygwin shell. Does anybody know if this is possible and if so, what environment and/or other changes need to be made? Cheers, Gary spivey@ieee.orgArticle: 33386
Hi, After a BGA Xilinx FPGA (xcv1000e) has been soldered onto a board, can anyone suggest a way of determining whether the power pins are soldered correctly. We can check the i/o pins between adjacent FPGA's, we can check the chip registers themselves (although this is probably not a useful test as this would be done at the factory), and can do various other checks...but are trying to think how we can detect power supply problems. We have thought of a few ideas ranging from creating a hard macro that has on-the-edge timing, and tile the whole device. If there are localized power problems, then we may be able to detect bit errors in a given tile. Or we could connect all the registers together, or do a JTAG, and hope that power supply problems would manifest in bit errors and so on. So, any neat ideas anyone? Regards, Gary Cook Sony Oxford, UK.Article: 33387
The renowned Gary Cook <gc@sonyoxford.co.uk> wrote: > After a BGA Xilinx FPGA (xcv1000e) has been soldered onto a > board, can anyone suggest a way of determining whether the > power pins are soldered correctly. X-ray inspection. Best regards, -- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Spehro Pefhany --"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com Contributions invited->The AVR-gcc FAQ is at: http://www.BlueCollarLinux.com =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=Article: 33388
"Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in> wrote in message news:9jln51$n11@news.or.intel.com... > Software & Silicon Systems India Pvt. Ltd. (An Intel company) How long have you been an Intel company?Article: 33389
"Gary Spivey" <spivey@ieee.org> writes: > Has anybody had any experience running ModelSim on a Windows box (currently > Windows98) within the cygwin environment? Not exactly, I have win2k. I'm not exactly sure what your problem is? I just tried vsim from cygwin's bash shell and I got the GUI okay. I also tried running vish and got the '%' prompt and could run a few commands. I even ran vsim from within vish and got the GUI. It all seems to work okay. So I'm not helping you sort your problem! The only ModelSim-specific environment I have are LM_LICENSE_FILE and PATH. I haven't tried ModelSim in win98 although I've had no problems with cygwin in that environment. -- Andy Rushton LME Design Automation Limited, UKArticle: 33390
On Wed, 25 Jul 2001 02:03:09 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: (snip) > >Or was it accidental ? I have a feeling that our ancient ca 1996/7 >Parallel-III cable might not use the HC parts, these might have been added to >program XL devices on pure 3V3 boards - I'll check. > > > We always power the parallel cable (or equivalent logic) from 5V, even when programming XL devices. AFAIK, all Xilinx XL products have 5V tolerant I/O. =================================== Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 33391
Hi, I'm wondering if anyone knows if it is possible to purchase a DIME module (expansion module standard for FPGA cards etc.) that contains RAM, but no FPGAs? I have an FPGA card that lacks external RAM but has a DIME module slot. Thanks, James BrennanArticle: 33392
I've designed a system with 3 primary clocks. I've designed a simple divider-by-2 on those clocks. However, the resultant divided clock is periodic. There are some points of phase-inversion. How can I overcome this problem? FPGA: Xilinx XCV2000E-8 Software: Foundation 3.1 Input Clocks: 20MHz, 21.4MHz, 12.25 MHz Error Watched: (by Logic Analyser) A divider from 12.25 MHz to 6.125 MHz Timing Reports: Minimum period: 37.712ns (Maximum frequency: 26.517MHz) Warning Errors in implementation flow: WARNING:NgdBuild:479 - The input pad net 'AUX_P_RESET_N' driving one or more clock loads should only use a dedicated clock buffer. This could result in large clock skews on this net. WARNING:NgdBuild:479 - The input pad net 'CLK1' driving one or more clock loads should only use a dedicated clock buffer. This could result in large clock skews on this net. WARNING:NgdBuild:477 - clock net 'N8316_BUFGed' has non-clock connections WARNING:NgdBuild:477 - clock net 'uni/bufg_cam_pclk' has non-clock connections What I've tried to do: use BUFG primitives on high fan-out sub-clocks. but failed.... Please help me.....Article: 33393
Nicolas Matringe <nicolas.matringe@IPricot.com> writes:
> Anyway, many people here will recommend you to use Emacs as an editor.
> It's really powerful (especially for VHDL)
Not exactly making use of the more powerful features of emacs but I
have vhdl-mode abbreviations so for example "isl" becomes "in
std_logic", "isv" becomes "in std_logic_vector ()" etc.
Jon
Article: 33394Good Idea. I'll give it a shot. "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in> wrote in message news:9jln51$n11@news.or.intel.com... > Hi Dave, > I always created my own new projects and never used the existing > ones. From your post I understand the following: > > > > !islow .all > > > > !ishigh .pct=100% > > > > !prep > > > > Reading "C:\SILOS3\EXAMPLES\exam2.ss1" > > Highest level modules (that have been auto-instantiated): > > test_bench > > 11 total devices. > > !fsim > > > > I think lines starting with "!" are commands for Silos and "fsim" is the > command to start their fault simulator. If so this isn't what I would do as > a first step in using Silos III as a simulator. Perhaps this exam2 project > is intended for that purpose. If you are interested in just using Silos as a > verilog simulator try creating your own project. > > HTH, > Srini > > -- > Srinivasan Venkataramanan > ASIC Design Engineer > Software & Silicon Systems India Pvt. Ltd. (An Intel company) > Bangalore, India > > >Article: 33395
Gary Cook <gc@sonyoxford.co.uk> writes:
> can anyone suggest a way of determining whether the
> power pins are soldered correctly. We can check the i/o pins
Beyond measuring some supply current would it be safe to pass a larger
current (hundreds of milliamps) between power pins with everything
else isolated and floating ?
Jon
Article: 33396Xilinx Support resolved this problem by giving me a different registration number which apparently makes the install ignore whatever caused the conflict. "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B5E1D05.A6CD1528@algor.co.uk... > > > Dave Feustel wrote: > > > I am attempting to install the Xilinx Foundation Software eval package > > On Windows 2000 Pro. When I enter the required registration id, the setup program > > displays a message saying that this software won't install with any other Xilinx > > software installed. Unfortunately the error message includes absolutely no > > information as to which other software package (or where it is on the disk) > > that the setup program finds offensive > > . > > I have checked the start programs menu, the top level C directory and the > > registry and I can find no sign of any software identified as from Xilinx. > > > > There is installed on this machine some software licenced from Atmel. > > There also is something from Mentor Graphics installed. > > > > Does anyone have any idea what software it is that the Xilinx setup program > > is complaining about? > > > > Thanks, > > > > Dave Feustel > > Fort Wayne, Indiana > > In theory you can install 3.3i with various other Xilinx packages (there's a solution > record somewhere in the answers database). I think this restriction is purely for > the eval version. What I did was to copy my 2.1i & WebPACK installations somewhere > else > and then uninstall them. The 3.3i eval installs fine & I can still get to the other > stuff, at least from the command line, by setting the ``XILINX'' env variable to > point to whichever toolset I want to use. > [It helps to have Cygwin installed and use the ``bash'' shell]. > > However this was on NT-SP6a. > > >Article: 33397
Hi I am attempting to install an evaluation version of ISE 3.3 on a Windows ME machine (750MHz pentium III laptop, 128M RAM) . Is this possible/has anyone else tried this?? It does actually install, and the Project Navigator comes up - and then dies after about 1 second...There is no other Xilinx s/w on the machine. I'd put this to the support people, but I've only just registered & haven't got access to the web case tools yet. regards, Paul Teagle CAE IncArticle: 33398
Hello, Can I use Foundation ISE and VCC software for PCI application development? When I try to creat new project with VCC software (HOT II Demoboard, www.vcc.com) , it make .pdf project. In FND ISE project have .npl extention. Thanks in advance, Blagomir mail: donchev@ecad.vmei.acad.bgArticle: 33399
Never lose sight of gate-level designs; however, most designs today are implemented via hardware design language such as VHDL, ABEL, or Verilog -- The best analogy I can offer to describe the difference between gate-level hiearachical designs vs HDL designs is assembly language code vs compiled code. Gate level design IMHO are more efficient in their use of gates/resources;whereas, HDL designs explode into a gillion gates. However, since most FPGAs contain a gillion gates this is not an issue. A good understanding of digital logic/gate design is to your advantage when inferring logic & control circuits via HDL. I still design using both gate-level and HDL-level techniques. Noddy wrote: > Hi, > > As you've guessed from recent posts, I'm very new to using FPGAs (couple of > months). I've been spending my time implementing schematic design entries > (using Foundation ISE). This brings me to my question? Should I rather be > attempting to implement my designs in VHDL instead? My experience with VHDL > is the Designer's Guide to VHDL! > > Any suggestions? > > Adrian
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