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Hallo, For all who answered (in)directly to my questions: thanks !!! ___ / __|__ / / |_/ Groetjes, Ruud \ \__|_\ \___| http://Ruud.C64.orgArticle: 32754
Chris, I have had similar trouble with the BRAMs. I found that the routing delay in getting the BRAM output anywhere can be as large as the TBCKO (clk->out). I tried registering the BRAM outputs, and found there was a huge delay in just getting the BRAM outputs to the input of a flop. The Xilinx placer also seems to do a poor job of placing BRAMs near the logic they drive or vice versa. This is true even when only a fraction of the part is being used. Maybe there's just an architecture problem. I noticed that Synplify, when making routing delay estimates, way underestimates the actual results, so the design seems to meet timing after synthesis but fails miserably in P&R. When I last had this problem, I just had to come up with a source-code solution. I was using BRAMs as lookup tables, and I used each port of the BRAM as a separate lookup and only used each port every other cycle. Hopefully SpartanII has better BRAM routing. -Kevin "chris" <cjwang_1225@hotmail.com> wrote in message news:24a13eb0.0107060947.2b68ea73@posting.google.com... > hi. i am doing post-route simulation on a design using the virtex > block ram. when i probe at the address and clock inputs, and the data > output, i see that there is a 14 ns delay from the clock rising edge > to the data appearing on the output data bus. i suspect that there is > something wrong with the way i configured the block ram, or some > setting i did not perform because the switching characteristic is that > the clock -> dout is 4.3 ns for the speed grade i have. the clock is > on a clock buffer (bufg) so that the slew rate is not a problem (my > original suspicion). i don't think it is routing delay because i am > probing directly at the inputs and outputs of the block ram > instantiation (RAMB4_S16). does anyone have any suggestions or > comments on what could be the problem? thank you in advance. > chris wang >Article: 32755
Hi, I am just designing a board with the Spartan2 XC2S15. In the Data-Sheets Specs. there is a power up current of min. 500mA. Thats quite a lot for the smallest Device. My operating current will be about 100mA. Do I really nead a power supply rated for 500mA at the 2.5 Volts? Does anybody knows the reason for such a large power up current Is this current the same for every Spartan2 Device for XC2S15 to XC2S200? Is there a Reference Design for Power Supply? thanks peterArticle: 32756
There are a couple of things automatic placement is not very good at, and BRAM placement is one of them. For best performance, you'll want to do a bit of floorplanning, and also register the inputs and outputs of the BRAM with just registers (no combinatorial logic in front of the registers). YOu'll also want to floorplan the placement of those registers to get them as close as possible to the BRAMs, especially for the EN and WE if you are using those. The routing around the BRAM is only half the problem (the BRAM tends to congest routing), the long delays into and out of the BRAM are the other half of the problem. A design change to access twice as many bits per access so you can cut the clock cycle to the BRAM in half will probably get you more mileage than tweaking ot get a few more tenths of ns. Kevin Neilson wrote: > Chris, > I have had similar trouble with the BRAMs. I found that the routing delay > in getting the BRAM output anywhere can be as large as the TBCKO (clk->out). > I tried registering the BRAM outputs, and found there was a huge delay in > just getting the BRAM outputs to the input of a flop. The Xilinx placer > also seems to do a poor job of placing BRAMs near the logic they drive or > vice versa. This is true even when only a fraction of the part is being > used. Maybe there's just an architecture problem. I noticed that > Synplify, when making routing delay estimates, way underestimates the actual > results, so the design seems to meet timing after synthesis but fails > miserably in P&R. > > When I last had this problem, I just had to come up with a source-code > solution. I was using BRAMs as lookup tables, and I used each port of the > BRAM as a separate lookup and only used each port every other cycle. > Hopefully SpartanII has better BRAM routing. > > -Kevin > > "chris" <cjwang_1225@hotmail.com> wrote in message > news:24a13eb0.0107060947.2b68ea73@posting.google.com... > > hi. i am doing post-route simulation on a design using the virtex > > block ram. when i probe at the address and clock inputs, and the data > > output, i see that there is a 14 ns delay from the clock rising edge > > to the data appearing on the output data bus. i suspect that there is > > something wrong with the way i configured the block ram, or some > > setting i did not perform because the switching characteristic is that > > the clock -> dout is 4.3 ns for the speed grade i have. the clock is > > on a clock buffer (bufg) so that the slew rate is not a problem (my > > original suspicion). i don't think it is routing delay because i am > > probing directly at the inputs and outputs of the block ram > > instantiation (RAMB4_S16). does anyone have any suggestions or > > comments on what could be the problem? thank you in advance. > > chris wang > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32757
In article <3B463F35.74114029@artsci.wustl.edu>, Jon Elson <jmelson@artsci.wustl.edu> wrote: > > >Subodh Nijsure wrote: > >> [ Not certain if this is the most appropriate group to post this message, >> could only find this fpga related newsgroup ] >> >> I have Xlilinx XCV50E for which I have bitstream file (.XBN), that I want to >> download. I am using a ALTERA CPLD to send this bitstream to the FPGA. >> Platform is running Linux (2.4.2) on Motorola 860 processor. I am writing >> a driver to send this file to the FPGA >> >> The basic quesiton I have is, when I am clocking this bitstream to the >> FPGA, as I read the byte from a file, should I be shifting the bits >> MSB first or LSB first? > >LSB first. > One of the earlier response indicated MSB first, I guess I will just have to download a file to FPGA and see what works (?). /SubodhArticle: 32758
I don't have a data sheet handy, but (to make things worse) I think the Spartan-II also specifies a ramp rate for the VCC voltage. Check the notes in the data sheet, but I think it can't be ramped faster than 2mS or slower than 50mS. We looked at using the Spartan-II recently. Supplying 500mA at power-up is bad enough, but keeping the ramp rate between 2 and 50mS made the power-supply complicated and more expensive. If you contact Xilinx tech. support they will send you a reference power-supply circuit that can handle the 500mA surge current, but it uses a very large capacitor to supply the current. At the time they could not recommend a simple LDO regulator that would control the ramp rate without external circuitry. Xilinx also requires the voltage ramp to be monotonic, which is difficult to achieve when the surge current might be 500mA. The big current hit will cause a dip. If the ramp is not monotonic, Xilinx says it may not configure. Our Xilinx FAE said they were working on a different regulator reference circuit, so maybe they have a better solution now. For our design, we decided to use the Altera Acex EP1K10. Altera tech. support said that the surge current would be <100mA and there was no minimum ramp time. [Although, they still have a maximum ramp time requirement and the ramp must be monotonic.] Gerald "Peter Lang" <Peter.Lang@gmx.de> wrote in message news:9i6j50$mcn$01$1@news.t-online.com... > Hi, > I am just designing a board with the Spartan2 XC2S15. > In the Data-Sheets Specs. there is a power up current of min. 500mA. > Thats quite a lot for the smallest Device. My operating current will be > about 100mA. > Do I really nead a power supply rated for 500mA at the 2.5 Volts? > Does anybody knows the reason for such a large power up current > Is this current the same for every Spartan2 Device for XC2S15 to XC2S200? > Is there a Reference Design for Power Supply? > thanks peter > > > >Article: 32759
This was thrashed out earlier this year. Follow the threads by clicking the ">>" to the right of the "T" in the links line at the begiining of each article. Try the following: http://www.fpga-faq.com/archives/29325.html#29327 http://www.fpga-faq.com/archives/29725.html#29731 http://www.fpga-faq.com/archives/30700.html#30719 On Sat, 7 Jul 2001 11:02:09 +0200, "Peter Lang" <Peter.Lang@gmx.de> wrote: >Hi, >I am just designing a board with the Spartan2 XC2S15. >In the Data-Sheets Specs. there is a power up current of min. 500mA. >Thats quite a lot for the smallest Device. My operating current will be >about 100mA. >Do I really nead a power supply rated for 500mA at the 2.5 Volts? >Does anybody knows the reason for such a large power up current >Is this current the same for every Spartan2 Device for XC2S15 to XC2S200? >Is there a Reference Design for Power Supply? >thanks peter > > > =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 32760
hi all. i'm really happy i found out this newsgroup existed. i think i would have progressed a lot faster in my design skill if i particpated in this group earlier. i have a question about how to maintain net names in synplicity and also in the xilinx place and route tool. i am having a difficult time debugging the post-synth and post-PAR netlists because all the names are changed in my design. does anyone know how to disable this, or at least partly disable it? thanks. chrisArticle: 32761
I guess this is one for the experts in comp.lang.vhdl Though I am not a guru on this stuff, the example from the Manual looks OK to me. In your version of the Manual code, the final assignment from a RESOLVED_BIT to a BIT does not look right... "Sven Blankenberg" <s.blankenberg@hs-zigr.de> wrote in message news:79f58899.0107050047.5282de09@posting.google.com... > As I read your post: > > 1. the example in the reference manual does not work. > > 2. this recode does work: > > c <='0' when a='0' else 'Z'; > > c <='0' when b='0' else 'Z'; > > > > Can you post the reference manual example? > > of course, i' can. > > -- copy from Manual > package RES_PACK is > function RES_FUNC(DATA: in BIT_VECTOR) return BIT; > subtype RESOLVED_BIT is RES_FUNC BIT; > end; > > package body RES_PACK is > function RES_FUNC(DATA: in BIT_VECTOR) return BIT is > -- synopsys resolution_method wired_and > begin > -- The code in this function is ignored by the program > -- but parsed for correct VHDL syntax > for I in DATA'range loop > if DATA(I) = '0' then > return '0'; > end if; > end loop; > return '1'; > end; > > end; > > use work.RES_PACK.all; > > entity WAND_VHDL is > port(X, Y: in BIT; Z: out RESOLVED_BIT); > end WAND_VHDL; > > architecture WAND_VHDL of WAND_VHDL is > > begin > > Z <= X; > Z <= Y; > > end WAND_VHDL; > > -- and my changes for use internal signals > > use work.RES_PACK.all; > > entity WAND_VHDL2 is > port(clk, X, Y: in BIT; Z: out BIT); > end WAND_VHDL2; > > architecture WAND_VHDL of WAND_VHDL2 is > > signal a,b : BIT; > signal c : RESOLVED_BIT; > > begin > > process(clk) > begin > if clk'event and clk='1' then > a <= X; > b <= Y; > end if; > end process; > > c <= a; > c <= b; > > process(clk) > begin > if clk'event and clk='1' then > Z <= c; > end if; > end process; > > end WAND_VHDL2; > > SvenArticle: 32762
Program Announced
Registration Open
Last Call for Papers
2001 MAPLD International Conference
JHU/APL - Laurel, Maryland
September 11-13, 2001
Note new addresses: mapld2001@klabs.org
http://www.klabs.org
The 4th annual Military and Aerospace Applications of Programmable
Devices and Technologies International Conference will address devices,
technologies, usage, reliability, fault tolerance, radiation
susceptibility, and applications of programmable devices and adaptive
computing systems in military and aerospace systems.
The program, abstracts, and registration information can be accessed at:
http://klabs.org/richcontent/MAPLDCon01/MAPLDCon01.html
This year's Conference will also include papers and an emphasis on
CPU design (both traditional processors as well as those embedded
in ASICs/SoC and programmable devices), logic design, and device
reliability/fault tolerance.
The program will consist of oral and poster technical presentations
and industrial exhibits. This conference is open to US and foreign
participation and is unclassified. Select papers will be published
in the AIAA Journal of Spacecraft and Rockets.
Late news papers will be accepted for the Poster Session.
MAPLD will present two tutorials/seminars:
1. Programmable Logic Devices and Architectures
2. Advanced Design: Designing for Reliability
Invited Talks:
Arthur F. Obenshain, Director
Applied Engineering & Technology Directorate
NASA Goddard Space Flight Center
Major General Willie B. Nance, Jr., United States Army
Keynote Address
National Missile Defense Program Executive Officer;
System Program Director for the Ballistic Missile Defense
Organization
Dr. David A. Bearden, The Aerospace Corporation
"When is A Satellite Mission Too Fast and Too Cheap?"
Dr. Roger D. Launius, Chief Historian
National Aeronautics and Space Administration
Dr. James E. Tomayko
Invited History Talk
Carnegie Mellon University
"From Sequencers to Processors on Early U.S. Spacecraft"
Dr. C. Dianne Martin, The George Washington University
Invited Ethics Talk
"Recipe for Disaster: Engineering without Ethics
Dr. Don Bouldin, University of Tennessee
"Platform System-on-Chip Design"
Dr. Steve Guccione, Xilinx Corporation
"FPGAs for Fault Tolerant Circuits"
Technical Sessions:
A. Applications: Military and Aerospace
Session Chair: Ralph Kohler - Air Force Research Laboratory
B. Design 1: Processors, Logic, and Programmable Devices
Session Chair: Rich Katz - NASA Goddard Space Flight Center
C. Reliability: Devices and The Effects of the Radiation Environment
Session Chairs: Dr. James W. Howard, Jr. - Jackson and Tull
D. Design 2: Systems
Session Chair: Hans Tiggeler - University of Surrey
E. Design 3: Fault Tolerance
Session Chair: John McHenry - National Security Agency
P. Poster Session
Session Chair: David Hepner - US Army Research Laboratory
Panel Session:
Design and Analysis vs. Test and Verification
A Discussion of the Technical, Programmatic, and Ethical Issues
in Military & Aerospace Systems
The conference is sponsored by:
NASA Goddard Space Flight Center
JHU/Applied Physics Laboratory
National Security Agency
Electronics Radiation Characterization Project
Digital Engineering Institute
Military & Aerospace Programmable Logic Users Group
American Institute of Aeronautics and Astronautics
IEEE Aerospace & Electronic Systems Society (AESS)
Air Force Research Labs
For further information, please see the conference www home page at:
http://www.klabs.org/richcontent/MAPLDCon01/MAPLDCon01.html
http://klabs.org
http://rk.gsfc.nasa.gov
Article: 32763
Rick Filipkiewicz wrote:
[ snip ]
> I'm beginning to wonder if some legislation enforcing a Xilinx-style publicly
> accessible answers database [bug list] on all EDA & chip suppliers is becoming
> necessary. A car maker couldn't get away with putting the steering wheel in the
> trunk and the spare in front of the driver so why can EDA vendors get away with
> the equivalent and then hide behind NDAs or a support system with the reflexes
> of a stoned dinosaur ?
-- General babble; not Synplicity specific.
I don't know if legislation is the correct answer or even feasible; but
I do agree with your point. Consider the cases of the people who
design:
1. Control systems for expensive hardware,
2. Systems that are critical for humanoids
(i.e., aircraft, helicopters, signaling
equipment for railroads, etc.), or
3. Weapons systems and platforms.
If there is a case of a known bug of some type by the vendor and a user
is not made aware of it and it gets into a system, who is held liable
for the 'mishap?' Why should there be a mishap?
In addition to bugs, the algorithms in many of these tools are not
documented and are subject to change with each new download of code.
Just running functional test benches and doing timing analysis is
inadequate (i.e., lockup state issue). In one case, caught in
simulation but was a bit of a head scratcher, one vendor's synthesizer
changed the encoding of TRUE and FALSE between tool revisions.
Excellent point!
--
rk Each element, no matter how apparently
stellar engineering, ltd. insignificant it appears, more often
stellare@erols.com.NOSPAM than not is a single point failure in
Hi-Rel Digital Systems Design the successful operation of a total
system. -- Richard Smith, 1975
Article: 32765
Hi,
I'm trying to implement a scaling multiplier for 2s complement
numbers. I can't come up conceptually with how to do the shift and
adds and handle the signs. If I want to multiply two numbers such as
-2 * -3, what should the partial products be ?
Ex:
1110 -2
1101 -3
---------
11111110 -- Sign extend first partial product
00000000 -- Second partial product zero
11111000 -- Third partial product
???????? -- For this partial product I need -2^3 * (-2^3 + 2^2 + 2^1)
=
2^6 - 2^5 -2^4.
So, I guess I don't know the trick for representing this last partial
product, or I'm missing something obvious. Or, do I have the wrong
approach for doing the scaling multiplier with 2s complement numbers?
Can anyone help out or provide a good reference for me?
Thanks in advance,
Pat
Article: 32766You're very close. Just use the negative of the sign extended shifted partial product. This is because the top bit represents a negative number -2^3. Alan Nishioka alann@accom.com Pat McGuirk wrote: > Hi, > > I'm trying to implement a scaling multiplier for 2s complement > numbers. I can't come up conceptually with how to do the shift and > adds and handle the signs. If I want to multiply two numbers such as > -2 * -3, what should the partial products be ? > > Ex: > 1110 -2 > 1101 -3 > --------- > 11111110 -- Sign extend first partial product > 00000000 -- Second partial product zero > 11111000 -- Third partial product > 00010000 -- For this partial product I need -2^3 * (-2^3 + 2^2 + 2^1) > ======= > 00000110 2^6 - 2^5 -2^4.Article: 32767
One solution is: Save the XOR of the MSB of both numbers. For each number, if the MSB is set, negate the number (make it positive) Do the multiply, N-1 steps, since MSBs are always '0' If the saved XOR result is set, negate the result. Philip Freidin On 8 Jul 2001 11:00:59 -0700, pmcguirk@mrcmicroe.com (Pat McGuirk) wrote: >Hi, > >I'm trying to implement a scaling multiplier for 2s complement >numbers. I can't come up conceptually with how to do the shift and >adds and handle the signs. If I want to multiply two numbers such as >-2 * -3, what should the partial products be ? > >Ex: > 1110 -2 > 1101 -3 >--------- >11111110 -- Sign extend first partial product >00000000 -- Second partial product zero >11111000 -- Third partial product >???????? -- For this partial product I need -2^3 * (-2^3 + 2^2 + 2^1) >= > 2^6 - 2^5 -2^4. > >So, I guess I don't know the trick for representing this last partial >product, or I'm missing something obvious. Or, do I have the wrong >approach for doing the scaling multiplier with 2s complement numbers? >Can anyone help out or provide a good reference for me? > >Thanks in advance, >Pat Philip Freidin FliptronicsArticle: 32768
hi all. i have a design that has two clocks on it, one at 48 mhz and one at 12 mhz (48 mhz divide by 4). the divide down is done with the DLL on the Virtex 300 part. currently my design passes our simulation testbench after synthesis and place and route module by module, but when the whole thing is integrated and then goes through the design flow, then timing issues prevent the design from working at the specified speed. one thing i unsuccessfully tried was to get synplicity to recognize the 12 mhz and 48 mhz parts and optimize accordingly. i specified the different clock signals in SCOPE, but i still get the same warnings in the log file that some nets don't make the 48 mhz timing window (even though the nets are in the 12 mhz section). if i had to declare all the false or multicycle paths, it would kill me because there are so many. i was wondering if anyone has success in getting synplicity to recognize the different clock domains and optimize according to those frequencies. another thing is that i have a receive clock (RxClk) at 12 mhz which is derived from the incoming signal, and that clock has a lot of skew with my internal 12 mhz clock which it needs to be in phase with. is there a way to limit this clock to clock skew? and finally, in synplify i cannot simulate two separate module netlists at the same time. there is overlap between the modules it creates (ie: LUT3_2 or something like that) and it causes Verilog-XL to choke. does anyone know how to get around this problem? i have heard about the modular design option in synplify and am considering it. lastly, is it possible to place and route a design module by module? since i can get the pieces working but not the whole, i would like to PAR the pieces and then glue them together to make the whole. thanks for all the previous help. sorry this message is so long. chrisArticle: 32769
The start up current and possible ways to deal with it were discussed. But I don't think there are any conclusive results stated. Xilinx representatives indicated that they were working on a power supply design which is probably the one mentioned in the other posting here. Xilinx also indicated that they were working to characterize the current surge (which is very short lived) in more detail with the goal of reducing the requirement as a function of part size. But I have not heard any more of this. I don't know how many sockets have been lost due to this current requirement. But Xilinx has reduced this requirement in the Virtex II family. Philip Freidin wrote: > > This was thrashed out earlier this year. > > Follow the threads by clicking the ">>" to the right of the > "T" in the links line at the begiining of each article. > > Try the following: > > http://www.fpga-faq.com/archives/29325.html#29327 > > http://www.fpga-faq.com/archives/29725.html#29731 > > http://www.fpga-faq.com/archives/30700.html#30719 > > On Sat, 7 Jul 2001 11:02:09 +0200, "Peter Lang" <Peter.Lang@gmx.de> wrote: > >Hi, > >I am just designing a board with the Spartan2 XC2S15. > >In the Data-Sheets Specs. there is a power up current of min. 500mA. > >Thats quite a lot for the smallest Device. My operating current will be > >about 100mA. > >Do I really nead a power supply rated for 500mA at the 2.5 Volts? > >Does anybody knows the reason for such a large power up current > >Is this current the same for every Spartan2 Device for XC2S15 to XC2S200? > >Is there a Reference Design for Power Supply? > >thanks peter > > > > > > > > =================== > Philip Freidin > philip@fliptronics.com > Host for WWW.FPGA-FAQ.COM -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 32770
Marco wrote: > > Hello everybody, > > i am developing with an ACEX EP1K30. > My question: Do anybody know the best configuration device for that device? > i only know the EPC1 and EPC2. Are there some form other manufacturers ? > > Have anyone some schematics with the ACEX ???? > > Thank you very much. > > Best regards > > Marco You may find other problems in using this part unrelated to the hardware. We are working with the 10K parts on an existing board. We are trying to do a design with an 80 MHz clock where a portion of the circuit uses multiple clock cycles to process signals through combinatorial logic. It would appear that the MaxPlus II tools so not well support this type of design timing. The tool problems we have found are numerous. It is a bit like being in a maze and finding every path blocked. Our final approach is to simply constrain the entire design to 80 MHz, and manually examine all of the failure reports. The failures on single clock paths are fixed. The failures on multi-cycle paths are ignored. This is not fun as the failing paths change on each iteration of place and route. We call this the "whack-a-mole" approach. As you fix paths, other paths then fail. Once you have a working design, any change makes more moles pop up. One pleasant note is that the next release of the Quartus tool is supposed to support the 10K series. Quartus II has much better multi-cycle support. I don't know if they intend to support the 1K ACEX parts with Quartus II. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 32771
I was going to send you to my website, but on checking it I realize I never got around to putting the part on handling negative numbers on there. The secret is to realize that two's complement numbers are represented by weighting the msb as -2^(n-1), not 2^(n-1). Recognizing this, it becomes obvious that you need to subtract the partial (1xN) product corresponding to the MSB of the serial input instead of adding it. This is easiest to accomplish if you use an adder/subtractor instead of a straight adder for the scaling accumulator. That takes care of a signed serial input. For a signed parallel input, you simply need to sign extend the parallel input to the full width of the scaling accumulator (normally the scaling accumulator has one bit above the parallel input for an LSB first implementation). Also don't forget to sign extend the shifted accumulator feedback. Pat McGuirk wrote: > Hi, > > I'm trying to implement a scaling multiplier for 2s complement > numbers. I can't come up conceptually with how to do the shift and > adds and handle the signs. If I want to multiply two numbers such as > -2 * -3, what should the partial products be ? > > Ex: > 1110 -2 > 1101 -3 > --------- > 11111110 -- Sign extend first partial product > 00000000 -- Second partial product zero > 11111000 -- Third partial product > ???????? -- For this partial product I need -2^3 * (-2^3 + 2^2 + 2^1) > = > 2^6 - 2^5 -2^4. > > So, I guess I don't know the trick for representing this last partial > product, or I'm missing something obvious. Or, do I have the wrong > approach for doing the scaling multiplier with 2s complement numbers? > Can anyone help out or provide a good reference for me? > > Thanks in advance, > Pat -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32772
You might try just constraining the whole thing for 48 MHz. 48 MHz is not aggressive at all for any of the devices in the Virtex family. Then if you have paths that won't make timing, address them individually, either through multi-cycle time constraints or by revisiting the design. Personally, I prefer writing a UCF file to constrain the design rather than fooling around with the synplicity constraints. I've had more consistent results that way, and I am not as tightly tied to a particular synthesis tool. The multiple clock domains in the xilinx tools work well. The 12 MHz external clock is below the range for the DLL, so you can't use that to deskew the clock. I don't know you particular circuit, but my approach would be to initially receive the data using the skewed external clock, then internally retime it to the local 12 MHz clock by transferring it from the input register (clocked by the external 12 MH clk) to a second register syncronized to the internal 12 mHz clock. You can use the 48 MHz clock to clock the resyncing logic, since it is aligned pretty close to the internal 12 mHz clock by the DLL. Synplicity is not a simulator, so I am not sure what you mean by simulating two module netlists at once. I'm not sure what trouble you are having. If you are creating peices of the design as separate synthesis runs, those peices need to be instantiated as black boxes in a higher level design. The top level will give each piece a different hierarchical name. There can only be one top level netlist going into the xilinx tools. Same with a simulator. The place and route is currently a whole design flow, so you can't easily glue together partial place and routes. There is a way to do it using hard macros created in the FPGA editor. Basically, you have to create each part of the design as a hard macro then instantiate the pieces in a higher level design. It is clunky at best, and I don't recommend it. The xilinx environment does not produce hierarchical placement (the floorplan and UCF files are flat), so placement done in the backend tools isnot really modular. You can do modular placement by embedding hierarchical placement in your source, but it is more work. I do that on pieces that I will either reuse, or that will be instantiated many times in the design (and also on pieces that have a fairly regular simple structure). Otherwise, I just do it in the floorplanner each time. chris wrote: > hi all. > i have a design that has two clocks on it, one at 48 mhz and one at 12 > mhz (48 mhz divide by 4). the divide down is done with the DLL on the > Virtex 300 part. currently my design passes our simulation testbench > after synthesis and place and route module by module, but when the > whole thing is integrated and then goes through the design flow, then > timing issues prevent the design from working at the specified speed. > one thing i unsuccessfully tried was to get synplicity to recognize > the 12 mhz and 48 mhz parts and optimize accordingly. i specified the > different clock signals in SCOPE, but i still get the same warnings in > the log file that some nets don't make the 48 mhz timing window (even > though the nets are in the 12 mhz section). if i had to declare all > the false or multicycle paths, it would kill me because there are so > many. i was wondering if anyone has success in getting synplicity to > recognize the different clock domains and optimize according to those > frequencies. > another thing is that i have a receive clock (RxClk) at 12 mhz which > is derived from the incoming signal, and that clock has a lot of skew > with my internal 12 mhz clock which it needs to be in phase with. is > there a way to limit this clock to clock skew? > and finally, in synplify i cannot simulate two separate module > netlists at the same time. there is overlap between the modules it > creates (ie: LUT3_2 or something like that) and it causes Verilog-XL > to choke. does anyone know how to get around this problem? i have > heard about the modular design option in synplify and am considering > it. > lastly, is it possible to place and route a design module by module? > since i can get the pieces working but not the whole, i would like to > PAR the pieces and then glue them together to make the whole. > thanks for all the previous help. sorry this message is so long. > chris -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32773
I will follow up to Rick's post under a new thread name. This new thread has little to do with Marco's original posting. -- Bob Elkind, eteam fpga/design consulting Rick Collins wrote: > Marco wrote: > > > > Hello everybody, > > > > i am developing with an ACEX EP1K30. > > My question: Do anybody know the best configuration device for that device? > > i only know the EPC1 and EPC2. Are there some form other manufacturers ? > > > > Have anyone some schematics with the ACEX ???? > > > > Thank you very much. > > > > Best regards > > > > Marco > > You may find other problems in using this part unrelated to the > hardware. We are working with the 10K parts on an existing board. We are > trying to do a design with an 80 MHz clock where a portion of the > circuit uses multiple clock cycles to process signals through > combinatorial logic. It would appear that the MaxPlus II tools so not > well support this type of design timing. > > The tool problems we have found are numerous. It is a bit like being in > a maze and finding every path blocked. Our final approach is to simply > constrain the entire design to 80 MHz, and manually examine all of the > failure reports. The failures on single clock paths are fixed. The > failures on multi-cycle paths are ignored. This is not fun as the > failing paths change on each iteration of place and route. We call this > the "whack-a-mole" approach. As you fix paths, other paths then fail. > Once you have a working design, any change makes more moles pop up. > > One pleasant note is that the next release of the Quartus tool is > supposed to support the 10K series. Quartus II has much better > multi-cycle support. I don't know if they intend to support the 1K ACEX > parts with Quartus II. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 32774
Hello. I have extra Xilinx PCI development systems which consist of hardware and software for sale. It's still new and wrapped in the package. Come and check it out at ebay.com, just type "xilinx pci" in the search box. Or, if you want it now, I can let it go for $300 It's worth $695 retail. Made by www.vcc.com Thanks. ps. if pictures needed, let me know.
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