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In article <3B79C344.682A@designtools.co.nz>, Jim Granville <jim.granville@designtools.co.nz> wrote: > Eric Inazaki wrote: > > > > I have a PLD circuit which requires a clock signal. I'm thinking it'd > > be really nice if I could use some of the otherwise unused gates (along > > with a cap and a couple of resistors) to generate the clock. > > Is this a bad idea, doomed to failure or is this sort of thing done all the > > time? > > Somewhere in-between :-) I'm looking to do something in the few to few-tens of kHz. Would you consider that to be at the low end of the scale? The circuit I have in mind has an inverter whose output is the clk signal. This output also feeds a resistor (R1). The other end of R1 is connected to a cap (C) and another resistor (R2). The other end of R2 goes to the input of a buffer. The buffer's output, the inverter's input and the other leg of C are all tied together. (I know, pictures would be a big help.) BTW, is this what you mean by 3 terminal design? > > Low Frequency RC oscillators, of 2/3 terminal design, are impractical > in > CPLD due to lack of pin hysteresis. Ouch, that could be a problem. I should go look through my data sheets. I don't suppose there are any PLDs that have Schmitt trigger inputs (either configurable, or hard wired)? > For low Freq sources, we use HEF4541, available in SO14. > For medium Freq, a TinyLogic single gate makes a good osc source. > You can quite safely build a 3 terminal OSC, (for higher precision), > using an external TinyLogic gate and a PLD 'gate'. > > These solutions also keep the Icc down. > For my purposes, if I can't do the PLD thing I'll probably just break out a 555. I only need 2kHz or so and accuracy and stability are pretty much non-issues (or so I hope). > At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal > osc, with care. You need to do your own margin testing. > > Better may be to removce the R's and C's entirely: > > We have designed completely buried oscillators in the ATMEL > ATF150X family of cpld, using a chain of foldbacks. > Any chance you could point me towards an app note, text reference or sample circuits? > > > With respect to timing circuits in general, can PLDs be used in > > place of discreet logic gates? > > If you mean RC timing, like 4528, 4093, 40106, HC14, then no. > If you mean counter chains, like 4060/4040 then yes. > > I'm thinking either a delayed monostable or a straight delay. The delay and pulse width would be on the order of few to tens of microseconds. > ======= 80x51 Tools & PLD IP Specialists ========= > = http://www.DesignTools.co.nz Thanks for all the input, you've given me quite a bit to chew on. I've actually just started doing things w/ PLDs. PLDs rock, especially these isp types. ericArticle: 34126
Dear All,
After I have successful installed the Xilinx ( the computer told me), I
checked the size of the xilinx folder, it just has about 90MB!! I have
clicked all the things but still small size. Is that having any problem
here??
Thanks a lot
Article: 34127Hi, Does anyone know where Xilinx hide their pin lists, in text format (not pdf) on their web site? I've given up trying to battle the various search engines. Ta, Allan.Article: 34128
I've been thinking about the i/o interface obstacle that exists between cpu and pci-bus mediated fpga accelerators for a couple of days now. I have come to the conclusion that the way to have *really* fast fpga accelerators is to put a hardwired cpu on the fpga chip along with the accelerator logic and make the entire application run directly from the fpga. You now can get fpgas with ARM, Powerpc and or other custom cpus preprogrammed into them and still have lots of room for your accelerator logic. IP cores for almost every commonly used peripheral are available to be incorporated onto the fpga chip - leave off the interfaces you don't need. Put the whole thing on a PCI card and plug it into your pc to make development easier(download through the pci bus). "Mike Butts" <mbutts@realizer.com> wrote in message news:3B758FB0.B98CA76A@realizer.com... > Dave Feustel wrote: > > The real short version is > > that the PCI bus interface is so slow relative to the > > speeds of the cpu and accelerator that it usually > > isn't worth adding an accelerator if the interface > > is via the PCI bus. > > This is often, but not necessarily true. Accelerator architecture > totally depends on your application. This is exactly what Philip > meant by "how long should a piece of string be". Not ridicule, > just maybe a little drier wit than we're used to... > > If your application depends on lots of back-and-forth > between the host and the card in its core kernel, PCI is usually > a barrier. Many early research projects in this field found this > out the hard way. It's not the bandwidth that matters in such > cases, it's the latency, the round-trip time for a single operation. > > PCI, especially as implemented in modern PCs and workstations, > can be very bad at that. Mark Shand gave an excellent and > most useful paper about this at FCCM '97, that anyone using PCI > must study: > Laurent Moll and Mark Shand. Systems performance measurement on > PCI Pamette. In FPGAs for Custom Computing Machines > (FCCM'97). IEEE, April 1997. > http://www.research.compaq.com/SRC/staff/shand/bib.html > > If, on the other hand, your app is a self-contained kernel that > grinds away mostly on its own, PCI can be fine. Often signal > processing apps are like this, with the signal I/O direct to > the card. > > I believe a very big win for reconfigurable computing is for > apps that demand lots of parallel memory bandwidth, since the > processor-memory bottleneck is so fundamental to conventional > computing. I'm working with a project at Oregon Graduate Institute > lately to develop a neural network accelerator. In our case, it's all > about memory bandwidth. I/O to/from the host is orders of > magnitude less. We're planning a PCI card with as many SDRAM DIMMs > as we can hook up to some FPGAs for them to grind away on matrix- > vector multiplies in parallel at 100 MHz. PCI will just control > and program the card, and feed inputs and collect results at a > lazy and latency-insensitive pace. > > So tell us more about your application, and maybe we can give you > better advice. > > --MikeArticle: 34129
hamish@cloud.net.au wrote: > > Rick Collins <spamgoeshere4@yahoo.com> wrote: > > Clearcase also makes it hard to do some things such as using labels to > > track builds. > > Really? Just an extra line in the config spec for your view. > I agree with Allan.. ClearCase is overkill for most FPGA work (it > excels for the software engineers), but it's nice overkill to have. > With project teams of 2-7 FPGA engineers, we use labels and branches > with good effect. We don't usually need to do much merging though. > The GUI integration is IMHO really good, but you do have to use > the command line for non-day-to-day stuff. Accessing the label is not the problem. It is a chore creating a new label. It takes some 10 or 12 steps to add a new label and that is only if you have a current view that exactly matches what you want to label. In our build process we have to check out about 8 files BEFORE we create the label. If you forget to check out a file before you make the label, you have to remember to move the label to the new version. We have seen many, many mistakes made trying to make a new label which defeats the purpose of using these labels. Don't think that branches and labels are unique to Clearcase. We were using branches and labels 10 years ago with PVCS and they were not new then. > The original poster said he had design components which depended on > shared sub-components, and that different components might use different > versions of the same sub-components. I'm not sure how any version control > system would cope with that; you can only expect to see one version of > any particular entity at one time. I might even go so far as to say > that it sounds like a bad idea to need this feature. I think this statement shows the influence that Clearcase has had on your thinking about how version control should work. I see the requirement of different modules needing to access different submodule versions as being one of label control. The way Clearcase handles it, you can only access one version at a time, but with labels in PVCS, you can refer to one version for this component and a different version for a different component. Of course, you can't have both versions available at the same instant in time. But if your tool can compile the components separately and then combine the results, you should be able to support this unusual means of version control. You just need to perform "get" on a particular version as you need it, then discard the file before (or as) you "get" the next version. I just happened to find an unused copy of PVCS today. I expect I will be installing it and giving it a try to see how it stacks up to Clearcase. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 34130
We are working on a design in an XC4000 about 64K gates and are having a problem with register replication. The P$R tool is replicating a FF that is the critical element of a cross clock domain synchronizer. I call this a "bad thing". We looked at the Xilinx web site and found Answer #3813. This says that PAR can split a net and duplicate the FF driving it. Of course this will break a synchronizer, they even mention this. The solution is to use an environment variable to control this feature. This seems like a very odd way to control the PAR tool! Is there no option that can be set for this??? Has anyone else been bitten by this "issue"? Any other solutions? I don't really understand why PAR wants to split this net. The synchronizer consists of two FFs on the same clock with an AND gate detecting the two FFs being of different values to generate a single clock wide pulse. The first FF output feeds only three inputs, yet this is the net that was split. Anyone understand why this is happening? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 34131
hamish@cloud.net.au wrote:
>
> Thomas Stanka <Thomas.Stanka@de.bosch.com> wrote:
> > And its no problem to use multiple versions in different directories
>
> Then are they really the same file? Or are they separate copies of
> a file which was once the same file?
Maybe I miss your question, of course, they are separate copies.
/dir1/file
/dir2/file
where file in dir1 is another version than in dir2. You have no need, to
handle one of the files spezial in any case. While editing an older
file, you get automatically a branch.
> > The only problem I see is to have multiple versions of the same file in
> > the same directory.
>
> Yes. As Allan points out, you can do that in ClearCase by using
> the full pathname to the version. And that works with labels too,
> which is quite neat. I'd still rather not have to use it though.
In that case the files differ in their names, right ?
I don't dare thinking about handling different filenames for the same
files with our tools.
bye Thomas
--
Thomas Stanka
Bosch SatCom GmbH UC_RA/EMD4 s/UC-RA/BC
Gerberstr. 49 Tel. +49 7191 930-1690
Zi. 10/528 Fax. +49 7191 930-21690
Thomas.Stanka@de.bosch.com
Article: 34132On Wed, 15 Aug 2001 02:34:58 -0400, Rick Collins <spamgoeshere4@yahoo.com> wrote: >hamish@cloud.net.au wrote: >> >> Rick Collins <spamgoeshere4@yahoo.com> wrote: >> > Clearcase also makes it hard to do some things such as using labels to >> > track builds. >> >> Really? Just an extra line in the config spec for your view. >> I agree with Allan.. ClearCase is overkill for most FPGA work (it >> excels for the software engineers), but it's nice overkill to have. >> With project teams of 2-7 FPGA engineers, we use labels and branches >> with good effect. We don't usually need to do much merging though. >> The GUI integration is IMHO really good, but you do have to use >> the command line for non-day-to-day stuff. > >Accessing the label is not the problem. It is a chore creating a new >label. It takes some 10 or 12 steps to add a new label and that is only >if you have a current view that exactly matches what you want to label. >In our build process we have to check out about 8 files BEFORE we create >the label. If you forget to check out a file before you make the label, >you have to remember to move the label to the new version. We have seen >many, many mistakes made trying to make a new label which defeats the >purpose of using these labels. > >Don't think that branches and labels are unique to Clearcase. We were >using branches and labels 10 years ago with PVCS and they were not new >then. > > >> The original poster said he had design components which depended on >> shared sub-components, and that different components might use different >> versions of the same sub-components. I'm not sure how any version control >> system would cope with that; you can only expect to see one version of >> any particular entity at one time. I might even go so far as to say >> that it sounds like a bad idea to need this feature. > >I think this statement shows the influence that Clearcase has had on >your thinking about how version control should work. I see the >requirement of different modules needing to access different submodule >versions as being one of label control. The way Clearcase handles it, >you can only access one version at a time Rick, Clearcase does what you describe here: > but with labels in PVCS, you >can refer to one version for this component and a different version for >a different component. Of course, you can't have both versions available >at the same instant in time. But if your tool can compile the components >separately and then combine the results, you should be able to support >this unusual means of version control. You just need to perform "get" on >a particular version as you need it, then discard the file before (or >as) you "get" the next version. The main difference is that you need to change your config spec between "gets", i.e. get file, change config spec, get (different version of) file. The setcs command allows you to change your config spec from a script, which allows you to automate the process. Earlier you said that you'd only had training in the GUI for Clearcase. The GUI only supports a subset of the available features. Bye, Allan.Article: 34133
Here it is:
http://www.xilinx.com/products/virtex/vpackages.htm
http://www.xilinx.com/products/virtex/vepackages.htm
http://www.xilinx.com/products/virtex/v2packages.htm
Philip
On Wed, 15 Aug 2001 04:51:15 GMT, allan_herriman.hates.spam@agilent.com (Allan
Herriman) wrote:
>Hi,
> Does anyone know where Xilinx hide their pin lists, in text format
>(not pdf) on their web site?
>
>I've given up trying to battle the various search engines.
>
>Ta,
>Allan.
Philip Freidin
Fliptronics
Article: 34134Hi Ali, Nallatech do various PCI based FPGA development boards. www.Nallatech.com regards, Robert -----Original Message----- From: aelmousa@yahoo.com (Ali) [mailto:aelmousa@yahoo.com] Posted At: 14 August 2001 11:57 Posted To: fpga Conversation: Development Boards for FPGA based Application Subject: Development Boards for FPGA based Application Hello All, I am looking for reasonably priced development boards that use FPGAs. The boards should be for application development and not for testing purposes. They should use the PCI bus interface in a PC. I am not interested in going into the details of programming the PCI interface if an FPGA is used for that purpose. It is preferable to have parts of the PCB board available for in-house circuit additions also. Memory subsytem is not very important on the board. Any help with knowledge of availability of such boards, vendor addresses, web pointers, prices etc will be greatly appreciated. Thank you. AliArticle: 34135
For that small frequency I would recommend 40106 ST hex inverter. You only need resistor between in and out an cap between input and gnd. Rest of the buffers You can tie in parallel so you can have more power on the output. This config works fine to approx. 1Mhz with 5V Vcc. And less number of components comparing with 555 design. Regards M. -- Veselic Mladen Laboratorija Sigma ECO Izenjering Eric Inazaki <penfold@deadbeat.edu> wrote in message news:140820012044292591%penfold@deadbeat.edu... > In article <3B79C344.682A@designtools.co.nz>, Jim Granville > <jim.granville@designtools.co.nz> wrote: > > > Eric Inazaki wrote: > > > > > > I have a PLD circuit which requires a clock signal. I'm thinking it'd > > > be really nice if I could use some of the otherwise unused gates (along > > > with a cap and a couple of resistors) to generate the clock. > > > Is this a bad idea, doomed to failure or is this sort of thing done all the > > > time? > > > > Somewhere in-between :-) > > I'm looking to do something in the few to few-tens of kHz. Would you > consider that to be at the low end of the scale? > > The circuit I have in mind has an inverter whose output is the clk > signal. This output also feeds a resistor (R1). The other end of > R1 is connected to a cap (C) and another resistor (R2). The other > end of R2 goes to the input of a buffer. The buffer's output, the > inverter's input and the other leg of C are all tied together. (I > know, pictures would be a big help.) BTW, is this what you mean by > 3 terminal design? > > > > > Low Frequency RC oscillators, of 2/3 terminal design, are impractical > > in > > CPLD due to lack of pin hysteresis. > > Ouch, that could be a problem. I should go look through my data sheets. > I don't suppose there are any PLDs that have Schmitt trigger inputs > (either configurable, or hard wired)? > > > For low Freq sources, we use HEF4541, available in SO14. > > For medium Freq, a TinyLogic single gate makes a good osc source. > > You can quite safely build a 3 terminal OSC, (for higher precision), > > using an external TinyLogic gate and a PLD 'gate'. > > > > These solutions also keep the Icc down. > > > > For my purposes, if I can't do the PLD thing I'll probably just break > out a 555. I only need 2kHz or so and accuracy and stability are pretty > much non-issues (or so I hope). > > > At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal > > osc, with care. You need to do your own margin testing. > > > > Better may be to removce the R's and C's entirely: > > > > We have designed completely buried oscillators in the ATMEL > > ATF150X family of cpld, using a chain of foldbacks. > > > > Any chance you could point me towards an app note, text reference > or sample circuits? > > > > > > With respect to timing circuits in general, can PLDs be used in > > > place of discreet logic gates? > > > > If you mean RC timing, like 4528, 4093, 40106, HC14, then no. > > If you mean counter chains, like 4060/4040 then yes. > > > > > > I'm thinking either a delayed monostable or a straight delay. > The delay and pulse width would be on the order of few to tens > of microseconds. > > > ======= 80x51 Tools & PLD IP Specialists ========= > > = http://www.DesignTools.co.nz > > Thanks for all the input, you've given me quite a bit to chew on. > I've actually just started doing things w/ PLDs. PLDs rock, especially > these isp types. > > ericArticle: 34136
Hi, I am working with an Actel FPGA, a A54SX32A, however the question interests me whatever brand of FPGA. I am wondering if there is a certain hysteresis behaviour on an FPGA buffer ? Is it an information I can find in the datasheet (I looked but did not find) ? If I consider different IO standards (LVTTL, PCI are the two available) can I expect a change concerning the hysteresis ? Thank you, J.F.Article: 34137
Thanks Philip. Silly me, I was looking in the databook section and the packaging section of the web page. Bye, Allan. On Wed, 15 Aug 2001 01:05:43 -0700, Philip Freidin <philip@fliptronics.com> wrote: >Here it is: > > http://www.xilinx.com/products/virtex/vpackages.htm > > http://www.xilinx.com/products/virtex/vepackages.htm > > http://www.xilinx.com/products/virtex/v2packages.htm > >Philip > > >On Wed, 15 Aug 2001 04:51:15 GMT, allan_herriman.hates.spam@agilent.com (Allan >Herriman) wrote: >>Hi, >> Does anyone know where Xilinx hide their pin lists, in text format >>(not pdf) on their web site? >> >>I've given up trying to battle the various search engines. >> >>Ta, >>Allan. > >Philip Freidin >FliptronicsArticle: 34138
I just downloaded v2000efg1156.txt, and it seems to have an error. The "package name" column has the following values: ------ VCCO_7 VCCO_0 D5 B4 F7 GND This has the package names for the IO pins, but it has the supply name for the supply pins. I expected it to match the pin names, as in: "U11" instead of "VCCO_7" Anyone know why this is? (I ended up cutting and pasting from the PDF anyway.) Thanks, Allan. On Wed, 15 Aug 2001 09:47:11 GMT, allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote: >Thanks Philip. > >Silly me, I was looking in the databook section and the packaging >section of the web page. > >Bye, >Allan. > >On Wed, 15 Aug 2001 01:05:43 -0700, Philip Freidin ><philip@fliptronics.com> wrote: >>Here it is: >> >> http://www.xilinx.com/products/virtex/vpackages.htm >> >> http://www.xilinx.com/products/virtex/vepackages.htm >> >> http://www.xilinx.com/products/virtex/v2packages.htm >> >>Philip >> >> >>On Wed, 15 Aug 2001 04:51:15 GMT, allan_herriman.hates.spam@agilent.com (Allan >>Herriman) wrote: >>>Hi, >>> Does anyone know where Xilinx hide their pin lists, in text format >>>(not pdf) on their web site? >>> >>>I've given up trying to battle the various search engines. >>> >>>Ta, >>>Allan. >> >>Philip Freidin >>Fliptronics >Article: 34139
Eric Inazaki wrote: > > In article <3B79C344.682A@designtools.co.nz>, Jim Granville > <jim.granville@designtools.co.nz> wrote: > > I'm looking to do something in the few to few-tens of kHz. Would you > consider that to be at the low end of the scale? > > The circuit I have in mind has an inverter whose output is the clk > signal. This output also feeds a resistor (R1). The other end of > R1 is connected to a cap (C) and another resistor (R2). The other > end of R2 goes to the input of a buffer. The buffer's output, the > inverter's input and the other leg of C are all tied together. (I > know, pictures would be a big help.) BTW, is this what you mean by > 3 terminal design? Yes. When building this from non Hyst elements, the NonInverter (CAP) stage should go first, then the inverter (Resistor) stage. That way, regenerative feedback comes first, then the slower RC -ve feedback can come later. > > For low Freq sources, we use HEF4541, available in SO14. > > For medium Freq, a TinyLogic single gate makes a good osc source. > > You can quite safely build a 3 terminal OSC, (for higher precision), > > using an external TinyLogic gate and a PLD 'gate'. > > > > These solutions also keep the Icc down. > > > > For my purposes, if I can't do the PLD thing I'll probably just break > out a 555. I only need 2kHz or so and accuracy and stability are pretty > much non-issues (or so I hope). CMOS 555's are also a good solution - higher Icc than a 4541/40106, but fewer pins.. > > > At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal > > osc, with care. You need to do your own margin testing. > > > > Better may be to removce the R's and C's entirely: > > > > We have designed completely buried oscillators in the ATMEL > > ATF150X family of cpld, using a chain of foldbacks. > > > > Any chance you could point me towards an app note, text reference > or sample circuits? I've put an example on our web: http://www.designtools.co.nz/lcd32ser.zip This is a LCD serial interface driver, and has a chain of foldbacks as a delay line, used for a Latch+XOR to drive a LCD backplane, using a ATF1502ASL. > > > > > > With respect to timing circuits in general, can PLDs be used in > > > place of discreet logic gates? > > > > If you mean RC timing, like 4528, 4093, 40106, HC14, then no. > > If you mean counter chains, like 4060/4040 then yes. > > > > > > I'm thinking either a delayed monostable or a straight delay. > The delay and pulse width would be on the order of few to tens > of microseconds. For this scale, consider a monostable-counter, using the buried Foldback OSC, and a triggered saturating counter - you'll get zero external components, and a time resolution of ~166nS - jgArticle: 34140
I'm just a newbie here and would like to know which FPGA would be best suited for reconfigurable computing in terms of logic units, speed of reconfigurability, etc. Any help would be appreciated. Thanks Jason H. MorrisArticle: 34141
Program Announced
Early Registration Closing
Last Call for Papers
2001 MAPLD International Conference
JHU/APL - Laurel, Maryland
September 11-13, 2001
Note new addresses: mapld2001@klabs.org
http://www.klabs.org
The 4th annual Military and Aerospace Applications of Programmable
Devices and Technologies International Conference will address devices,
technologies, usage, reliability, fault tolerance, radiation
susceptibility, and applications of programmable devices and adaptive
computing systems in military and aerospace systems.
The program, abstracts, and registration information can be accessed at:
http://klabs.org/richcontent/MAPLDCon01/MAPLDCon01.html
Early registration for the Conference closes August 24th, 2001.
Late registration will open on the 25th, either on-line or at
the door.
This year's Conference will also include papers and an emphasis on
CPU design, logic design, and device reliability/fault tolerance.
The program will consist of oral and poster technical presentations
and industrial exhibits. This conference is open to US and foreign
participation and is unclassified. Select papers will be published
in the AIAA Journal of Spacecraft and Rockets.
Late news papers will be accepted for the Poster Session, space
permitting.
MAPLD will present two tutorials/seminars:
1. Programmable Logic Devices and Architectures
2. Advanced Design: Designing for Reliability
Invited Talks:
Major General Willie B. Nance, Jr., United States Army
Keynote Address
National Missile Defense Program Executive Officer;
System Program Director for the Ballistic Missile Defense
Organization
Dr. David A. Bearden, The Aerospace Corporation
"When is A Satellite Mission Too Fast and Too Cheap?"
Dr. Roger D. Launius, Chief Historian
National Aeronautics and Space Administration
Dr. James E. Tomayko, Carnegie Mellon University
Invited History Talk
"From Sequencers to Processors on Early U.S. Spacecraft"
Dr. C. Dianne Martin, The George Washington University
Invited Ethics Talk
"Recipe for Disaster: Engineering without Ethics
Dr. Don Bouldin, University of Tennessee
"Platform System-on-Chip Design"
Dr. Steve Guccione, Xilinx Corporation
"FPGAs for Fault Tolerant Circuits"
Eric Sundberg, National Reconnaissance Office
Invited AIAA Talk
Technical Sessions:
A. Applications: Military and Aerospace
Session Chair: Ralph Kohler - Air Force Research Laboratory
B. Design 1: Processors, Logic, and Programmable Devices
Session Chair: Rich Katz - NASA Goddard Space Flight Center
C. Reliability: Devices and The Effects of the Radiation
Environment
Session Chairs: Dr. James W. Howard, Jr. - Jackson and Tull
Ken LaBel - NASA Goddard Space Flight Center
D. Design 2: Systems
Session Chair: Hans Tiggeler - University of Surrey
E. Design 3: Fault Tolerance
Session Chair: John McHenry - National Security Agency
P. Poster Session
Session Chair: David Hepner - US Army Research Laboratory
Panel Session:
Design and Analysis vs. Test and Verification
A Discussion of the Technical, Programmatic, and Ethical Issues
in Military & Aerospace Systems
The conference is sponsored by:
NASA Goddard Space Flight Center
JHU/Applied Physics Laboratory
National Security Agency
Electronics Radiation Characterization Project
Digital Engineering Institute
Military & Aerospace Programmable Logic Users Group
American Institute of Aeronautics and Astronautics
IEEE Aerospace & Electronic Systems Society (AESS)
Air Force Research Labs
For further information, please see the conference www home page at:
http://www.klabs.org/richcontent/MAPLDCon01/MAPLDCon01.html
http://rk.gsfc.nasa.gov
Article: 34142Rick Collins <spamgoeshere4@yahoo.com> wrote: > versions as being one of label control. The way Clearcase handles it, > you can only access one version at a time, but with labels in PVCS, you > can refer to one version for this component and a different version for > a different component. Of course, you can't have both versions available > at the same instant in time. But if your tool can compile the components > separately and then combine the results, you should be able to support > this unusual means of version control. Well then of course you can do the same with ClearCase.. you can change your config spec, for a start. Or you can have multiple views; that might be even better, because then you can see multiple versions of the same file just by looking in different views (different drive letters). Or you can refer to the file as \path\to\file@@\main\branch\version etc. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 34143
I have a JEDEC file that identifies itself as a Signetics(Philips) PLHS18P8A and I need to know how I would convert that file back into logic equasions. It says it was generated by BP-1200/84/SM48D if that means anything to anyone... If there is any way to get the logic equasions out of this file please let me know. I dont have access to the origonal PAL chip from which the .jed file came.Article: 34144
Hello I want to design my own sound chip using Fpga. The aim is to build a chip able to play in hardware standard sound format as MP3, WAV... and emulate AY and SID format. Is there some people interrested to help me in this project ?Article: 34145
In article <aa5d502.0108150556.2ceb06ba@posting.google.com>, jonwil@tpgi.com.au says... > It says it was generated by BP-1200/84/SM48D if that means anything to > anyone... I can't help with the logic equations, but I don't think this number is going to help. This number looks a lot like a BP Microsystems EPROM programmer. See (sorry for the split): http://www.bpmicro.com/web/Products.nsf/bf5c382ba7f803138625665a006e9bd 8/c7e74b488861a4ca86256a6c005b75f0!OpenDocument ---- KeithArticle: 34146
Hi; I have a question regarding the DLL and clock to clock skew with Xilinx Virtex2 devices. I have two groups of logic which I want to run at different speeds. One group is at 33 MHz, and the clock net is driven without using a DLL (ibufg directly to bufg). This is defined in their PCI core. The other logic would benefit from running at a higher speed, but I want to avoid any metastability issues with crossing clock domains. My questions are as follows: Should I feed the DLL using the bufg output, or should I tap into the ibufg output? Secondly, will the software automatically account for any skew between the clock nets? In other words, will it make sure that setup/hold times are met when crossing from a register on the 33 MHz domain and the 33*n MHz domain? Or, do I have to somehow figure out what skew is and write an appropriate constraint? Finally, does it matter if I were using the 2x DLL output, as opposed to the frequency synthesis output? Thanks very much for reading! Cheers, JamieArticle: 34147
Eric Inazaki ha scritto nel messaggio <140820011643075782%penfold@deadbeat.edu>... >With respect to timing circuits in general, can PLDs be used in >place of discreet logic gates? In this particular case I'm using a >Lattice ispLSI1016E. In my esperience, yes. I did oscillators just with Lattice 1K and 2K CPLD series. You have to configure a macrocell as a simple inverter and connect the input and the output to two adjacent pins. Internally you connect the macrocell output to the clock lines. Externally, you connect input and output with a resistor and the input with a capacitor to ground. This works in a very wide frequency range, also shorting input and output directly and without any capacitor to obtain easily 100-200 MHz! Unfortunately this kind of oscillator is unreliable as it is unstable and sensitive to noise, so you have to use it with caution. LuigiArticle: 34148
Since your two clock frequencies are fundamentally phase-coherent, albeit perhaps with a certain unpredictable tolerance, you can cross the clock-domain boundary simply by using the opposite edge of the higher frequency clock. This does cut into your timing budget, but is safe otherwise. Peter Alfke
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