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where can I find a dispositivo hardware(FPGA,DSP......) that it implements a > function random(deve to produce numbers uniformly distributed among 0, 1) or > the method of runge kutta? > thanks > > > N.B: > excuse for my bad EnglishArticle: 34326
I am assuming you have need of the extra CLK2X180 output provided by the CLKDLLE - if this is the case, I can't help, but if you do not require this then the plain CLKDLL may be of use - sings, dances , jumps hoops in my sims, without trouble, straight from the box Fred Johnsonw10 <johnsonw10@hotmail.com> wrote in message news:13053c26.0108200716.69d95efa@posting.google.com... > According to Xilinx app. note 132, the feedback clock input of CLKDLLE > can be clk0 or clk2x. But in the functional simulations the CLKDLLE > doesn't work (all clock outputs remain 0's) if clk0 output is directly > connected to the clkfb input. Everything works fine if a bufg is > inserted between clk0 and clkfb. Does anybody know if this is just a > simulation issue or it is how clkdlle logic actualy works (clkfb input > has to be driven by a some form of bufg). I am using vcs and the > clkdlle.v model revision is 1.4.20.2. > > Thanks,Article: 34327
The problem is propably that your simulator does not have the right timing reolution. When you use modelsim try typing "vsim -t ps" and try again. Good luck.Article: 34328
Hi there! I'm pretty new at FPGAs, and what I'm trying to do is program an MP3 decoder into an FPGA.. Does anyone have experience at this? Are there VHDL or Handel-C mp3 decoder sources around? Or anyone wants to discuss this subject with me? :-)) thanks in advance! -Mark p.s. sorry for the cross-post, but I thought I'd best try both :-)Article: 34329
In article <S6ig7.986$ZN5.165455@newsread1.prod.itd.earthlink.net>, joey@sun.science.wayne.edu says... > - Most machines seem to use some sort of clock chip (often Cypress) running > off a 14.3 oscillator. Swapping that seems like it would certainly cause > problems for the computer (dram, video, etc), correct? I'm not in modern > motherboard design so I'm not sure what would happen. There were socket-7 boards that had a separate clock chip for the PCI with an asynchronous northbridge. These were intended to support the Cyrix processors with a 75MHz FSB. IIRC the SiS 5571, 5582, 5597, and 5598 as well as the Via VP2 chipsets supported this, though not all motherboards with these chipsets supported an async PCI. The MTech R534E/F/G motherboards had such a setup as well as a number of others. If you can find one of these antiques, you should be able to cut the PCI oscillator out and patch in another oscillator. ---- KeithArticle: 34330
Hi Mark, there's a demo design available from Altera that implements an MP3 decoder. It uses a 16-bit NIOS soft core processor together with some hardware acceleration to do the decoding. You might want to contact someone at Altera and ask whether you can get the demo design. I think it's not available off their public website. Furthermore, here at El Camino we've built a prototyping board that has an ALTERA ACEX 1K device together with some SRAM, FLASH, RS232, IDE and an audio chip - everything you need to implement MP3 hardware, with or without a NIOS processor. Check out http://www.elca.de/Products/prod%20d1kx208e.html if you need a hardware platform for you project. Regards Wolfgang Mark <m.smulders@philips.com> wrote in message news:3b822fb0$0$14118$4d4ebb8e@read-nat.news.nl.uu.net... > Hi there! > > I'm pretty new at FPGAs, and what I'm trying to do is > program an MP3 decoder into an FPGA.. > Does anyone have experience at this? > Are there VHDL or Handel-C mp3 decoder sources around? > Or anyone wants to discuss this subject with me? :-)) > > thanks in advance! > > -Mark > > p.s. sorry for the cross-post, but I thought I'd best try both :-) > > >Article: 34331
Alrite! thanks for answering my question :-)) At this point I'm going to use a board from Celoxica (has a Xilinx FPGA) pretty nice.. programming it in Handel-C... peace, - Mark "Wolfgang Loewer" <wolfgang.loewer@elca.de> wrote in message news:9ltprr$lfi$07$1@news.t-online.com... > Hi Mark, > > there's a demo design available from Altera that implements an MP3 decoder. > It uses a 16-bit NIOS soft core processor together with some hardware > acceleration to do the decoding. You might want to contact someone at Altera > and ask whether you can get the demo design. I think it's not available off > their public website. > > Furthermore, here at El Camino we've built a prototyping board that has an > ALTERA ACEX 1K device together with some SRAM, FLASH, RS232, IDE and an > audio chip - everything you need to implement MP3 hardware, with or without > a NIOS processor. > Check out http://www.elca.de/Products/prod%20d1kx208e.html if you need a > hardware platform for you project. > > Regards > Wolfgang > > > Mark <m.smulders@philips.com> wrote in message > news:3b822fb0$0$14118$4d4ebb8e@read-nat.news.nl.uu.net... > > Hi there! > > > > I'm pretty new at FPGAs, and what I'm trying to do is > > program an MP3 decoder into an FPGA.. > > Does anyone have experience at this? > > Are there VHDL or Handel-C mp3 decoder sources around? > > Or anyone wants to discuss this subject with me? :-)) > > > > thanks in advance! > > > > -Mark > > > > p.s. sorry for the cross-post, but I thought I'd best try both :-) > > > > > > > > >Article: 34332
Rick Filipkiewicz <rick@algor.co.uk> wrote in message news:<3B820B62.54174F87@algor.co.uk>... > I'm with Austin on this. It *is* possible to get a Virtex-E to meet 33MHz PCI > timing. I was in a similar position ~2.5 years ago when (1) I had to proto a PCI > i/f destined, ultimately, for an ASIC and (2) a bought in IP solution was not > acceptable to the client. Yes, I totally agree it could be done, but what I tried to mention in my previous post is that the PCI core itself is not the problem at all. The problem is the "rest of the chip". I'll continue below. > The basic trick I discovered (although I'm not claiming any originality) is to > strip the master/target core statemachines down to the absolute minimum and > "offline" everything that doesn't absolutely *have* to be driven direct out of > them [6/5 states resp.]. Only these core machines + the outgoing data pipe > control should use the raw, unregistered, PCI signals as inputs. I guess what I didn't explain well enough is that my critical paths don't involve the PCI block at all; they are in the gigantic data structures (fifos, etc) in the main design. The localbus clock is just a buffered 33mhz PCI clock. Timingan says my problem is is pushing signal through 20-25 levels of combinational logic that the asic folks expected would take half a cycle. Each CLB/LUT takes some time and it adds up when things are deep enough! Better yet, that report is when working with a single module which fits on a single fpga. There are actually tons more modules, so the entire chip is partitioned across several VirtexE 2k's. Just fixing some clock-enables or jumping a speedgrade can't get me the 30ns improvements on fields of combinational logic that I would need. Also one thing I might not have expressed clearly; the PCI is just a control interface. Other chip clocks would have to run even faster to work in the actual environment. I wrote off at-speed as a loss in the beginning. My main goal is to get it running at all. Now using a different PCI core could be a great idea to make this chip work; that way localbus clock would not have to equal PCI clock. If it were easy I'd jump on the idea, but the current IP is not well suited for that change. The goal is to prototype for test, not to rewrite the code and release an at-speed fpga. If my changes introduced or eliminated a bug, the whole test effort would have been useless. If it were an easy, for-sure bug-free change I'd do it; but on this design it's a major change and therefore not an option. I keep thinking that I would have been a lot more successful if I had picked a microprocessor or something where I could control the clock. This one looked simple at first, it turned out more like "it sounded like a good idea at the time"! Maybe the final answer is that we're just too cheap and need to buy that PCI slowdown card for $3k. Of course it always seems like there has to be some cheaper, easier way. Making a computer run slow has got to be easier than making it run fast! > One question I might ask is what Synth tool are you using ? We use Synplify. I think we've learned a lot doing this rather large chip. Using an Aptix system explorer, several VirtexE 2ks, evaluating Amplify physical optimizer, and evaluating Certify beta 5 with auto partitioning. Synplify Pro is great for many projects, but if you're doing a serious design you need their higher end tools. They really need to integrate Amplify and Certify though; right now they seem to be seperate products. The reason I say evaluating is because (don't laugh) I started the project using Synopsys dc_shell targeting the VirtexE libraries provided with Alliance. It sounds great since the asic guys already have the licenses. With dc_shell I got terrible results, and even some illegal EDIF output because of a problem with the Xilinx library. Wanted to give Synopsys a fair shake before jumping ship and take a look at fpga_compiler, but given a month and a half they couldn't get us an eval. My customer service experience with Synplicity has been a whole lot better. I'd love to keep the discussion going! Thanks for your thoughts everybody. -joeyArticle: 34333
> > The path through CLBs and routing to make an oscillator like that > shown should be long enough to keep the frequency relatively low, > compared to discrete logic. > > -- glen The LUT oscillator that I created had 25% of the chip running at .45ns(lut) + .5ns(route) or ~ 512Mhz and 75% of the chip running at .45ns + .9ns or ~ 740Mhz. That is a Virtex-II 1000 speed 4. This of course is by the book delays, which we have found actual routes to be 80% of the delay in the book(at nominal temp/voltage). Anyway, just FYI. I can't believe anyone would accidentally create this scenario, but I suppose that is what people thought as they were going down on the Titanic. BryanArticle: 34334
On Tue, 21 Aug 2001 10:41:04 +0100, "Tim" <tim@rockylogic.com.nospam.com> wrote: >"Mark Taylor" <101551.3434@compuserve.com> wrote in message >news:3b816b86.32685097@news.compuserve.com... > >> 1) Is the access time / CLOCK to DOUT time for the BRAMS faster when set >> for a wide data configuration? >> (ie presumably the output signals can skip 4 levels of multiplexers) > >Most likely you get the muxes (pretty fast pass-transistors?) anyway. > Yes but they will be mainly switched off ( and so not contributing much to delays) or switched on and contributing say 80 ps for 4 layers or less for fewer. Since the BRAMS are synchronous, they might go through a final layer of FFs. (in which case I am surprised that the Tbcko is so high, ~3ns on -6 grade) (if they do , then obviously the MUXES won't contribute at all to Tbcko) The probable difference is that for a NARROW Data width configuration, the setup time for some address lines (which only control the muxes) might be vey much less than that for other address lines (which have to go through the physical RAM as well). What I wanted to do was to have deliberately skewed clocks such that much of the fixed delays are effectively eliminated, but I wanted to be sure that the delays would not have appreciable skew between the data bits. There is also the issue of the net delays for routing, and whether these can be modelled as primarily TRANSPORT or INERTIAL. I want to aggressively maximise throughput, but not at the expense of unreliability. Look at the timing specs for the BRAMs. If you are just reading from them, then they can probably coast along at 250MHz+. The Tbcko + net delay +? +setup time might add 7nS for one path. If this were all transport delay, it would be possible to read imposing no limit on operating frequency. BUT if another path only took 1nS, then there would be a slight problem. There's a skew of 6nS, which at a clock rate of 166Mhz would mean that the pipeline would be completely screwed up. Fmax would probably be reduced to 80MHz or so.... This is a somewhat extreme case, but the difference between 80MHz & 250 MHz is enormous. So I need to know how severe these skews are. ( and no, I'm not asking for 250Mhz!) >> 11)The P&R tools seem to consider (single port) RAM address lines to be >> unswappable. >> Is there any way around this, because almost invariably I find that >> swapping (ie deleting net pins then adding net pins) >> the two highest net delay address inputs improves the timing on BOTH lines. > >Be grateful that these lines aren't swapped when used as SRL delay values... > > > > Actually that wouldn't matter, as long as I knew about it! I would use the SRL's as a convenient way of reprogramming the contents of a LUT. This would only be sensible where most of the bits change and where the update rate is less than a MHz, because 16 ~ is 16~. I would be mainly using RAM16s to update those LUTs where only 1 or 2 bits change, and where the update rate is higher. I can see that for complex cells integrating RAM with the multiplier AND's the scope for pin swapping is less, but would still be there. (just upper 2 bits and/or lower 2 bits) Even dual port is ok, as long as the F & G lines have equal swaps. So, the question is how do I automate the procedure of reducing the maximum net delays? (manually using FPGA_EDITOR is just not on ..)Article: 34335
bryan@srccomp.com (Bryan) writes: >> The path through CLBs and routing to make an oscillator like that >> shown should be long enough to keep the frequency relatively low, >> compared to discrete logic. >> >> -- glen >The LUT oscillator that I created had 25% of the chip running at >.45ns(lut) + .5ns(route) or ~ 512Mhz and 75% of the chip running at >.45ns + .9ns or >~ 740Mhz. That is a Virtex-II 1000 speed 4. This of course is by >the book delays, which we have found actual routes to be 80% of the >delay What is the maximum clock speed for Virtex-II, FF, through one LUT, to another FF? Can Virtex-II run a design where most of the logic runs at that clock speed? -- glenArticle: 34336
hello, How does a for loop executes the statements in AHDL .... for instance...: FOR i IN 0 to 21 GENERATE DATA.d = data_word[i]; lb_word[i] = data_word[i]; --assuming DATA is connected to LB END GENERATE; where... we have data_word[21..0] DFFE; lb_word[21..0] DFFE and DATA DFFE; so now on simulation lets say i provide data_word[] = (H"38CCAA") then wat should be the result in DATA n lb_word[] Also, does it have sequentially or concurrently..?? Thx Abhimanyu rastogiArticle: 34337
Hi, CPLD and FPGA are fascinating however I am having trouble getting basic info. I would like to build a board around one of these devices as a learning exercise. Were is a good place to start? ThanksArticle: 34338
Daniel Nilsson wrote: > > Hi. > I have an 3.3V OUTPUT from a xilinx xc9536 cpld that I sometimes need to > pull high to +12 volts (controlled from the cpld using 3.3V output), is > there any way of doing this (maybe series resistance to protect pin?), high > frequency square waves in the range 10 MHz are sometimes present on this > output. > > P.S. are there any better way of doing this? > > What I intend to do is generating an output (reset-pin) that can produce > nice 10 MHz logic signals that switch between 0 and 3.3V and sometimes goes > all the way up to 12V (to inactivate erase protection function of flash > eprom) > > / Daniel Nilsson, M.Sc.EE student, and EE hobbyist Suggestion: Use the same technique used by the programmer manufacturers, they use a series R, and parallel Cap You will need to check the used CPLD pin actually has a Vcc clamp diode, and if not, add one. Series R can be 1-10K region. Parallel Cap is 22pF-100pF region, and is needed to preserve edge rates -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 34339
Hi. I have an 3.3V OUTPUT from a xilinx xc9536 cpld that I sometimes need to pull high to +12 volts (controlled from the cpld using 3.3V output), is there any way of doing this (maybe series resistance to protect pin?), high frequency square waves in the range 10 MHz are sometimes present on this output. P.S. are there any better way of doing this? What I intend to do is generating an output (reset-pin) that can produce nice 10 MHz logic signals that switch between 0 and 3.3V and sometimes goes all the way up to 12V (to inactivate erase protection function of flash eprom) / Daniel Nilsson, M.Sc.EE student, and EE hobbyistArticle: 34340
> > them [6/5 states resp.]. Only these core machines + the outgoing data pipe > > control should use the raw, unregistered, PCI signals as inputs. > > Arnt all inputs defined as registered in the definition of PCI?? No. The use of some unregistered control signals is required. That would be PCI-X you may be thinking of.Article: 34341
At >300 MHz you are talkingabout tiny chunks of logic generating their own local clock. I built a frequency counter in XC4002XL three years ago, that resolved 420 MHz ( in the one flip-flop that matters). I am going for 1 GHz now, but not in a CLB flip-flop. Just for bragging rights. So it all depends... Peter Alfke, Xilinx Applications -------------------------------------------------------- glen herrmannsfeldt wrote: > bryan@srccomp.com (Bryan) writes: > > >> The path through CLBs and routing to make an oscillator like that > >> shown should be long enough to keep the frequency relatively low, > >> compared to discrete logic. > >> > >> -- glen > > >The LUT oscillator that I created had 25% of the chip running at > >.45ns(lut) + .5ns(route) or ~ 512Mhz and 75% of the chip running at > >.45ns + .9ns or > >~ 740Mhz. That is a Virtex-II 1000 speed 4. This of course is by > >the book delays, which we have found actual routes to be 80% of the > >delay > > What is the maximum clock speed for Virtex-II, FF, through one LUT, > to another FF? Can Virtex-II run a design where most of the logic > runs at that clock speed? > > -- glenArticle: 34342
On Mon, 20 Aug 2001 19:10:26 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: >Peter, > >On top of all the other useful stuff you contribute to CAF you have just answered a >long-standing (or burning ?) question of mine regarding the calibration of heat >sensing fingertips. Peter, my right forefinger is calibrated as follows: 50C - ok for infinite duration contact 52C - 10 seconds to pullaway 60C - 1 second to pullaway Interpolate linearly between points. Your digits may vary. We just got a cheap ($79) infrared temp sensor, which is cool (no pun, really) for scanning FPGAs on a board. John > >To go further and get another data point: Last summer I was wondering why our new >board wasn't doing anything from power-on. I, very briefly, put my finger on it & >came away with a large & painful blister that was still very sore 2 days later. > >Cause = BGA chip pinout mirrored (not by me I hasten to add). > >What temp do you think the package would have reached ?Article: 34343
On 21 Aug 2001 20:43:17 GMT, gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote: >What is the maximum clock speed for Virtex-II, FF, through one LUT, >to another FF? In a V-II , -5 speed grade, M3.3.08i speed files, with careful placement, about 666MHz . > Can Virtex-II run a design where most of the logic >runs at that clock speed? NO >-- glen --philip Philip Freidin FliptronicsArticle: 34344
There's lots of good info at www.optimagic.com
and you also might want to look at
http://www.fpga-faq.com/FAQ_Pages/0007_Device_type_comparisons.htm
Philip
On Tue, 21 Aug 2001 17:47:57 -0400, M Smith <m.f.smith@larc.nasa.gov> wrote:
>Hi,
>CPLD and FPGA are fascinating however I am having trouble getting basic
>info. I would like to build a board around one of these devices as a
>learning exercise. Were is a good place to start?
>Thanks
>
Philip Freidin
Fliptronics
Article: 34345
hi,
i am having trouble using JTAG...i have Virtex XCV300 board (VW-300
Virtual Workbench from VCC)...and when i try to download my design
.bit file thru JTAG onto the board...the JTAG PROGRAMMER crashed on
me. I put the JTAG chains which i believe for my board is as follow:
-------------- ---------------
TDI--| XCV300_BG352 |----| XC9536 |-----|
| mydesign.bit | | JED/BIT File? | |
|--------------| |---------------| |
|
|
TDO -------------------------------------------|
so where "JED/BIT File?", i try to specify the XC9536.bsd file...but
as soon as i do that...the JTAG Programmer crashes...
"The instruction at "0x5f40129c" referenced memory at "0x00000004".
The memory could not be read."
any idea how i can get around it? i tried BYPASSING that XC9536 as
well...but if i do that i get the message that says " The JTAG chain
has one or more devices that are of an undefined type." any input is
very much appreciated! Thanks!
--
" Great minds discuss ideas;
Average minds discuss events;
Small minds discuss people. "
~ Justin
Article: 34346IIRC, this should work: lb_word[]=data_word[] Do you really need DATA ? Abhimanyu Rastogi wrote: > > hello, > > How does a for loop executes the statements in AHDL .... > > for instance...: > > FOR i IN 0 to 21 GENERATE > DATA.d = data_word[i]; > lb_word[i] = data_word[i]; --assuming DATA is connected to LB > END GENERATE; > > where... we have data_word[21..0] DFFE; lb_word[21..0] DFFE and DATA DFFE; > > so now on simulation lets say i provide data_word[] = (H"38CCAA") then wat > should be the result in DATA n lb_word[] > > Also, does it have sequentially or concurrently..?? > > Thx > > Abhimanyu rastogi -- ___ ___ / /\ / /\ / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ /__/ / Victoria, Australia, Down-Under /__/\/\/ \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ \__\/ \__\/Article: 34347
use google to look thru the history of this group and comp.lang.vhdl M Smith wrote: > > Hi, > CPLD and FPGA are fascinating however I am having trouble getting basic > info. I would like to build a board around one of these devices as a > learning exercise. Were is a good place to start? > Thanks -- ___ ___ / /\ / /\ / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ /__/ / Victoria, Australia, Down-Under /__/\/\/ \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ \__\/ \__\/Article: 34348
I reviewed the book. It was quite interesting, I did not fully understand it untill I spoke with the authors. The focus is on picking a set of tools and libraries that work consistently with a style of verilog. -- James "Dave Feustel" <dfeustel1@home.com> wrote: >Anyone who has read or examined the book >_Principles of Verifiable RTL Design_ (2nd edition) >by Bening and Foster: > >Comments about the usefulness and or >relevance of the book to their work? > >Thanks. > > -.-. --.- -.-. --.- -.. . -. .---- -.. -.. -.- -..-. .-- -.... James M. Lee jml@jmlzone.com Verilog Instructor http://jmlzone.com Author "Verilog Quickstart" ISBN 0-7923-8515-2 -.-. --.- -.-. --.- -.. . -. .---- -.. -.. -.- -..-. .-- -....Article: 34349
Are there any significant differences between a logic emulated version (implemented in an FPGA) and an ASIC version. I could imagine that at least some timing differences should occure. Are these timing differences important? Are there any other differences? Can anybody tell practical experiences? Michael
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