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In article <35A29D88.CBDAF52D@netas.com.tr>, Utku Ozcan
<ozcan@netas.com.tr> writes
>To use in a chip, I had to design such a logic that
>had 2 vectors of input, say, a[1:0] and b[3:0], and
>one vector of output, say, c[3:0]. Design entry is Verilog.
>
[snip]
>
>1. Is it possible to put 6-bit input (a[1:0] + b[3:0] = 6 bits)
> and 4-bit output in 2 CLB's only?
>
No, at least not for an arbitrary function of the inputs. But unless
I've missed something, your functions map nicely into three CLBs:
______
b[3:0] ---| FMAP |---,
~~~~~~ \ ______
a[1:0] ----------------| HMAP |---- c[n]
~~~~~~
Three bits of this uses three CLBs, with three 4-input LUTs spare, two
of whch can be used for the fourth bit. There's still one LUT and two
flip-flops spare!
Bonne chance
Paul
--
Paul Walker 4Links phone/fax
paul@walker.demon.co.uk P O Box 816, Two Mile Ash +44 1908
http://www.walker.demon.co.uk Milton Keynes MK8 8NS, UK 566253
Article: 10976In article <35A2B4DE.C87D2056@algor.co.uk>, Rick Filipkiewicz <rick@algor.co.uk> writes >The problem with the M1.x ABL2EDIF is very bad. The only way around it is >to use the old path via the .pld file and let NGDBUILD create and XNF file. >Comparing the 2 approaches it's clear that the EDIF route can use 50% more >CLBs & run 1/3 slower for the same ABEL design. > >I discussed this with Xilinx earlier this year & found that (i) the >responsibility for fixing it was placed with DataIO and (ii) Xilinx intend >to abandon ABEL anyway. Thanks for confirming this and giving an alternative route. The crazy thing is when it takes an already optimised design and the (un-turn-off-able) optimiser then pessimises it! If we are going to have to move to VHDL, does there exist, or would there be some sort of market for, an Abel to VHDL converter? Paul -- Paul Walker 4Links phone/fax paul@walker.demon.co.uk P O Box 816, Two Mile Ash +44 1908 http://www.walker.demon.co.uk Milton Keynes MK8 8NS, UK 566253Article: 10977
In article <35A2BA54.8DF8216D@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> writes > >Have you sent this to Xilinx? Not this complete list, but I have had a great deal of help from the UK help desk on these and other problems. Most have been my own finger trouble, but the ones mentioned are such that I can sort them myself (with a load of extra work) or on which the help desk has concluded there is not really an answer. > The problem with the symbol editor turned out to be a hyphen in the signal name in the original schematic. This was accepted by the Schematic Editor, accepted by Create Macro, but rejected by Symbol Editor with a useless error message. >> Auto-Placement: >There are other controls over the PAR process that might help without >the handwork. You can set the options to spend more time in the >placement stage. >The default settings tend to get an adequate solution >for many designs without spending a lot of computer time. When you have >a tougher problem to solve, you need to tell the software to think about >it harder. > A very minimal set of options is provided, and the main one is to increase the effort made by both place *and* route. Given a good placement, the EPIC routing is very quick, so it seems a bit odd that the default is placement taking seconds and routing taking minutes. >> Upper and Lower Case: ... >> But the Schematic entry >> package that comes with Foundation insists that all signal names are >> upper case, regardless of what I type. I would, politely as I can, >> suggest to Xilinx that this is INCONSISTENT_AND_VERY_ANNOYING. > >I agree with this 100%. But I know what they will tell you. The M1 >software was written by Neocad on Unix platforms by Unix programmers. For a package put together from a load of diifferent manufacturers, Xilinx have done a remarkably good job of ironing out the inconsistencies. But this one really irks, and, as you say, there is a huge amount of work for Xilinx to fix it. > Thanks for the comments Paul -- Paul Walker 4Links phone/fax paul@walker.demon.co.uk P O Box 816, Two Mile Ash +44 1908 http://www.walker.demon.co.uk Milton Keynes MK8 8NS, UK 566253Article: 10978
Has anyone worked on behavioral modeling of SCSI components in the past?
I would be interested to hear from people who have implemented
initiator/target transactors and/or protocol analysis engines. I am
constructing a test environment for RTL SCSI blocks (to be developed in the
near future). Ideally, I would like to find a 3rd party protocol-checker
which I could plug into my simulation bus, as an additional ('independent')
verification of the RTL chunks. Does such a creature exist? Would anyone be
willing to share components of a previous/current project?
Regards,
Mike Lardner
Design Engineer,
Eurologic Systems Ltd.
Article: 10979>I discussed this with Xilinx earlier this year & found that (i) the >responsibility for fixing it was placed with DataIO and (ii) Xilinx intend >to abandon ABEL anyway. Data I/O is not renowned for taking responsibility for anything. I bought their Chiplab-48 programmer and within a year it was "obsolete"; in fact it turned out that all new device support had stopped on it at least a year or two before they stopped selling it. Eventually they closed their UK office and that was the end of all effective support anyway. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10980
In article <35A2513B.6350@com.nt>, Marc Boulais <marc_boulais@com.nt> writes: > Bob Myers wrote: > > > > I am routing a XC4052XL part, which is using 68% of CLBs. The last time > > I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. > > Are routes like this typical??? > > > > I am setting my clock period to 25 ns in the .ucf file, along with > > specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > > > > Any suggestions welcomed as to what I can do to reduce the length of > > place & route. > > > > Regards, > > Bob > > If your system is Win95 based, there is at least 6 patches that needs > to be applied to M1.4, one of them address a speed issue on Win95 > compared with NT system. All patches should be on Xilinx web site and > the one that address the speed issue is win95_m14.zip. > > Hope this help > > -- > > Marc Boulais N O R T E L Actually, I was running on a PII-266 box (128 mb ram, 6 Gb hard disk) using NT 4.0. I had installed a number of patches from the web site (such as core_nt12, spd_4kxl_m14, bann_nt3, gui_nt1, li_pc). I haven't checked the web site in the last two weeks, but I'll go looking there today to see if any new patches are available. What may be causing the problem is that the routing level was set to 5. I know that 3 is the minimum that's needed with this design before all nets are routed. Even then, the third pass was completed somewhere in day 3 or 4 of the 6 1/2 day route. In the meanwhile, I'm going to be giving my design to the local Avnet (Hamilton-Hallmark) group to see if they can determine what the cause of the lengthy routes might be. -BobArticle: 10981
Hello everybody,
I am puzzled by the behaviour of the VHDL simulator at Power up. We are
using Synario to design a Xilinx XC4010XL Fpga and then ModelSim to
simualte the design.
In the design a data bus is connected to a bidirectional buffer. The
output enable of the tree state buffer is dependent only on the inputs
of some pins and some combinatorial logic.
Right after powerup all the signals are undefined. I can drive the input
pins of the logic that controls the tree state buffer in the testbench
(cs <= '0';) as well as by forcing (Force -deposit cs 0) the signals to
a given value, thus disabling the driving to the bus.
On the other hand I cant do the same on the data bus. The simulator
seems to have a different point of view of what is on the bus.
In the testbench the first command for the bus is to set it to Z.
---------------------------------------------------------------------
TB : process
variable period : time := 30 ns;
--------------------------------------
begin
-- wait for 0 ns;
--------------------------------------
data_pin <= "ZZZZZZZZ";
cs <= '1';
wait for period;
Article: 10982In article <35A2B4DE.C87D2056@algor.co.uk>, Rick Filipkiewicz <rick@algor.co.uk> wrote: > The problem with the M1.x ABL2EDIF is very bad. The only way around it is > to use the old path via the .pld file and let NGDBUILD create and XNF file. > Comparing the 2 approaches it's clear that the EDIF route can use 50% more > CLBs & run 1/3 slower for the same ABEL design. > > I discussed this with Xilinx earlier this year & found that (i) the > responsibility for fixing it was placed with DataIO and (ii) Xilinx intend > to abandon ABEL anyway. > > If (ii) then how am I going to specify my state machines. ABEL's built in > state machine syntax is a much nicer way to define them than Foundation's > SM editor or VHDL > If you are using schematic entry and only using ABEL for your state machines, I suggest that you download the One-Hot State Machine library (free) from our website http://www.memecdesign.com/ It is a library of schematic symbols, each composed of simple flip flops or gates, that allow you to design One-Hot Alorithmic State Machines simply by wiring the appropriate symbols together. The beauty of this method is that there is no special compile step and that the completed schematic looks like a flowchart of your algorithm. We have libraries for Workview Office and Foundation as well as a user's guide. Rob Weinstein Memec Design Services rob_weinstein@memecdesignDOTcom > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 10983
Call for Papers
IEEE Design and Test of Computers
* * * DRAM Architecture and Testing * * *
Web Page: http://www.ee.ualberta.ca/ce/dramissue.html
Deadline: July 15, 1998
IEEE Design and Test of Computers seeks original manuscripts
describing applied research or practical experience with architectural
and testing aspects of DRAMs. The theme issue is scheduled to appear
in the first issue of 1999.
EMBEDDED MEMORIES
impact, developments, and experiences with embedded macrocells;
reconciling DRAM and logic requirements in a single process;
logic-enhanced DRAMs; processors-in-memories; DRAMs embedded in ASICs;
application-specific DRAMs (graphics, multimedia, communications, ...)
TECHNOLOGY AND STANDARDS
trends in storage cell technology; DRAM-specific processes; circuit
design methodology; fuse technology; packaging; reliability; failure
analysis; high-performance architectures; RAMBUS versus SLDRAM;
impact, developments, and experiences with standards; cache-enhanced
DRAMs
DESIGN
timing system design, timing calibration, synchronous versus
self-timed operation, pipelined design, static and dynamic redundancy,
noise control, error correcting codes, multilevel DRAM, future trends
REPAIR AND TEST
fault models, failure mechanisms, repair algorithms, built-in
self-repair, DRAM test design, design-for-testability, built-in
self-test, parallel test strategies, automatic test equipment, memory
interconnect test
For additional information, consult the web page or contact one of the
guest editors:
Bruce Cockburn, cockburn@ee.ualberta.ca
Fabrizio Lombardi, lombardi@cs.tamu.edu
Jackie Meyer, fmeyer@cs.tamu.edu
Article: 10984
Hello everybody,
I am puzzled by the behaviour of the VHDL simulator at Power up. We are
using Synario to design a Xilinx XC4010XL Fpga and then ModelSim to
simualte the design.
In the design a data bus is connected to a bidirectional buffer. The
output enable of the tree state buffer is dependent only on the inputs
of some pins and some combinatorial logic.
Right after powerup all the signals are undefined. I can drive the input
pins of the logic that controls the tree state buffer in the testbench
(cs <= '0';) as well as by forcing (Force -deposit cs 0) the signals to
a given value, thus disabling the driving to the bus.
On the other hand I cant do the same on the data bus. The simulator
seems to have a different point of view of what is on the bus.
In the testbench the first command for the bus is to set it to Z.
---------------------------------------------------------------------
TB : process
variable period : time := 30 ns;
--------------------------------------
begin
-- wait for 0 ns;
--------------------------------------
data_pin <= "ZZZZZZZZ";
cs <= '1';
wait for period;
. . .
wait; -- for ever
---------------------------------------------------------------------
After starting the simulation, the bus goes in the Z state, as
instructed in the testbench.
As soon as I force the signal on the bus (Force -deposit d0 1) I get as
a result on the bus still a Z, on the simualtor I see a glitch,
indicating that the simulator tried to set it to the value, but resolved
the signal to back to a Z.
What I dont understand is why. According to the resolution function of
the std_logic a value of 1 or 0 does win over a Z. OR better said a Z
can be only made if two Z resolve.
To make the simulation more fun, if I brutally force the data bus to the
values (Force -freeze d0 1), the simulation works properly. But I am
reluctant to use this solution, because the force freeze command
overwrites the value of the data bus regardles to the real value on the
bus, thus covering any other sources that might drive the bus with other
values.
What am I missing here is:
1) In what states are the signals in a simulator after loading the vhdl
description and the testbench, and before strating the simulation?
2) How do I properly initialize the values of the signals in the chip?
3) Should I only use the testbench and apply stimuli so long that the
chip falls in a "safe" state before starting a simulation or am I
allowed to force signals as to reach the "safe" state? *
4) How do you initialize a chip anyway?
* To question number 3 there is a gottcha. In the timing simulation I
have a situation where the simulator gets stuck in an infinte loop.
Reaching the maximum number of iteration on the same time step it issues
an error telling me that 5000 iteration where done, and politely asks me
to increase the number of iterations. Even increasing the number of
iteration to a prohibitive number does not resolve the situation. What
is going on here and how do I start investigating the problem.
Thanks for helping
Matija
Article: 10985Hi, Can anyone let me know the speed vs accuracy issues that crop up when modeling complex embedded systems. I am interested in the performance level with respect to speed vs accuracy. Basically how should processors, architectures and software be modeled. Any web sites / classic papers for this kind of stuff ?? Like I mentioned I am looking at the performance level (basically timing and not that much of functional details..) Thanks, Deepu -- ~~~~~~~~~~~~~ deepu@ece.vill.edu / deepu@computer.org ~~~~~~~~~~~~~ | Deepu Talla | If it is not necessary to change | | | it is necessary not to change ... | | Phone: (610)225-0243 (R) | | | (610)519-7371 (O) | whatever, whoever, wherever, whenever| ~~~~~~~~~~~~~~~~ http://www.ece.vill.edu/~deepu ~~~~~~~~~~~~~~~~~~~Article: 10986
Milostnik <milostnik@iskratel.si> wrote: : I am puzzled by the behaviour of the VHDL simulator at Power up. We are : using Synario to design a Xilinx XC4010XL Fpga and then ModelSim to : simualte the design. : In the design a data bus is connected to a bidirectional buffer. The : output enable of the tree state buffer is dependent only on the inputs : of some pins and some combinatorial logic. : Right after powerup all the signals are undefined. I can drive the input : pins of the logic that controls the tree state buffer in the testbench : (cs <= '0';) as well as by forcing (Force -deposit cs 0) the signals to : a given value, thus disabling the driving to the bus. : On the other hand I cant do the same on the data bus. The simulator : seems to have a different point of view of what is on the bus. : In the testbench the first command for the bus is to set it to Z. : --------------------------------------------------------------------- : TB : process : variable period : time := 30 ns; : -------------------------------------- : begin : -- wait for 0 ns; : -------------------------------------- : data_pin <= "ZZZZZZZZ"; : cs <= '1'; : wait for period; You don't give us all the details; however, I surmise that data_pin is multply driven or is an inout port. (Inout ports, even when undriven from below, contribute a driving value to the network.) My suspicion is that other drivers of data_pin are driving 'U's. Paul -- Paul Menchini | mench@mench.com | "Se tu sarai solo, Menchini & Associates | www.mench.com | tu sarai tutto tuo." P.O. Box 71767 | 919-479-1670[v] | -- Leonardo Da Vinci Durham, NC 27722-1767 | 919-479-1671[f] |Article: 10987
Milostnik <milostnik@iskratel.si> wrote: : * To question number 3 there is a gottcha. In the timing simulation I : have a situation where the simulator gets stuck in an infinte loop. : Reaching the maximum number of iteration on the same time step it issues : an error telling me that 5000 iteration where done, and politely asks me : to increase the number of iterations. Even increasing the number of : iteration to a prohibitive number does not resolve the situation. What : is going on here and how do I start investigating the problem. You apparently have a delta-delayed oscillator somewhere. Find the signals that are changing at this time and figure out why.... A very simple delta-delayed oscillator is: s <= not s; Paul -- Paul Menchini | mench@mench.com | "Se tu sarai solo, Menchini & Associates | www.mench.com | tu sarai tutto tuo." P.O. Box 71767 | 919-479-1670[v] | -- Leonardo Da Vinci Durham, NC 27722-1767 | 919-479-1671[f] |Article: 10988
Ed McCauley <edmccauley@bltinc.com> wrote: >If you want just the 1s and 0s, you want to turn on the "Produce ASCII >Configuration File" option in the configuration/configuration template. >What are you really trying to do? Sorry, but where did you found this option????? MarcusArticle: 10989
I don't know if you are familiar with stack architectures. Check out 'Stack Computers' by Phil Koopman on the WWW. Simon ------------------------------------------------------------------------------------ deepu@wavelet.ee.vill.edu (Deependra Talla) wrote: > >Hi, > > Can anyone let me know the speed vs accuracy issues that crop up when >modeling complex embedded systems. I am interested in the performance level with >respect to speed vs accuracy. Basically how should processors, architectures and >software be modeled. Any web sites / classic papers for this kind of stuff ?? >Like I mentioned I am looking at the performance level (basically timing and >not that much of functional details..) > >Thanks, >Deepu >-- >~~~~~~~~~~~~~ deepu@ece.vill.edu / deepu@computer.org ~~~~~~~~~~~~~ >| Deepu Talla | If it is not necessary to change | >| | it is necessary not to change ... | >| Phone: (610)225-0243 (R) | | >| (610)519-7371 (O) | whatever, whoever, wherever, whenever| >~~~~~~~~~~~~~~~~ http://www.ece.vill.edu/~deepu ~~~~~~~~~~~~~~~~~~~ Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 10990
Sorry Marcus, I should have been more explicit: 1. Open Xilinx Design Manager 2. Select the pulldowns: Utilities --> Template Manager 3. Select the desired Familiy at the top of the dialog box 4. Select the "Configuration Templates" radio button 5. Select Edit... 6. The "Produce ASCII Configuration File" check box is at the bottom -- Ed McCauley President Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 Marcus Lankenau wrote: > > Ed McCauley <edmccauley@bltinc.com> wrote: > > >If you want just the 1s and 0s, you want to turn on the "Produce ASCII > >Configuration File" option in the configuration/configuration template. > >What are you really trying to do? > > Sorry, but where did you found this option????? > > MarcusArticle: 10991
On Wed, 8 Jul 1998 04:49:36 GMT, fliptron@netcom.com (Philip Freidin) wrote: >The weird assignment of the DOUT pin as a clock input is not unique to the >Spartan family. This "annoyance" permeates all the XC4000 families: > XC4000, 4KE, 4KL, 4KH, 4KD, 4KEX, 4KXL, and 4KXV, Spartan. > >This is the price of compatibility :-) Nope. Spartans have different pinouts. Thus Xilinx could have assigned DOUT to something other than SGCK4. (XCS40-PQ208 has 16 VCC pins, 4020E-HQ208 has only 8.) Allan.Article: 10992
The gate count depends on what device it will interface with. I think approximately 2k to 3k gate count for serial port with 8-bit addressing and 8-bit data type. In article <35A20EB2.A4F95297@email.sps.mot.com>, David Lin <r43475@email.sps.mot.com> wrote: > Greetings, > > I would like to apologize in advance if this is not the right place to > seek for assistance on this issue. > > I'm looking for some sort of information which could give me a rough > idea on how many gate counts will be required to implement the features > like serial port, parallel port, etc. as those legacy PC I/O devices so > I could estimate how big the chip will if I plan to integrate those > aforementioned functions into the design. > > Thanks in advance for your kindly help. > > Regards, > > David Lin > r43475@email.sps.mot.com > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 10993
In article <3592A5FB.A4146280@bradford.ac.uk>, ali Benkhalil <akbenkha@bradford.ac.uk> wrote: > > Hi, > > I am using the Altera HDL to perform a real-time motion detection > algorithms (Background Subtraction) for FLEX 10k device. Dose any one > have or know any AHDL code done simeler thing or is there any good > references, books, or papers on AHDL code. > > Thanks all, > > Khalil > e-mail: akbenkha@bradford.ac.uk > A new book is available in the market by name AHDL and VHDL. It is with me. If u want author,ISBN code reply to my email address:satish_me@hotmail.com by Satish Kumar,Scientist > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 10994
Utku Ozcan schrieb in Nachricht <35A29D88.CBDAF52D@netas.com.tr>... >To use in a chip, I had to design such a logic that >had 2 vectors of input, say, a[1:0] and b[3:0], and >one vector of output, say, c[3:0]. Design entry is Verilog. ..... snippp The "Programmable Logic Data Book" says: XC4000: "A CLB can be used to implement any two independent functions of up-to-four variables, or any single function of five variables, or any function of four variables together with some functions of five variables , or it can implement even some functions of up to nine variables." ManfredArticle: 10995
Hi I'm using a Xilinx 5215 coupled to a static RAM chip. The RAM data lines and address lines may be arbitrarily swapped around to improve routability, for example, it doesn't really matter if D2 is connected to D2 on the RAM, any unique data line will do. Using Foundation and schematic capture, is there any way to specify this so that the pins will automatically route in the simplest manner? Thanks -- Keith WoottenArticle: 10996
On Mon, 06 Jul 1998 07:36:20 GMT, "koh bongseok" <stonesys@chollian.net> wrote: >Hello. > >I want to download MAX+PLUS 8.1 for pc >please tell me where this program is located > >Thank you. > >mail me: stonesys@chollian.net > > Sincerelly, Victor Levandovsky PLD application instructor Technological University of Podillia Ukraine vic@NSalpha.podol.khmelnitskiy.ua remove@NS.for.email.meArticle: 10997
This is for all those hardware designers using FPGAs who are tired of waiting several hours (or days?) to compile large circuits: For my Master's thesis, I'm working on a high-speed routing tool that is capable of routing a 20,000 4-LUT circuit in 70 seconds. (on an architecture similar to the Xilinx 4000EX/XL) I would greatly appreciate it if you could take a few minutes to answer the following questions: Would you be interested in a tool that could place and route your BIG circuits (20,000 4-LUTs) in under 5 minutes? If you had to give up some quality (20% in circuit delay and/or 20% less device utilization than say Xilinx M1), would you still want to use such a tool? How much quality would you be willing to give up for high-speed place and route? How much would you be willing to pay for such a tool? (if it existed) Thanks in advance for your comments. Jordan Swartz Dept of Electrical and Computer Engineering University of Toronto http://www.eecg.toronto.edu/~jsswartz/Article: 10998
For all Synthesis tools, the coding style does affect the optimization of the result. Synthesis is not completely magic, the designer needs to have inmind the target design and device architecture, and write the code in a way that generates the design intended. -- James Utku Ozcan wrote: > > To use in a chip, I had to design such a logic that > had 2 vectors of input, say, a[1:0] and b[3:0], and > one vector of output, say, c[3:0]. Design entry is Verilog. > > I tried to model the logic in algorithmic level but > I couldn't do it. Therefore I have written a "function", > which includes a case, that defines the output for all > of the possible states of a[1:0] and b[3:0], respectively. > UDP-alike. > > I synthesized the approach above on XC4062XL and 6 CLB's > came out. I found this number too much. A colleague here > had designed a small software during his MSc which gives > 1st canonic expansions of several combinational logic > functions. The program tries to find common minterms. > I entered the output of this program and I obtained 7 CLB's!! > > 1. Is it possible to put 6-bit input (a[1:0] + b[3:0] = 6 bits) > and 4-bit output in 2 CLB's only? > > 2. Does coding technique play a dramatical role for optimizations? > I can't see any improving by partioning combinational > logic functions into small sub-functions. > > Synthesizer is Synplify. > > -- > - Vous me prenez pour l'oncle Picsou? > Utku Ozcan, http://www.ehb.itu.edu.tr/~utku/ -- -.-. --.- -.-. --.- -.. . -. .---- -.. -.. -.- -..-. .-- -.... James M. Lee jml@seva.com Seva Technologies, Expert EDA Services http://www.seva.com 200 Brown Road, Ste 103, Fremont, CA 94539 (510) 249-9085 Author "Verilog Quickstart" ISBN 0-7923-9927-7 -.-. --.- -.-. --.- -.. . -. .---- -.. -.. -.- -..-. .-- -....Article: 10999
On Wed, 08 Jul 1998 17:24:42 +0200, Milostnik <milostnik@iskratel.si> wrote: <snip> are you driving GSR from your testbench? from memory, the chip starts up in a combination of 'U's and 'Z's which can't be over-ridden until you've driven GSR. this doesn't just affect F/Fs - for instance, you can't get a signal through a clock buffer until you've done this. evan (ems@nospam.riverside-machines.com)
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