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We are doing that at the moment. Yes it is a pig !! The way we do it is by the use of 0.1" headers on the PCI card itself. This allows you to put the Analyser probes on to the signals directly. I would strongly advise you to stay clear of PCI Extender cards as these can mess up your timings. My $0.02 worth. dan wrote in message <360924FC.569E@cat-envisys.com>... >Andrew Phillips wrote: >> >> Hi, >> >> Trying to test some PCI cards - it's not easy to probe signals etc when >> the card is stuck inside a normal PC with other PCI cards alongside ... >> >> Anybody found a better prototype PCI card test system set-up - i.e. one >> that allows easy access to both sides of the card being tested? >> >> Thanks for any pointers ... >> >> Andy Phillips >> Supercomputing Systems AG >> Zurich, Switzerland > >Hi Andy, > >I have not had a need to do much card development lately, but when >I was building/testing ISA card regularly, I really liked the card >extenders that Digikey/Jameco and many others sell. These simply >raise the card in the slot above the height of the others. In fact, >the best arrangement came by simply chopping a slot in the side/top >of the case and surrounding it with nonconductive edge guards so the >case could be closed but my development slot was still accessible. >Simple... but it worked. > >I am sure that PCI extender cards are available somewhere. Check >Vector Electronics product line (Digikey is a distributer). > >Cheers, >DanArticle: 12001
If you have synthesizable VHDL for your design, you will re-sinthesize using an ASIC gate library instead of the Altera 10K20 FPGA library. However, "translating" is a different story. Translating means you are "mapping" equivalent gates from the FPGA library to the ASIC library. This is more difficult. I don't think it is possible to load an FPGA-based netlist in a synthesizer and then switch the library to optimize to another library (in your case switch to an ASIC library). In terms of timing, "mapping" means you (or a tool) are finding equivalent gates, inverters and flip-flops with the same drive, so timing will remain the same. However, timing depends also in the interconnect wiring between these gates, and you will have a different placement and routing in your ASIC. So this means that timing will change too. So the only way to find out if your design still works in the ASIC, after placing the netlist in the ASIC, is by simulating it again, with the new interconnect loads. Everybody says Accolade has a good tool for the money. It may be true. You can download their tool and test it yourself. John Huang wrote in message <6u8ue8$92b$1@news.seed.net.tw>... >Hello all: > I have a FPGA design in ALTERA 10K20, and now I want to >translate it into ASIC, would you tell me what is important about >translation? does timing will change? how to keep the result current? > >Thanks > John Huang > >Article: 12002
Dan's way is the first thing I would try, but be aware that some boards simply won't work on an extender. The extra capacatance and bus length puts them over the timing edge. Jerry -- If my address has "x" or "z" in it, remove them to reply. Never ascribe to malice what might be be ignorance, stupidity, or sloth. ------------------------------------------------------------------------ dan wrote: > > Andrew Phillips wrote: > > > > Hi, > > > > Trying to test some PCI cards - it's not easy to probe signals etc when > > the card is stuck inside a normal PC with other PCI cards alongside ... > > [snip] > > > > Andy Phillips > > Supercomputing Systems AG > > Zurich, Switzerland > > Hi Andy, > > I have not had a need to do much card development lately, but when > I was building/testing ISA card regularly, I really liked the card > extenders that Digikey/Jameco and many others sell. These simply > raise the card in the slot above the height of the others. In fact, > the best arrangement came by simply chopping a slot in the side/top > of the case and surrounding it with nonconductive edge guards so the > case could be closed but my development slot was still accessible. > Simple... but it worked. > > I am sure that PCI extender cards are available somewhere. Check > Vector Electronics product line (Digikey is a distributer). > > Cheers, > DanArticle: 12003
ems@nospam.riverside-machines.com writes: (snip) >quick thought: the micro writes the compare data stream into a fifo. >this gives you maximum density on the compare data. when you get a new >word into your device, just pop one word out of the fifo, and compare >it against your new input data - ie. you only need one comparator. >this is much more efficient for long compares. >the edge decoders probably wont give you a speed advantage, since you >still have to do something with your compare answer once you've got it >(and spartan doesn't have edge decoders anyway). In the cases I know, this won't work. That is, in general you don't know where the start is, but want to match wherever the data pattern appears in the data stream. A state machine, actually, a Deterministic Finite State Automaton, is a good way, depending on data width and length. -- glenArticle: 12004
"John Funnell" <j.funnell@dmv.co.uk> writes: >Hi, >I'm trying to think of an efficient implementation of an max-function that >finds the largest from 16 unsigned 8-bit numbers. The input format is not >specified (I decide parallel binary, serial LSB first, serial MSB first). >The max-function must signal which of its inputs was the largest and the >value of that input. What can I do to mimise FPGA area used and maintain a >continuous flow of input data? Is there anything clever I can do? 8 bit max can be done in 5 CLB. Program as a normal subtract circuit. The last CLB will have an unused FG. Use this to determine the sign of the result of the subtract. Feed this signla down to the unused input of the FG in the subtractor, and configure the LUT as mux logic. The greater/not greater is done by the carry logic alone. The LUT do the mux logic. I don't know that any synthesis or routing tools will figure this out. I hand coded it using LCAedit, and then use it as an RPM from verilog source. Home this helps, -- glenArticle: 12005
This is the same as a macro I use. Synthesis won't create this structure without alot of monkeying around. With schematics it works just fine with a few RLOCs and FMAPs. I have 2 bit min/max slice macro that has the FMAPs and RLOCs inside it (inverting the control signal as it comes out of the msb provides min or max). On the next level up, you put down as many of these as you need to get the desired width and put RLOCs on them to arrange the 2 bit macros in a column. You'll need a special macro at the top and bottom of the column. Using this technique, you can build carry chain circuits of arbitrary widths very quickly (use the array command in you schematic editor to do it even quicker) using a library of basic 1 and 2 bit macro slices. Since it is relatively pre-placed, it breezes through place and route too. I see no need to do it in LCAedit, seems like more work and harder to verify that way. You can take the schematic result and instantiate that if you want to use the structure under an HDL. glen herrmannsfeldt wrote: > 8 bit max can be done in 5 CLB. Program as a normal subtract circuit. > The last CLB will have an unused FG. Use this to determine the sign > of the result of the subtract. Feed this signla down to the unused input > of the FG in the subtractor, and configure the LUT as mux logic. > > The greater/not greater is done by the carry logic alone. The LUT do > the mux logic. I don't know that any synthesis or routing tools will > figure this out. I hand coded it using LCAedit, and then use it as an RPM > from verilog source. > > Home this helps, ^^^^ but does it help away from home too? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12006
We have several job opportunities in Phoenix (nice quite, no crime, low living cost city in Arizona) for ASIC/FPGA people at a $600 mil. IC design company. And we need CAD SW people as well. Position: Design engineer, will be responsible for the design and development of low power high speed products based upon embedded RISC and DSP cores. Requirements: BSEE, MSEE, (university degree) 2++ year experience (the more the better), English language skill. Pls. send your TXT resume as an EMAIL TXT only (pls do not send MS-WORD document). We provide US work visa for 4,8+ years. Laslo and Gary Gary N. Lang Vice President of ACD,Inc. E-mail: garynlang@aol.com http://www.acdcon.com/Article: 12007
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Article: 12008There are four ways to do what I believe you are trying to do. 1) buy a PCI bus analyzer from either VMETRO, HP or Catylist 2) Use an extender card that has a PCI bridge on it. This is the ONLY way to use an extender card and maintain the PCI spec....ANY extender card that DOES NOT have a bridge on it, violates the PCI spec. International Product Design offers one.... 3) Use a very well designed ACTIVE extender card. The best one out there is from UltraView, called PCIEXT64. 4) Use a PASSIVE extender card. There is one that is VERY short, and gives you probe points made by International Product Design. I believe all four of them are available from Twin Industries (800) 570 TWIN. URL: http://www.twinhunter.com/Products/T_PCI_Prod.htm No, I don't work for Twin, or any of the above companies, but I did help them (and others) design and test their extender cards. Choice 3 is a very good choice (I mostly use this exact same card) if you don't have $5k to spend on 1 (I have a VMetro too, but I really like to use the extender card for some reason...). Choice 2 can cause you 'some' problems if your system doesn't handle bridges well.... Austin Franklin darkroom@ix.netcom.com Andrew Phillips <andrew@scs.ch> wrote in article <36091AC3.C733E671@scs.ch>... > Hi, > > Trying to test some PCI cards - it's not easy to probe signals etc when > the card is stuck inside a normal PC with other PCI cards alongside ... > > Anybody found a better prototype PCI card test system set-up - i.e. one > that allows easy access to both sides of the card being tested? > > Thanks for any pointers ... > > Andy Phillips > Supercomputing Systems AG > Zurich, Switzerland >Article: 12009
I want to buy a FPGA tool, do you recommand which one is better, how about Accolade and Aldec? John HuangArticle: 12010
Andrew Phillips wrote: > Hi, > > Trying to test some PCI cards - it's not easy to probe signals etc when > the card is stuck inside a normal PC with other PCI cards alongside ... > > Anybody found a better prototype PCI card test system set-up - i.e. one > that allows easy access to both sides of the card being tested? > > Thanks for any pointers ... > > Andy Phillips > Supercomputing Systems AG > Zurich, Switzerland Hello ! When we gained our first experiences with PCI we used a prototype board from PLX technology. This board is a PCI to ISA bridge equipped with an PLX9050 PCI Target Interface Chip and contains test-points for all signals behind the PCI Interface. This board was very usefull for driver development. For monitoring the PCI-signals we used a PCI-Extender from CORELIS in conjunction with a HP Logic-Analyzer. CORELIS ships this extender with dedicated software for some of the HP analyzers. The software package contains a PCI-Bus disassemler which really simplifies debugging, because the PCI-actions are not only displayed as numbers but are decoded for you. Its also possible to filtrate PCI on interesting actions. R.Becker II.Physikalisches Institut University of Giessen 35392 GiessenArticle: 12011
I have used a HP PCI bus analyser with a 1660 logic analyser which I found very useful indeed. It uses an extender board into which the LA probes plug. The effect of this board on PCI timing may be slightly deleterious - I recommend a close reading of the PCI 2.1 spec and conservative design of the PCI interface on your board. You will live to regret cutting corners with PCI - don't do it ;-) ---- Dr Mike Addlesee The Olivetti & Oracle Research Laboratory Limited 24a Trumpington Street Cambridge CB2 1QA U.K.Article: 12012
> For monitoring the PCI-signals we used a PCI-Extender from CORELIS in > conjunction with a HP Logic-Analyzer. CORELIS > ships this extender with dedicated software for some of the HP analyzers. Be carefull using a product such as this 'PCI signal extender'. All the board is, is a PCI card with long cables (well, long in terms of a PCI bus that is) that allows direct attachment logic analyzer pods. It really makes a MESS of the PCI bus signal intregity, and as such, can add much more difficulty to your debugging task than you bargained for. AustinArticle: 12013
I am a newbie in vhdl-fpga. Does Anyone know free/shareware for fpga design? Thanx Adria BofillArticle: 12014
Try to use a series resistor. Its value should match the line impedance. Maybe you will find 120 Ohm useful. Regards ManfredArticle: 12015
Try Aldec, their new Active-VHDL 3.2 with Fast Direct Compile... Check it out at http://www.aldec.com/ Son Huynh John Huang wrote in message <6uctfk$ht4$1@news.seed.net.tw>... >I want to buy a FPGA tool, do you recommand which >one is better, how about Accolade and Aldec? > >John Huang > > >Article: 12016
C'mon Gary, NO CRIME? Rob Weinstein Memec Design Services - Phoenix rob_weinstein@memecdesignDOTcom In article <19980923204955.09176.00001033@ng141.aol.com>, garynlang@aol.com (Garynlang) wrote: > > We have several job opportunities in Phoenix > (nice quite, no crime, low living cost city in Arizona) > for ASIC/FPGA people at a $600 mil. IC design > company. And we need CAD SW people as well. > Position: Design engineer, will be responsible for the > design and development of low power high speed products > based upon embedded RISC and DSP cores. > Requirements: > BSEE, MSEE, (university degree) > 2++ year experience (the more the better), English language > skill. > Pls. send your TXT resume as an EMAIL TXT only > (pls do not send MS-WORD document). > We provide US work visa for 4,8+ years. > Laslo and Gary > > Gary N. Lang > Vice President of ACD,Inc. > E-mail: garynlang@aol.com > http://www.acdcon.com/ > -- Rob Weinstein Memec Design Services - Phoenix rob_weinstein@memecdesignDOTcom -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 12017
I would talk to Altera directly about this. I know, for example, that if you are moving a Xilinx part to large productiuon runs the Xilinx will produce a metalization layer for an ASIC instead of using the SRAM cells. This effectively gives you an ASIC with the same peoperties as the original FPGA/CPLD. The other companies you may wish to talk to are ORBIT semiconductor as they tout that they can produce ASICs from your FPGA circuits. [StandardDisclaimer] MyOpinionsOnly= ON Gareth Baron John Huang wrote in message <6u8ue8$92b$1@news.seed.net.tw>... >Hello all: > I have a FPGA design in ALTERA 10K20, and now I want to >translate it into ASIC, would you tell me what is important about >translation? does timing will change? how to keep the result current? > >Thanks > John Huang > >Article: 12018
For inexpensive (if not cheap) test adapters: http://www.pcengines.com/test.htm (you could build your own, but it would cost more) -------------------------------------------------------------------- Pascal Dornier pdornier@pcengines.com http://www.pcengines.com Your Spec + PC Engines = Custom Embedded PC Hardware --------------------------------------------------------------------Article: 12019
Hi all, I am using Xilinx XC4028XL-1-PG299 to implement a circuit. The utilization is 100 % (all 1024 CLBs are used). After I download the circuit, I use a IMS Tester to test the chip. I found that for some output pin assignment, my circuit works well, but for another, it just gives wrong result or just no result (all outputs stay zero). I've done post-sim using the .sdf and .vhd files generated by M1 in synopsys and the it works well (not any glitch problems ) and the timing requirement for my circuit is not tight at all. does anyone have the same experience? I've already spent 2 weeks time in debugging this problem but don't have any idea up till now..... Thanks a lot. Rgds, OliverArticle: 12020
Anyone interested in a truely embedded IrDA infrared software protocol stack should check out: http://www.embednet.com This stack is . ANSI C compliant . small (<10K bytes) . efficient ( Zero copy buffer management ) . RTOS ready . simple to port . well tested. . not to forget: inexpensive (<$6k) bobg@triax.com "Pure Embedded Development Determination"Article: 12021
John Huang wrote: > I want to buy a FPGA tool, do you recommand which > one is better, how about Accolade and Aldec? > > John Huang Feel free to evaluate our toolset as well. www.synario.com www.minc.com We support both the Accolade simulator and Model Sim. Drop me an email if you have any questions or would like more info.. jdoherty@synario.com Jay Doherty Minc Washington/Synario Design AutomationArticle: 12022
Andrew Phillips <andrew@scs.ch> wrote in article <36091AC3.C733E671@scs.ch>... > Hi, > > Trying to test some PCI cards - it's not easy to probe signals etc when > the card is stuck inside a normal PC with other PCI cards alongside .. > > Anybody found a better prototype PCI card test system set-up - i.e. one > that allows easy access to both sides of the card being tested? > > Thanks for any pointers ... Take the motherboard out of the case! -andy ---- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories apeters@noao.edu.NOSPAMArticle: 12023
Several FPGA companies have low cost (<$100) starter packages.
XESS has a nice logic development package for $139
Ultra Technology has a processor development board set for $555
http://wwwdnai.com/~jfox/fpgakit.htm
Simon
===============================================================
"adria.bofill" <adria.bofill@imag.fr> wrote:
>I am a newbie in vhdl-fpga.
>
>Does Anyone know free/shareware for fpga design?
>
>Thanx
>
>Adria Bofill
Article: 12024Nick Hartl <"nhartl[no_spam]"@earthlink.net> wrote in article <3604EC4A.70C43A67@earthlink.net>... > > > Philip Freidin wrote: > > > A major advantage of using this batchfile to process your designs, is that > > unlike Xilinx's design manager, it doesn't litter your disk with 10's > > (or 100's ) of megabytes of unwanted files in \rev and \ver directories. > > I continue to be amazed that Xilinx's design manager goes to so much > > effort to maintain all these directories of files for different revisions > > and versions of your design, all of which could be recreated from the > > original design, but the one thing that it won't manage is the revisions > > of the design it-self, which is the only thing that actually needs > > revision control. > > > > *****Check the M1.5 Design Manager there is now a a feature to allow copying of extra files i.e. the design files with each new > version/revision. Menu Design=>Properties =>Version List. > > You are right a rev with out a source is useless. But now one can save the source as well. It's ABOUT TIME! -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories apeters@noao.edu.NOSPAM
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Compare FPGA features and resources
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