Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Take look at www.model.com and under products look at PE for personal Edition. TTFN Rick Filipkiewicz wrote in message <36150046.9FDB1F31@algor.co.uk>... >I'm looking for a reasonably priced Verilog simulator to add to our >Xilinx Foundation+Express package. >So far I can see VeriWell, Chronologic, QuickTurn. Anybody have any >comments on these or others. We could go to $5000 which I assume writes >off Cadence. > >Also looking for a Verilog PCI testbench suite. >Article: 12176
You might also want to look into Exemplar's Leonardo Spectrum. It will allow you do the fpga to asic conversion, timing constraints are considered during the conversion. Kapilan Gareth Baron wrote: > I would talk to Altera directly about this. I know, for example, that if > you are moving a Xilinx part to large productiuon runs the Xilinx will > produce a metalization layer for an ASIC instead of using the SRAM cells. > This effectively gives you an ASIC with the same peoperties as the original > FPGA/CPLD. > > The other companies you may wish to talk to are ORBIT semiconductor as they > tout that they can produce ASICs from your FPGA circuits. > > [StandardDisclaimer] > MyOpinionsOnly= ON > > Gareth Baron > > John Huang wrote in message <6u8ue8$92b$1@news.seed.net.tw>... > >Hello all: > > I have a FPGA design in ALTERA 10K20, and now I want to > >translate it into ASIC, would you tell me what is important about > >translation? does timing will change? how to keep the result current? > > > >Thanks > > John Huang > > > >Article: 12177
try silos from http://www.simucad.com It is really nice. I have been using it for the last three years. Rick Filipkiewicz <rick@algor.co.uk> wrote: >I'm looking for a reasonably priced Verilog simulator to add to our >Xilinx Foundation+Express package. >So far I can see VeriWell, Chronologic, QuickTurn. Anybody have any >comments on these or others. We could go to $5000 which I assume writes >off Cadence. > >Also looking for a Verilog PCI testbench suite. muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 12178
Hi. I have a serious trouble with my Orcad Capture V7.20. I have a design with 5 different diagrams. When I want to save the designs, Orcad reports the following: DSM0006 Unable to save "filename" System error. I the Session log following errors are reported: ERROR [DSM0006] Unable to save "filename" ERROR [DBO3203] System error What is wrong. I need to save the design. My backup file is 3 days old, so I dont want to go back. Sarbjit SinghArticle: 12179
In article <36150046.9FDB1F31@algor.co.uk>, Rick Filipkiewicz <rick@algor.co.uk> wrote: > I'm looking for a reasonably priced Verilog simulator to add to our > Xilinx Foundation+Express package. > So far I can see VeriWell, Chronologic, QuickTurn. Anybody have any > comments on these or others. We could go to $5000 which I assume writes > off Cadence. We're pretty happy with Silos III. > Also looking for a Verilog PCI testbench suite. We bought the Virtual Chips PCI Test Environment in Verilog. It was about $15k plus maintenance, but it proved to be quite valuable when integrating the Xilinx PCI core into some of our clients' designs. It was worth it. We used it with Silos. -- Rob Weinstein Memec Design Services - Phoenix rob_weinstein@memecdesignDOTcom -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12180
The following is a similar but older problem from OrCAD. Basically it says to copy the design pages to a new design. Hope this helps. -- Greg xxxgread@voicenet.com (Remove the 'xxx' to send Email) =========================== OrCAD TechTip - Capture: [CAP0030] Unable to save page Question: When trying to save a design I receive the following error: CAP0030 Unable to save page. Capture appears unable to save the page. This error often occurs when the relevant file is open in another application. Is there a way to fix this? Answer: This error is a possible result of corrupt design data. To fix this, key information in the error-prone design needs to be transferred to a new project. To do this, follow the procedure below: 1. First open the problematic design in Capture. Make sure all of its schematic pages are closed. 2. Create a new design and close the blank schematic page that opens automatically; do not save it. 3. Choose Tile Vertically from the Window menu. Select all of the schematic folders in the original design using the control key. Do not select the Design Cache. 4. Choose Copy from the Edit menu. In the project manager of the new design, select the design file (it has a default name of design1) and choose Paste from the Edit menu. 5. Select your top level schematic folder and choose Make Root from the pop-up menu. 6. Save the new design you just created and discard the faulty one. Questions or comments: E-mail: techsupport@orcad.com (include your registration number in the subject line) Technical Support Phone: (503) 671-9400 Extended Support Option Renewal: (800) 671-9505. OrCAD users with an Extended Support Option (ESO) can find more technical information in our Knowledge Base at http://www.orcad.com/odn/kb. - Please ignore any attachment appearing with this message. - This TechTip is only valid for the current version of the related product. =========================== Sarbjit Singh wrote in message ... >Hi. > >I have a serious trouble with my Orcad Capture V7.20. > >I have a design with 5 different diagrams. > >When I want to save the designs, Orcad reports the following: > >DSM0006 >Unable to save "filename" >System error. > >I the Session log following errors are reported: >ERROR [DSM0006] Unable to save "filename" >ERROR [DBO3203] System error > >What is wrong. I need to save the design. My backup file is 3 days old, so I >dont want to go back. > > >Sarbjit Singh > > > > >Article: 12181
janovetz@tempest.ece.uiuc.edu (Jake Janovetz) writes:
> WHEN WILL THESE PEOPLE GET THE IDEA?!?!
>
> We don't want Windows applications! I need to be able to use Make and
> other CLI features. Ooooh, this really pisses me off.
Didn't you hear at the DAC that scripting is not a virtue but a conceptual
design error ? ;-)
I think they won't wake up until it starts to hurt their pockets and as
long as the market is supply driven, this is not the case. Competition
is relatively low, profit is probably rather high, why bother ?
(Not to mention the relevant Conspiracy Theory :-)
Until enough people who has the knowledge and capabilities feel
*very* pissed off indeed and start to write a GPL-ed synthesis engine,
you will live with whatever they give you, running it on systems they
specify, and paying whatever they ask for it.
Unfortunately, the interest in a synthesis engine is much lower than
that of an OS or a compiler, the know-how is much more arcane and
specialised which makes it unlikely - although you can never know,
the FreeVHDL project is going quite well, AFAIK.
Zoltan
PS: Two very very pissed off individuals are apparently identified,
anyone to join ? :-)
--
+------------------------------------------------------------------+
| ** To reach me write to zoltan in the domain of bendor com au ** |
+--------------------------------+---------------------------------+
| Zoltan Kocsi | I don't believe in miracles |
| Bendor Research Pty. Ltd. | but I rely on them. |
+--------------------------------+---------------------------------+
Article: 12182
I have an immeadiate need for a VHDL consultant to do some work in the
Communications Arena (mods/demods). The VHDL will be done for LUCENT
FPGAs. Anyone interested please contact me. (~several months).
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 12183Ray Andraka wrote: > > walterb wrote: > > > Give me a fast DSP anyday. They are far more flexible. > > I have to disagree here. An FPGA provides a very flexible fabric for hosting > whatever process you decide to implement. Why, you can even implement a > microprocessor if you are so inclined. For the current cost structure, A DSP > microprocessor is still the sensible choice IF it complete the task within the > allotted time. What the FPGA buys you is the capability of customizing your hardware > so that you can compute your algorithm all at once instead of in the sequential > manner done by a CPU. > > The bottom line, is that FPGAs doprovide more flexibility than a CPU, and in many > cases higher performance. However, the design path is very different (hardware vs. > software), so unfamiliarity with implementing algorithms in hardware or with working > within the confines of the FPGA architecture can lead to disappointing results, as > Walt has discovered. Perhaps I should let Walt speak for himself, but I think most people mean flexibility to mean the ability to easily modify or implement algorithms rather than the raw capability of a medium to implement algorithms. In this case I don't think many people will argue that it is easier to design an FPGA than it is to program a DSP for a given algorithm. And certainly it is much easier to change that 32 tap FIR to a 5 biquad IIR on a DSP than an FPGA. I suppose this is a matter of opinion based on what you are familiar with. But I am much more familiar with FPGAs than DSPs and given the choice, I would choose the DSP! -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12184
Sarbjit Singh wrote: > > Hi. > > I have a serious trouble with my Orcad Capture V7.20. > > I have a design with 5 different diagrams. > > When I want to save the designs, Orcad reports the following: > > DSM0006 > Unable to save "filename" > System error. > > I the Session log following errors are reported: > ERROR [DSM0006] Unable to save "filename" > ERROR [DBO3203] System error > > What is wrong. I need to save the design. My backup file is 3 days old, so I > dont want to go back. > > Sarbjit Singh Sarbjit, I would suggest that you not use Orcad for FPGA design. I don't want to get a reputation for Orcad bashing, but I started a project with Orcad working in a Xilinx FPGA and had to abandon Orcad before I was done. This was primarily because of many problems with VHDL synthesis, but there were many other problems such as the one you have found. Orcad seems to deal with these problems by expecting the customer to work around them. Many times Orcad did not consider the problem to be significant enough to fix in the next release. I know this not by assumption, but because I had many conversations with tech support where they told me this. I can't begin to tell you how many times Orcad crashed on my machines (I worked on two different ones during the course of my project). I even was able to send them a schematic which if you deleted a couple of parts at once, would crash. Their response was that this was expected given the "invalid state" this would put the schematic in since the parts were heiarchical port symbols. Orcad's response to the problem of losing data when the program crashed so often was to tell you to save your work often. This is a practice that I learned in the 70's programming on a mainframe. But most people no longer consider this an adequate solution in the 90's. (But then again I get ticked off at my ISP for not being as reliable as my telephone service). So I just gave up on Orcad and started using Xilinx Foundation. It is certainly not bug free. But I am able to move ahead and get my work done. With Orcad, I was stuck for as long as a day at a time trying to find a solution to each problem. I really don't want to be an Orcad basher. If anyone has any positive comments about Orcad I would love to hear them. But I have posted my complaints about Orcad to this board several times before and the only positive comments I have received were that Orcad is OK for board level schematic capture. It would seem that very few people use Orcad for FPGA work, and for a reason! -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12185
Rickman <spamgoeshere4@yahoo.com> wrote in article <3615AB82.19863D60@yahoo.com>... > Sarbjit Singh wrote: > > > > I have a serious trouble with my Orcad Capture V7.20. > > > I would suggest that you not use Orcad for FPGA design. > > I don't want to get a reputation for Orcad bashing, but I started a > project with Orcad working in a Xilinx FPGA and had to abandon Orcad > before I was done. This was primarily because of many problems with VHDL > synthesis, but there were many other problems such as the one you have > found. Orcad seems to deal with these problems by expecting the customer > to work around them. Many times Orcad did not consider the problem to be > significant enough to fix in the next release. I know this not by > assumption, but because I had many conversations with tech support where > they told me this. You are getting Capture and Express mixed up! Capture is strictly a schematic entry program and works quite well at version 7.20. The original poster should also check to make sure that he has sufficient disk space for his output file. Daniel Lang dblx@tyrvos.caltech.edu (but remove the x)Article: 12186
You are right, except in the case of an ASIC containing an EEPROM - that would require some expense to reverse engineer. >it seems easy enough to just pop the top off of the part - a lot of chips that >i've seen, using a regular lab scope, make it easy for you as they write the >chip name in the corner. or if you want to get scientific you can look at the >structure and compare it to the fpga's you have piled up on the bench. for a >few hundreds of dollars you can make a pretty good library. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 12187
I have very good success with OrCAD Express and previously with Capture and Simulation. Yes there have been bugs, but I can't think of any software that I've used that was bug-free. That said, I have only done schematic designs (not HDL) and only on Actel parts and none have been very complicated. -- Greg xxxgread@voicenet.com (Remove the 'xxx' to send Email) Rickman wrote in message <3615AB82.19863D60@yahoo.com>... >Sarbjit Singh wrote: >> >> Hi. >> >> I have a serious trouble with my Orcad Capture V7.20. >> >> I have a design with 5 different diagrams. >> >> When I want to save the designs, Orcad reports the following: >> >> DSM0006 >> Unable to save "filename" >> System error. >> >> I the Session log following errors are reported: >> ERROR [DSM0006] Unable to save "filename" >> ERROR [DBO3203] System error >> >> What is wrong. I need to save the design. My backup file is 3 days old, so I >> dont want to go back. >> >> Sarbjit Singh > >Sarbjit, > >I would suggest that you not use Orcad for FPGA design. > >I don't want to get a reputation for Orcad bashing, but I started a >project with Orcad working in a Xilinx FPGA and had to abandon Orcad >before I was done. This was primarily because of many problems with VHDL >synthesis, but there were many other problems such as the one you have >found. Orcad seems to deal with these problems by expecting the customer >to work around them. Many times Orcad did not consider the problem to be >significant enough to fix in the next release. I know this not by >assumption, but because I had many conversations with tech support where >they told me this. > >I can't begin to tell you how many times Orcad crashed on my machines (I >worked on two different ones during the course of my project). I even >was able to send them a schematic which if you deleted a couple of parts >at once, would crash. Their response was that this was expected given >the "invalid state" this would put the schematic in since the parts were >heiarchical port symbols. > >Orcad's response to the problem of losing data when the program crashed >so often was to tell you to save your work often. This is a practice >that I learned in the 70's programming on a mainframe. But most people >no longer consider this an adequate solution in the 90's. (But then >again I get ticked off at my ISP for not being as reliable as my >telephone service). > >So I just gave up on Orcad and started using Xilinx Foundation. It is >certainly not bug free. But I am able to move ahead and get my work >done. With Orcad, I was stuck for as long as a day at a time trying to >find a solution to each problem. > >I really don't want to be an Orcad basher. If anyone has any positive >comments about Orcad I would love to hear them. But I have posted my >complaints about Orcad to this board several times before and the only >positive comments I have received were that Orcad is OK for board level >schematic capture. It would seem that very few people use Orcad for FPGA >work, and for a reason! > > >-- > >Rick Collins > >redsp@XYusa.net > >remove the XY to email me.Article: 12188
In article <36150046.9FDB1F31@algor.co.uk>, Rick Filipkiewicz <rick@algor.co.uk> wrote: >I'm looking for a reasonably priced Verilog simulator to add to our >Xilinx Foundation+Express package. >So far I can see VeriWell, Chronologic, QuickTurn. Anybody have any >comments on these or others. We could go to $5000 which I assume writes >off Cadence. > >Also looking for a Verilog PCI testbench suite. > My favorite is Silos III, been using it for the last 5 years as my first choice verilog simulator. Daniel K. Elftmann Actel Northeast Field Applications EngineerArticle: 12189
Daniel Lang wrote: > > Rickman <spamgoeshere4@yahoo.com> wrote in article <3615AB82.19863D60@yahoo.com>... > > Sarbjit Singh wrote: > > > > > > I have a serious trouble with my Orcad Capture V7.20. > > > > > I would suggest that you not use Orcad for FPGA design. > > > > I don't want to get a reputation for Orcad bashing, but I started a > > project with Orcad working in a Xilinx FPGA and had to abandon Orcad > > before I was done. This was primarily because of many problems with VHDL > > synthesis, but there were many other problems such as the one you have > > found. Orcad seems to deal with these problems by expecting the customer > > to work around them. Many times Orcad did not consider the problem to be > > significant enough to fix in the next release. I know this not by > > assumption, but because I had many conversations with tech support where > > they told me this. > > You are getting Capture and Express mixed up! Capture is strictly a schematic > entry program and works quite well at version 7.20. The original poster should > also check to make sure that he has sufficient disk space for his output file. > > Daniel Lang dblx@tyrvos.caltech.edu (but remove the x) I am not sure why you say I am mixing the two. Some of my problems were with the schematic capture part of the Orcad package, most were with the VHDL synthesis engine. But the schematic capture is the same between Capture and Express. Although I had fewer problems with schematic capture, I still had fatal problems. The one I mentioned above kept me down for over a day while I sent the files to Orcad and they explored the problem. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12190
Hi Has anyone out there in FPGA land ever used or attempted to use the 74297 Phase Locked Loop function that can be found in the standard Maxplus2 libraries? My application is to syncronise the VD (50Hz) and HD (15.6 KHz) inputs of a CCIR (european standard) video camera to the 50 Hz mains supply we have here in the U.K. I have been told that a lock range from 49 to 51 Hz should be adequate, and that the mains frequency only ever changes very slowly. The camera VD & HD signal tolerance is within 10% of nominal. These frequencies are relativly low in FPGA terms, so I'd thought a FPGA PLL would be possible. However the Altera help file for the function is terse, and the Texas Instruments databook only tells you the basics. Any pointers, experiences or URL's would be greatly welcomed. This is a one-off application, so I do not think my Altera FAE is likely to spend a great deal of time on my behalf. Cheers -- Steve Dewey Steve@s-deweynospam.demon.co.uk remove "nospam" for mail Too boring to have an interesting or witty .sig file.Article: 12191
I would also think that for a given algorithm and performance, an FPGA would run at a much lower power than a DSP. OTOH if one has a DSP in a product, one can usually get the DSP to do a lot of other stuff, thus saving a microcontroller etc. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 12192
You are describing Orcad Capture and probably the Express stuff. These are Orcad's Windoze offerings, and they started horrendously buggy, and got better only slowly. I think they might get there in a few years' time. I wonder how good the older and virtually bug-free SDT/386 would be for FPGA work. I have been using SDT3, and since ~ 1995 SDT/386, and never had one crash, or any other problem I recall. The only drawback is the 640x480 video in the NT4 DOS box, although 800x600 is possible with certain video cards. The probably biggest problem is simulation. Unlike board-level design, this is really necessary for FPGA work, and VST was never a well debugged product. I never tried VST/386 though. >I really don't want to be an Orcad basher. If anyone has any positive >comments about Orcad I would love to hear them. But I have posted my >complaints about Orcad to this board several times before and the only >positive comments I have received were that Orcad is OK for board level >schematic capture. It would seem that very few people use Orcad for FPGA >work, and for a reason! -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 12193
Orcad Help implies a common reason for this is the file is open by another application program. Might this be your case? Russell May "Sarbjit Singh" <singh@bk.dk> wrote: >Hi. > >I have a serious trouble with my Orcad Capture V7.20. > >I have a design with 5 different diagrams. > >When I want to save the designs, Orcad reports the following: > >DSM0006 >Unable to save "filename" >System error. > >I the Session log following errors are reported: >ERROR [DSM0006] Unable to save "filename" >ERROR [DBO3203] System error > >What is wrong. I need to save the design. My backup file is 3 days old, so I >dont want to go back. > > >Sarbjit Singh > > > > >Article: 12194
yes, of course. the response i gave was simply to derek's comment that by removing the chip id from the package, it would provide security and not even let people know if it's an asic, standard product, or programmable. getting the actual design content, obviously, is a bit more work. rk Peter wrote: > You are right, except in the case of an ASIC containing an EEPROM - > that would require some expense to reverse engineer. > rk wrote: > > >it seems easy enough to just pop the top off of the part - a lot of chips that > >i've seen, using a regular lab scope, make it easy for you as they write the > >chip name in the corner. or if you want to get scientific you can look at the > >structure and compare it to the fpga's you have piled up on the bench. for a > >few hundreds of dollars you can make a pretty good library. Derek Palmer wrote: > <snip> > In the end, the only security scheme I've seen > work consistently is to ship parts with no vendor lablel only a customer > designs #. This way the people trying to copy the device have not idea if > it's programmable, an ASIC or standard product. Simple and very effective.Article: 12195
Announcing PCISIM ----------------- PCISIM is a C++ class library I have developed as part of my University thesis for the purpose of PCI traffic simulation. The core logic library provides synchronous logic simulation with 6 logic levels (low, high, unknown, high-z, pull high, pull low). using the core logic simulation classes, I have defined the following highly configurable classes: * PCI Target * PCI Master * PCI Arbiter The classes are fully configurable (by deriving new classes from those base classes and overriding the default behavior). Take a look at: http://www.geocities.com/SiliconValley/Campus/3216/ Please send your comments to udif@usa.net Udi FinkelsteinArticle: 12196
Do you know much about PLLs? What are you using as your VCO? (for TV work I recommend a VCXO). The narrow lock range suggests you might want a loop filter with a 1-2 Hz cutoff. Which means a lock time of seconds (without tricks). You need to read the 4046 (CMOS) data sheet as a starting point. Some books might be a good idea as well. Motorola has some good PLL refrences as does National semi. Simon =========================================================== Steve@nospams-dewey.demon.co.uk (Steve Dewey) wrote: >Hi > >Has anyone out there in FPGA land ever used or attempted to use the 74297 >Phase Locked Loop function that can be found in the standard Maxplus2 libraries? > >My application is to syncronise the VD (50Hz) and HD (15.6 KHz) inputs of a >CCIR (european standard) video camera to the 50 Hz mains supply we have here in >the U.K. I have been told that a lock range from 49 to 51 Hz should be adequate, >and that the mains frequency only ever changes very slowly. The camera VD & HD >signal tolerance is within 10% of nominal. > >These frequencies are relativly low in FPGA terms, so I'd thought a FPGA PLL >would be possible. However the Altera help file for the function is terse, and >the Texas Instruments databook only tells you the basics. > >Any pointers, experiences or URL's would be greatly welcomed. > >This is a one-off application, so I do not think my Altera FAE is likely to >spend a great deal of time on my behalf. > >Cheers >-- >Steve Dewey >Steve@s-deweynospam.demon.co.uk >remove "nospam" for mail >Too boring to have an interesting or witty .sig file. > Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 12197
In article <3616bd9c.1458368@news.megsinet.net> msimon@tefbbs.com writes: > Do you know much about PLLs? I've done a couple, and a Video Genlock, but that was just implementing the Elantec application/demo circuit. > What are you using as your VCO? (for TV work I recommend a VCXO). > The 74297 Datasheet argues that the k-counter is in effect the VCO. > The narrow lock range suggests you might want a loop filter with a > 1-2 Hz cutoff. > > Which means a lock time of seconds (without tricks). > The frequency of the mains only changes very slowly, as it is linked to the speed of rotation of all the generators: _LOTS_ of inertia. A lock time of seconds will be fine. > You need to read the 4046 (CMOS) data sheet as a starting point. > Some books might be a good idea as well. Motorola has some good PLL > refrences as does National semi. > > Simon Yep, The Art of Electronics has a very good section on designing PLLs based on the 4046. The Motorola databook fills in the gaps. I know I can do this using a conventional 4046 based approach. However I would still use a PLD for the divider and to mop up any other logic I need. Seeing the 74297 function listed in Altera's Maxplus2 library, I was wondering whether I could implement an all-digital version, cut down on components and gain some experience. -- Steve Dewey Steve@s-deweynospam.demon.co.uk Too boring to have an interesting or witty .sig file.Article: 12198
You can download from Altera site (http://www.altera.com/) a free entry level version of their software. JoseArticle: 12199
The topic of managing VHDL models and libraries has come up from time to time on comp.lang.vhdl. Traditionally, the VHDL simulation tools have done a poor job of helping designers cope with the issues. Janick Bergeron, the VP of Technical Wisdom at Qualis Design, has written a 10-page white paper that puts the whole problem into perspective, and offers real solutions and handy suggestions for VHDL designers. Starting with a quick primer on Makefiles, Janick dispels the myths and mystery of compilation dependencies, identifies solid ways of designing Makefiles for models and libraries, and identifies sound strategies for minimizing compilation dependencies. The white paper is full of useful methodology notes you'll likely find indispensable. If you're a VHDL designer, it's worth your time. Check out Janick's white paper in the Qualis Library. You can access it at: http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=mb004 Michael
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z