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Back in January, there was a discussion about floating nodes in xilinx 4000E series ram. There is a problem when the maximum value of Twps is exceeded. From dejanews: Ryan Herbst wrote: > It is my understanding that if the write clock signal is held high > for more than a millisecond, permanent damage to the device can be > caused. Peter Alfke replied with some figures for working out the extra power consumption, but said: > I will post the exact value later, right now I quote from memory I have the need to use rams in this way, and based on Peter's figures my excess power consumption will be 144mW, which is tolerable in a HQ208 package. Could we have the exact figures please, so that I can be sure my design is ok? Thanks, Allan. Peter's earlier reply follows: >The problem on XC4000E stems from a dynamic node in the write circuitry. >After the active write edge, the addressing and data lines in the RAM >are not held at a dc level, but can float. This does not affect the >write operation in any way, but it can result in poorly defined >cross-current when the input to an inverter drifts through the >half-supply-voltage range. The max current per inverter is something >like 100 microamps ( I will post the exact value later, right now I >quote from memory ). Each CLB has 18 of such nodes ( difficult to >explain why 18, please believe me ). >For a short while ( milliseconds ) after parking write clock at the >"forbidden" level, each CLB configured as a synchronous RAM can thus >conduct up to 1.8 mA, but he current disappears again as the nodes drift >away from the "bad" voltage. There is no local problem with this >current. Transistors and metal can carry that current forever, and the >localized heating is minuscule. The problem comes when large numbers of >CLBs are used this way.Article: 11476
Our "garage" startup is developing a new piece of consumer electronics hardware for which we need an important piece of IP. We are looking for someone with very strong skills in modulation theory who can create QPSK and/or simplified QAM modulator and demodulator logic in an FPGA with external DAC and ADC for ultimate reduction to a custom ASIC. While this product is vaguely related to the settop box space, it is not a digital cable or sattelite reciever. This project has not yet been venture funded. We are fininshing up the first phase of the hardware but need this additional functionality. You would be offered defered cash compensation and an equity position in the project. Our company has several patents pending and believes the product's technology will be one of the core elements in the next generation of digital home technology. If you have the resources to work uncompensated for a period of time, and the inclination to work on something amazingly cool, drop me a line at hank777@aol.com.Article: 11477
Sounds like the pinout is not being constrained properly. Check the syntax of your .ucf file and check in the reports file that it actually put the pins where you want them. This would explain why simulation works, and why you get different results on each compilation. Just a thought. Mark. Remove NOSPAM_ from email address watm <watm@asterix.ist.utl.pt> wrote in article <35D94D41.41066AFF@asterix.ist.utl.pt>... > I'm making a project using Xilinx tools and one weird thing has > happened : > > I designed the blocks in the shematic, simulated them, checked that > everything was like i expected to be and .... when i loaded the code > into the FPGA, nothing happened the expected ! > This very strange, because it din't happened one or two times but > several, it simulates one thing, and relly happens another. Sometimes > entirely different. > > I am optimizing the design to area, i. e., making Xilinx fit the > code into the FPGA (XC4006E) > > If someone can give me a hel, i would appreciated .... > > Thanks in advance, > Rui Pinto > >Article: 11478
I responded to this just to see what they meant by "BIG MONEY" and they didn't even have the courtesy to e-mail a reply! Anyone else inquite about this? Austin Franklin darkroom@ix.netcom.com The Employment Solution <ottreply@tes.net> wrote in article <35D429B2.6A01@tes.net>... > The Employment Solution > > We are currently seeking Hardware Designers (2-4 Openings Available). > The ideal candidate will possess the following: ......Article: 11479
Mark makes an excellent suggestion regarding pin out's not being correct. When a design is so off the mark, usually, the problem is a simple one with dramatic results! One other thing to check is that your design meets its timing goals. You should at least put in a "PERIOD" constraint and verify, via timing analyzer, that all timing constraints have been met. NOTE1 (for everyone): At least up to M1.4, the PERIOD constraint does not constrain FFS to PADS, you need to use the OFFSET constraint there. NOTE2: Other things to check could include unmanaged asynchronous activity but you sound like your problems are more severe than that. -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 watm wrote: > > I'm making a project using Xilinx tools and one weird thing has > happened : > > I designed the blocks in the shematic, simulated them, checked that > everything was like i expected to be and .... when i loaded the code > into the FPGA, nothing happened the expected ! > This very strange, because it din't happened one or two times but > several, it simulates one thing, and relly happens another. Sometimes > entirely different. > > I am optimizing the design to area, i. e., making Xilinx fit the > code into the FPGA (XC4006E) > > If someone can give me a hel, i would appreciated .... > > Thanks in advance, FAX: (908) 996-0817Article: 11480
Would the assignment be in another process perhaps? Matt On Tue, 18 Aug 1998 Joel.Kolstad@USA.Net wrote: > I've got this brief snippet of code here: > > -- Generate the other strobes > process(Reset,Clk) > begin > if (Clk'Event and Clk='1') then > Strobes(1)<=Strobes(0); Strobes(2)<=Strobes(1); Strobes(3)<=Strobes(2); > Strobes(6)<=Strobes(5); Strobes(7)<=Strobes(6); > end if; > end process; > > ...that Synopsys' FPGA Express complains: > > Warning: The net '/StrobeGen/Strobes<1>' has more than one driver. > (FE-CHECK-5) > > It does this for all 5 signals that I'm using above. I can guarantee that, > other than the code above, no process assigns a value to Strobes 1, 2, 3, 6, > or 7. So just what is it unhappy about? Does anyone know? > > Thanks... > > ---Joel Kolstad > Joel.Kolstad@USA.Net > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum > >Article: 11481
This week's Tech Note article in the PLD Design Center describes the advantages of the in-system programming feature now present on many PLDs. Check out the site. http://www.edtn.com/pld Murray Disman Editor PLD Design CenterArticle: 11482
1998 IEEE International Workshop on
MEMORY Technology, Design, and Testing
August 24-25, 1998
Fairmont Hotel
San Jose, California
Web Page: www.cs.tamu.edu/faculty/fmeyer/mtdt98.html
For general information contact me before the weekend:
Jackie Meyer
fmeyer@cs.tamu.edu
Hotel reservation by: There may still be rooms available
Advance registration by: Register at the site now
Session Topics
Embedded DRAM
Embedded Memory Design Aids
Memory Repair
Content Addressable Memories
Algorithms and Testing Techniques
Unique Fault Models
Special Tutorial Sessions
DRAM Fault Modeling
SRAM Acceptance Testing
Article: 11483I am an undergraduate in Nanyang Technological University, Singapore. Recently, I am doing my final year project to implement turbo decoder on FPGA. I started from the schematic drawing in Design Architecture of MENTOR GRAPHIC software. Now, i want to generate the VHDL code from the schematic drawn. Following are the question that i met: 1. I use the and2 component from GEN_LIB. VHDL compiler complain that the output pin of that and2 use a reversed name of OUT. How to i change that? Thanks in advance for those who can help me. yowchingArticle: 11484
I am an undergraduate in Nanyang Technological University, Singapore. Recently, I am doing my final year project to implement turbo decoder on FPGA. I started from the schematic drawing in Design Architecture of MENTOR GRAPHIC software. Now, i want to generate the VHDL code from the schematic drawn. Following are the question that i met: 1. I use the and2 component from GEN_LIB. VHDL compiler complain that the output pin of that and2 use a reversed name of OUT. How to i change that? Thanks in advance for those who can help me. yowchingArticle: 11485
I am an undergraduate in Nanyang Technological University, Singapore. Recently, I am doing my final year project to implement turbo decoder on FPGA. I started from the schematic drawing in Design Architecture of MENTOR GRAPHIC software. Now, i want to generate the VHDL code from the schematic drawn. Following are the question that i met: 1. I use the and2 component from GEN_LIB. VHDL compiler complain that the output pin of that and2 use a reversed name of OUT. How to i change that? Thanks in advance for those who can help me. yowchingArticle: 11486
I am an undergraduate in Nanyang Technological University, Singapore. Recently, I am doing my final year project to implement turbo decoder on FPGA. I started from the schematic drawing in Design Architecture of MENTOR GRAPHIC software. Now, i want to generate the VHDL code from the schematic drawn. Following are the question that i met: 1. I use the and2 component from GEN_LIB. VHDL compiler complain that the output pin of that and2 use a reversed name of OUT. How to i change that? Thanks in advance for those who can help me. yowchingArticle: 11487
I am an undergraduate in Nanyang Technological University, Singapore. Recently, I am doing my final year project to implement turbo decoder on FPGA. I started from the schematic drawing in Design Architecture of MENTOR GRAPHIC software. Now, i want to generate the VHDL code from the schematic drawn. Following are the question that i met: 1. I use the and2 component from GEN_LIB. VHDL compiler complain that the output pin of that and2 use a reversed name of OUT. How to i change that? Thanks in advance for those who can help me. yowchingArticle: 11488
Hi all, Got a question.... Does anyone know where I can source the following tools ALL running under LINUX (Direct or under Xwindows). The TMS320C series of tools (ie. the C compiler, the assembler, linker etc etc) The Xilinx FPGA Implementation tools. The XDS510 JTAG Emulator tools. I have all the above for Windoze, but I have just about had enough of this awfull O/S... I would like some stability in my life, and I am fairly sure that LINUX is the way to go. (I used to run Linux all the time - it never once crashed on me). All I want to do is write code on a system that is stable for more that 20 minutes at a time. Hoo Hummm Yours wishingly.... Tony -- Sent By Tony Cooper. email: tony.cooper@virgin.net Allow at least 10 working minutes for reply. ;)Article: 11489
Maybe the compiler is getting confused with the Reset signal in the sensitivity list. Try using the Reset in the code to reset all the registers, or simply remove it from the sensitivity list. Some synthesizers get confused very easily if the form of the clocked process is not exactly what it expects. (Note however that this will simulate OK because it's valid VHDL, it just won't be synthesizable). Regards, Mark. Remove NOSPAM_ from email address Joel.Kolstad@USA.Net wrote in article <6ral4j$9dv$1@nnrp1.dejanews.com>... > I've got this brief snippet of code here: > > -- Generate the other strobes > process(Reset,Clk) > begin > if (Clk'Event and Clk='1') then > Strobes(1)<=Strobes(0); Strobes(2)<=Strobes(1); Strobes(3)<=Strobes(2); > Strobes(6)<=Strobes(5); Strobes(7)<=Strobes(6); > end if; > end process; > > ...that Synopsys' FPGA Express complains: > > Warning: The net '/StrobeGen/Strobes<1>' has more than one driver. > (FE-CHECK-5) > > It does this for all 5 signals that I'm using above. I can guarantee that, > other than the code above, no process assigns a value to Strobes 1, 2, 3, 6, > or 7. So just what is it unhappy about? Does anyone know? > > Thanks... > > ---Joel Kolstad > Joel.Kolstad@USA.Net > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum >Article: 11490
Does anyone know of any VHDL implementation of the decoding of a manchester-encoded bitstream. If no does anyone have any suggestion of how to attack teh problem? Sinecerely RezaArticle: 11491
On Tue, 18 Aug 1998 01:24:35 GMT, Joel.Kolstad@USA.Net wrote: >It does this for all 5 signals that I'm using above. I can guarantee that, >other than the code above, no process assigns a value to Strobes 1, 2, 3, 6, >or 7. So just what is it unhappy about? Does anyone know? how do you assign to Strobes 0, 4, and 5? it's likely that this assignment has created drivers for the *entire* strobes array (if, for example, you're assigning to a name which isn't static). evanArticle: 11492
http://www.girliegirl.com http://www.sassygirl.com http://www.world-premiere.com these sites are really starting to piss me off. they're regularly posting to all 8 newsgroups that i'm on. i've checked them out, and they're all related to each other. the information i have is as follows: the administrative and technical contacts (according to internic), for all 3 sites, are: ursula major ursulamajor@hotmail.com mike shevenell mike@www.covesoft.com todd jennings webmaster@cybertiger.net todd jennings runs a company that provides hosting for adolescent services. my guess is that all 3 sites are on his machines, at this address: Digital Illusions 590 Centerville Road Suite 288 Lancaster, PA 17601 US (+1) 717 898 1443 they also have an office at: 40 Heather Lane Terryville, CT 06786 US (+1) 860 585 8637 he can also be reached at webmaster@digitalillusions.com. http://www.digitalillusions.com also thoughtfully provides some personal details for mr. jennings. he claims that his company has connections to MAE east, MAE west, and UUnet. i can't find his upstream provider, but i would guess that it's Icon CMT corporation (contact@icon.com). give 'em hell. and perhaps one of you could come up with an email address for the police department in lancaster, PA.Article: 11493
I tried to experiment with these functionnalities but the compiler kept saying that the chip didn't support the features. Someone from Altera told me that it was only available with the 10K100DX I'm quite surprised because it's not mentionned anywhere in the databook Any hint ? -- Nicolas MATRINGE DotCom SA Conception électronique 16 rue du Moulin des Bruyères Tel: 00 33 1 46 67 51 00 92400 COURBEVOIE Fax: 00 33 1 46 67 51 01 mail reply : remove one dot from the address (guess which :-)Article: 11494
I wrote: > > I tried to experiment with these functionnalities but the compiler kept > saying that the chip didn't support the features. > Someone from Altera told me that it was only available with the 10K100DX > I'm quite surprised because it's not mentionned anywhere in the databook > > Any hint ? I have been confirmed by an Altera app. engineer : no ClockLock (and therefore no ClockBoost) in any Flex10K but the 10K100DX Nicolas MATRINGE DotCom SA Conception électronique 16 rue du Moulin des Bruyères Tel: 00 33 1 46 67 51 00 92400 COURBEVOIE Fax: 00 33 1 46 67 51 01 mail reply : remove one dot from the address (guess which :-)Article: 11495
Does anyone know what the pinouts for the Xilinx Parallel Xchecker cable are ? I have an extra parallel cable laying about that I want to use under Linux and since I can't use it on my NT box, it seems like a shame to toss the cable. See ya, -ingo -- /* Ingo Cyliax, cyliax@derivation.com, Tel/Fax: 760-431-1400/1484 */Article: 11496
I want to implement 4PPM coding in ABEL, if someone can give a help i would appreciated. Thanks in advance, Jose CardosoArticle: 11497
Thanks for the help. The problem was not the pinouts, i checked and everything was normal. Ed MacCauley was right about the timing goals, when i implemented the design using the "Balanced" optimization mode, the expected results came up. However my FPGA is almost full and the only possible option in the optimization mode is "Area", because otherwise the design don't fit in the FPGA. My question is : how do i specify the time constraints in the Xilinx ? What values do i specify ? Thanks in advance, Rui Pinto PS: If someone knows where i can order a FPGA XC4008/10, to be delivered as soon as possible, i would also appreciated. Ed McCauley wrote: > Mark makes an excellent suggestion regarding pin out's not being > correct. When a design is so off the mark, usually, the problem is a > simple one with dramatic results! > > One other thing to check is that your design meets its timing goals. > You should at least put in a "PERIOD" constraint and verify, via timing > analyzer, that all timing constraints have been met. > > NOTE1 (for everyone): At least up to M1.4, the PERIOD constraint does > not constrain FFS to PADS, you need to use the OFFSET constraint there. > > NOTE2: Other things to check could include unmanaged asynchronous > activity but you sound like your problems are more severe than that. > > -- > Ed McCauley > Bottom Line Technologies Inc. > Specializing Exclusively in Xilinx Design, Development and Training > Voice: (500) 447-FPGA, (908) 996-0817 > > watm wrote: > > > > I'm making a project using Xilinx tools and one weird thing has > > happened : > > > > I designed the blocks in the shematic, simulated them, checked that > > everything was like i expected to be and .... when i loaded the code > > into the FPGA, nothing happened the expected ! > > This very strange, because it din't happened one or two times but > > several, it simulates one thing, and relly happens another. Sometimes > > entirely different. > > > > I am optimizing the design to area, i. e., making Xilinx fit the > > code into the FPGA (XC4006E) > > > > If someone can give me a hel, i would appreciated .... > > > > Thanks in advance, > > FAX: (908) 996-0817 >Article: 11498
On Wed, 19 Aug 1998 13:38:04 +0200, "Reza Bohrani" <Reza.Bohrani@timespace.se> wrote: >Does anyone know of any VHDL implementation of the decoding of a >manchester-encoded bitstream. If no does anyone have any suggestion of how >to attack teh problem? > >Sinecerely >Reza > You might try "Manchester Decoder in 3 CLBs" near the bottom of <http://www.xilinx.com/apps/4000.htm#appnotes>. It shows a schematic diagram instead of VHDL, but it's a start. It looks a little over-simplistic but it should work okay if you don't have any noise. I have a fairly elaborate program for a Manchester II encoder-decoder written in Altera AHDL, but I have not tested it yet (probably won't for a while because the project has been shelved) and my Engineering Director might object to me giving it out. Russ MayArticle: 11499
do you know how to create a batch file in win95 to flood their email without having the return e-mail address on the message? ac@cd.com wrote in message <35dabad8.7932740@news.dial.pipex.com>... >http://www.girliegirl.com >http://www.sassygirl.com >http://www.world-premiere.com > >these sites are really starting to piss me off. they're regularly >posting to all 8 newsgroups that i'm on. i've checked them out, and >they're all related to each other. the information i have is as >follows: > >the administrative and technical contacts (according to internic), for >all 3 sites, are: > >ursula major ursulamajor@hotmail.com >mike shevenell mike@www.covesoft.com >todd jennings webmaster@cybertiger.net > >todd jennings runs a company that provides hosting for adolescent >services. my guess is that all 3 sites are on his machines, at >this address: > >Digital Illusions >590 Centerville Road Suite 288 >Lancaster, PA 17601 >US >(+1) 717 898 1443 > >they also have an office at: > >40 Heather Lane >Terryville, CT 06786 >US >(+1) 860 585 8637 > >he can also be reached at webmaster@digitalillusions.com. > >http://www.digitalillusions.com also thoughtfully provides >some personal details for mr. jennings. he claims that his >company has connections to MAE east, MAE west, and UUnet. >i can't find his upstream provider, but i would guess that >it's Icon CMT corporation (contact@icon.com). > >give 'em hell. and perhaps one of you could come up with >an email address for the police department in lancaster, PA. >
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